CN101211328B - High-performance programmable logic system interface and chip - Google Patents

Abstract

The invention provides a chip of a high-performance programmable logic system interface, which comprises: a first internal device, a second internal device and a bus controller. The first internal device is located in the chip and communicates with an external device through a first set of internal buses and a first set of external buses. The second internal device is located in the chip and communicates with the external device through a second set of internal buses and a second set of external buses. The bus controller is used for controlling the first group of internal buses, the first group of external buses, the second group of internal buses and the second group of external buses. The first internal device and the second internal device communicate with the bus controller at the same time.

Description

High performance programmable logic system interface and chip

technical field

The invention relates to an interface device, in particular to a high-performance programmable logic system interface.

Background technique

The communication between integrated circuit chips can be carried out by using parallel bus or serial bus data transmission method according to different system applications. When both chips have parallel buses, the general-purpose input and output (GPIO) interface is generally used to send signals. Although GPIO has the advantage of greater flexibility, its disadvantage is that it is slower. Therefore, another parallel and programmable interface has been developed, which combines the advantages of GPIO with the advantages of serial bus.

The block diagram shown in FIG. 1 is used to illustrate the above transmission system. In FIG. 1, the data transmission system 100 includes an integrated circuit chip 110 and an external device 120, wherein the external device 120 can be, for example, a printer, a video recorder, a digital camera, a storage device or other computer peripheral devices . The integrated circuit chip 110 includes an internal device 130 and a bus master 140 , wherein the internal device 130 can be, for example, a first-in-first-out (FIFO) device or a register. IC chip 110 further includes data buses 132 and 122 , address bus 124 , control buses 136 and 126 , and ready buses 138 and 128 . The internal device 130 communicates with the external device 120 through these buses.

The data buses 132 and 122 are bidirectional buses, but only one direction can be transmitted at the same time, that is, only read or write can be selected at the same time. The width of the data buses 132 and 122 can be programmed, for example, can be programmed to transmit data of one byte or one word at the same time. The address bus 124 is used for the external device 120 , and is used to transmit addresses that can access memory or registers of the external device 120 . The control buses 136 and 126 transmit control signals for writing, reading or selecting the external device 120 . The buses 138 and 128 are prepared to transmit handshake signals to control the signals from the internal device 130 and the external device 120 to the bus controller 140 respectively. For example, if the external device 120 is a FIFO device, the buses 138 and 128 are ready to transmit full/empty signals.

Since the data buses 132 and 122 in FIG. 1 are half duplex, the operation mode of the system 100 can be divided into a data writing mode and a data reading mode. In the data writing mode (that is, write data from the internal device 130 to the external device 120), the data bus 132 sends signals from the internal device 130 to the bus controller 140, and the data bus 122 sends signals from the bus controller 140 to the external device 120 . In the data read mode (that is, the internal device 130 reads data from the external device 120), the data bus 122 transmits a signal from the external device 120 to the bus controller 140, and the data bus 132 transmits a signal from the bus controller 140 to the internal device 130.

FIG. 2 depicts an example of a waveform of a bus transmission signal. A bus transmission cycle has 8 states, 1 of which is an idle state, and 7 are transfer states. In the idle state, all buses are inactive, and in the transfer state, the data, address, and control buses can be programmed separately. It can be seen from FIG. 2 that because the bus is a half-duplex bus, it can only transmit data in one direction at the same time, but cannot read and write data at the same time.

Therefore, it is necessary to provide a full-duplex bus to provide a mechanism for receiving and transmitting data at the same time.

Contents of the invention

In view of the problems existing in the prior art, the main purpose of the present invention is to provide a high-performance programmable logic system interface for providing bidirectional and simultaneous transmission.

According to one aspect of the present invention, a chip with a high-performance programmable logic system interface is provided, including: a first internal device, a second internal device, a bus controller and an external control bus. Wherein, the first internal device is located in the chip, and communicates with an external device through a first group of internal buses and a first group of external buses. The second internal device is located in the chip, and communicates with the external device through a second set of internal buses and a second set of external buses. The bus controller is used for controlling the first group of internal buses, the first group of external buses, the second group of internal buses and the second group of external buses. The external control bus is used to communicate with the external device and the bus controller. Wherein, the first internal device and the second internal device communicate with the bus controller at the same time, and the first internal device and the second internal device are respectively responsible for sending and receiving data. Moreover, the first internal device and the second internal device communicate with the external device at the same time.

According to another aspect of the present invention, a high-performance programmable logic system interface is provided. The high-performance programmable logic system interface is set in a chip, and the chip includes a first internal device, a second internal device, a bus controller and an external control bus. Wherein, the high-performance programmable logic system interface includes: a first group of internal buses used to communicate with the first internal device and the bus controller, a first group of external buses used to communicate with the bus controller and an external device, and used to communicate with the bus controller and an external device. A second set of internal buses for communicating the second internal device with the bus controller, a second set of external buses for communicating the bus controller with external devices, and an external control bus for communicating the external devices with the bus controller . Wherein, the first internal device and the second internal device communicate with the bus controller at the same time, and the first internal device and the second internal device are respectively responsible for sending and receiving data. Moreover, the first internal device and the second internal device communicate with the external device at the same time.

Description of drawings

Figure 1 illustrates a conventional data transmission system;

FIG. 2 depicts an example of a waveform of a conventional bus transmission signal;

FIG. 3 illustrates a data transmission system according to an embodiment of the present invention;

Fig. 4 is a data transmission system of a first-in-first-out active mode according to an embodiment of the present invention;

5 is a data transmission system of a micro-processing unit active mode according to an embodiment of the present invention;

FIG. 6 is a timing diagram of bus transmission signals according to the embodiment shown in FIG. 4:

FIG. 7 is a timing diagram of bus transmission signals according to the embodiment shown in FIG. 5 .

Description of figure number:

100, 300, 400, 500 data transmission system

110, 310, 410, 510 chip

120, 320, 420, 520 external device

122, 132, 322, 324, 332, 334, 422, 424, 462, 472 data bus

124, 321, 323, 421, 423, 521, 523 address bus

126, 136, 326, 336, 426, 466, 476, 526, 566, 576 control bus

128, 138, 328, 338, 428, 468, 478 ready bus

130, 330, 430, 530 internal device

140, 340, 440, 540 bus controller

460, 470, FIFO device

560, 570 buffer

Detailed ways

The invention discloses a high-performance programmable logic system interface and system. In order to make the description of the present invention more detailed and complete, reference may be made to the following description together with the diagrams of FIGS. 3 to 7 . However, the devices, systems and program steps described in the following embodiments are only used to illustrate the present invention, and are not intended to limit the scope of the present invention.

Referring to FIG. 3 , a data transmission system 300 according to an embodiment of the present invention is disclosed. The data transmission system 300 includes an integrated circuit chip 310 and an external device 320 , wherein the external device 320 can be, for example, a printer, a video recorder, a digital camera, a storage device or other computer peripheral devices. The integrated circuit chip 310 includes an internal device 330 and a bus master 340 , wherein the internal device 330 can be, for example, a first-in-first-out (FIFO) device or a register. The integrated circuit chip 310 further includes data buses 332 , 334 , and a control bus 336 for communicating with the internal device 330 and the bus controller 340 . A ready bus 338 may optionally be included between the internal device 330 and the bus controller 340 for transmitting handshake signals to control data transmission between the internal device 330 and the bus controller 340 . In addition, the IC chip 310 also includes data buses 322 and 324 , address buses 321 and 323 , a control bus 326 , and a ready bus 328 for communicating with the external device 320 and the bus controller 340 . The ready bus 328 is used to transmit handshake signals to control signals from the external device 320 to the bus controller 340 . The width of the above-mentioned bus can be programmed, for example, it can be programmed to transmit a byte or a word signal at the same time. The internal device 330 includes at least two storage units, such as registers or memories, one of which is responsible for writing to the external device 320 , and the other is responsible for reading from the external device 320 . Therefore, the internal device 330 and the external device 320 can communicate with the bus controller 340 at the same time. Through two data buses 322 and 324 and two address buses 321 and 323 between the bus controller 340 and the external device 320, the internal device 330 and the external device 320 can simultaneously read and write with the external device 320 Input action, and achieve the purpose of full duplex.

FIG. 4 is a data transmission system 400 in a FIFO transaction mode according to an embodiment of the present invention. The data transmission system 400 includes an integrated circuit chip 410 and an external device 420 . The integrated circuit chip 410 includes an internal device 430 and a bus controller 440 , wherein the internal device 430 includes a first FIFO device 460 and a second FIFO device 470 . The first FIFO device 460 communicates with the bus controller 440 via the data bus 462 , the control bus 466 and the ready bus 468 . The second FIFO device 470 communicates with the bus controller 440 via a data bus 472 , a control bus 476 and a ready bus 478 . In addition, the external device 420 and the bus controller 440 communicate with each other through the data buses 422 and 424, the address buses 421 and 423, the control bus 426, and the ready bus 428, wherein the data buses 422 and 424 are different buses and can be used individually. control, and the address buses 421 and 423 are also different buses and can be individually controlled. Because there are two sets of independent data and address buses, and the first FIFO device 460 and the second FIFO device 470 are responsible for sending and receiving data respectively, the internal device 430 can simultaneously read and write to the external device 420 , to achieve the purpose of full duplex.

FIG. 5 is a data transmission system 500 in an MCU transaction mode according to an embodiment of the present invention. The data transmission system 500 includes an integrated circuit chip 510 and an external device 520 . The integrated circuit chip 510 includes an internal device 530 and a bus controller 540 , wherein the internal device 530 is a micro control unit (MCU) including a first register 560 and a second register 570 . The first register 560 communicates with the bus controller 540 through a data bus 562 and a control bus 566 . The second register 570 communicates with the bus controller 540 through a data bus 572 and a control bus 576 . In addition, the external device 520 and the bus controller 540 communicate with each other through the data buses 522 and 524, the address buses 521 and 523, the control bus 526, and the ready bus 528, wherein the data buses 522 and 524 are different buses and can be used individually. control, and the address buses 521 and 523 are also different buses and can be individually controlled. Since there are two sets of data and address buses, and the first register 560 and the second register 570 are respectively responsible for sending and receiving data, the internal device 530 can simultaneously read and write to the external device 520 .

The internal device 530 may include units that a conventional MCU has, such as a read-only memory (ROM), a random access memory (RAM), a central processing unit (CPU), an I/O port (I/O Port), and a timer (timer). ) and so on, which will not be repeated here.

FIG. 6 is a timing diagram of bus transmission signals according to the embodiment shown in FIG. 4 . The bus transmission process can be divided into an idle state and a transfer state. In the idle state, all buses have no effect. According to the pre-stored firmware in the internal device, what kind of waveforms will be generated in the states of S0, S1, S2, etc. are determined. Because there are two independent address buses and data buses, one data can be written out and one data can be read in at the same time. For example, in state S2, when sending and writing data Do_0 (address Ao_0), receiving and reading at the same time Data Di_2 (address Ai_2) is fetched.

FIG. 7 is a timing diagram of bus transmission signals according to the embodiment shown in FIG. 5 . In this example, under the control of the firmware, the states S0 and S1 are only reading but not writing data, and the states S2 and S3 are both reading and writing data. 6 and 7 show that the present invention can provide a high-performance programmable logic system interface for simultaneously reading data from an external device to an internal device and writing data from an internal device to an external device.

The "chip" in the present invention can be, for example, a Universal Serial Bus (USB) chip. There are usually more than two FIFO devices in a general USB chip to store some setting data. Therefore, the present invention can use one of the FIFO devices for reading and the other for writing without adding additional hardware. The bus controller of the present invention can be, for example, an I2S (Inter-IC Sound) bus controller, so that the microphone and the speaker can act simultaneously. Because the present invention can provide a full-duplex bus, the data sent by the microphone and the data sent by the speaker can be transmitted simultaneously.

The invention can also be implemented on a digital video camera. Through the full-duplex bus of the present invention, an image sensor captures an image and simultaneously plays a sound effect through a speaker.

The above descriptions are illustrative only, not restrictive. Any equivalent modification or change made without departing from the spirit and scope of the present invention shall be included in the scope of the claims of the present invention.

Claims (16)

1. the chip with high performance programmable logic system interface is characterized in that, comprises:

One first interior arrangement is positioned at this chip, by one first group of internal bus and one first group of external bus, and links up with an external device (ED):

One second interior arrangement is positioned at this chip, by one second group of internal bus and one second group of external bus, and links up with this external device (ED):

One bus controller is in order to control this first group of internal bus, this first group of external bus, this second group of internal bus and this second group of external bus;

One external control bus is in order to link up this external device (ED) and this bus controller;

Wherein, this first interior arrangement and this second interior arrangement are to link up with this bus controller simultaneously, and this first interior arrangement and the transmission and the reception of responsible data respectively of this second interior arrangement,

And this first interior arrangement and this second interior arrangement are to link up with this external device (ED) simultaneously.

2. chip as claimed in claim 1 is characterized in that, this first interior arrangement and second interior arrangement are respectively a first in first out device.

3. chip as claimed in claim 1 is characterized in that, this first interior arrangement and second interior arrangement are respectively a micro-control unit buffer.

4. chip as claimed in claim 1 is characterized in that, this first group of internal bus is in order to connecting this first interior arrangement and this bus controller, and this first group of internal bus comprises a data bus and a control bus.

5. chip as claimed in claim 1 is characterized in that, this first group of external bus is in order to connecting this external device (ED) and this bus controller, and this first group of external bus comprises a data bus and an address bus.

6. chip as claimed in claim 1 is characterized in that, this external device (ED) is a printer, video recorder, a digital still camera, a storage device or other computer peripheral apparatus.

7. chip as claimed in claim 1 is characterized in that, the width programmable of each bus.

8. chip as claimed in claim 1 is characterized in that, this bus controller is an I2S bus controller, in order to the full duplex transmission between a microphone and the loudspeaker to be provided.

9. a high performance programmable logic system interface is arranged in the chip, and this chip comprises one first interior arrangement, one second interior arrangement and a bus controller, it is characterized in that, this high performance programmable logic system interface comprises:

One first group of internal bus is in order to link up this first interior arrangement and this bus controller;

One first group of external bus is in order to link up this bus controller and an external device (ED);

One second group of internal bus is in order to link up this second interior arrangement and this bus controller;

One second group of external bus is in order to link up this bus controller and this external device (ED);

One external control bus is in order to link up this external device (ED) and this bus controller;

Wherein, this first interior arrangement and this second interior arrangement are to link up with this bus controller simultaneously, and this first interior arrangement and the transmission and the reception of responsible data respectively of this second interior arrangement,

And this first interior arrangement and this second interior arrangement are to link up with this external device (ED) simultaneously.

10. high performance programmable logic system interface as claimed in claim 9 is characterized in that, this first interior arrangement and second interior arrangement are respectively a first in first out device.

11. high performance programmable logic system interface as claimed in claim 9 is characterized in that, this first interior arrangement and second interior arrangement are respectively a micro-control unit buffer.

12. high performance programmable logic system interface as claimed in claim 9 is characterized in that, this first group of internal bus comprises a data bus and a control bus.

13. high performance programmable logic system interface as claimed in claim 9 is characterized in that, this first group of external bus comprises a data bus and an address bus.

14. high performance programmable logic system interface as claimed in claim 9 is characterized in that, this external device (ED) is a printer, a video recorder, a digital still camera, a storage device or other computer peripheral apparatus.

15. high performance programmable logic system interface as claimed in claim 11 is characterized in that, the width programmable of each bus.

16. high performance programmable logic system interface as claimed in claim 11 is characterized in that, this bus controller is an I2S bus controller, in order to the full duplex transmission between a microphone and the loudspeaker to be provided.

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