CN101211792A - Semiconductor package and manufacturing method and stacking structure thereof - Google Patents

Abstract

The invention discloses a semiconductor package and a manufacturing method and a stacking structure thereof, which provides a substrate module with a plurality of substrates, wherein each substrate is connected with and electrically connected with a semiconductor chip and a plurality of conductive bumps, then, a package manufacturing process is performed to form a package body on the substrate module for encapsulating the semiconductor chip and the conductive bumps, and the end portions of the conductive bumps are exposed out of the top surface of the package body, then cutting along the substrates to form multiple semiconductor packages with exposed conductive bump ends on top surfaces, therefore, another semiconductor package is stacked through the conductive element and is electrically connected to the end part of the conductive bump exposed out of the top surface of the package body, and the problems that packaging resin pollutes a welding pad, the number of I/O (input/output) of electrical connection is small, no sufficient space is available for arranging a passive element, warping is easy to occur and the like in the conventional semiconductor package stacking structure are solved.

Description

Semiconductor package, its manufacturing method and stacked structure

technical field

The present invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package capable of stacking multiple packaging structures, its manufacturing method and stacking structure.

Background technique

In addition to the miniaturization of electronic products, performance and processing speed are still required to be improved. The best way to improve performance and processing speed is nothing more than increasing the number or size of chips in the semiconductor package, but the area available on the substrate for chip placement is often not enough for multiple chips to be arranged horizontally or larger in size. chip placement. Therefore, the current development focuses on the stacked multi-package module (Package on Package, POP) in which multiple packages are stacked one above the other.

Referring to FIG. 1, U.S. Patent No. 5,222,014 discloses a POP stack structure of a semiconductor package, which provides a ball grid array (BGA) substrate 11 with a plurality of stacked pads (stacked pads) 110 on the upper surface, so that the A semiconductor chip 10 is placed on the substrate 11 and a package body 13 covering the semiconductor chip 10 is formed to form a lower semiconductor package 101, and then a packaged upper semiconductor package 102 is connected through solder balls 14 and electrically connected. Connect to the stacking pads 110 on the substrate surface of the lower semiconductor package 101 to form a POP stack structure of the semiconductor package.

However, since the aforementioned upper semiconductor package and the lower semiconductor package are electrically connected by solder ball reflow, and the height H of the solder ball is generally 0.5 mm, the height h of the package body of the lower semiconductor package must be limited. Less than the height H of the solder ball, that is, the height h of the package is normally below 0.3 mm. However, the height of the package is too low to affect the quality of the bonding wire used to electrically connect the chip to the substrate, resulting in the lower semiconductor package Component reliability is poor.

In addition, the distance between the package body of the lower layer semiconductor package and the nearest soldering pad must be at least 0.25 mm, so as to reduce the pollution caused by the resin forming the package body overflowing to the soldering pad, causing electrical failure of stacked contacts. However, this will reduce the space available for setting the pads, so that the number of pads becomes smaller, resulting in a reduction in the number of I/Os electrically connected between the upper and lower semiconductor packages; in addition, for packages of different sizes and shapes , that is, corresponding different molds must be used, resulting in increased manufacturing cost and complexity, and the shape of the package also limits the application for subsequent stacking of another semiconductor package on the lower semiconductor package.

Relatively, in order to increase the number of I/Os that can be electrically connected between the upper layer and the lower layer semiconductor package, it is necessary to increase the pads as much as possible, that is, the package size of the lower layer semiconductor package must be limited as much as possible, but so That is, there is not enough space for passive components to improve the electrical quality of the package.

In addition, referring to FIG. 2, the size of the package body 13 of the lower semiconductor package 101 is relatively too small, which will lead to poor structural strength of the lower semiconductor package 101, and the problem of structural warpage (warpage) is prone to occur, resulting in difficulty in the follow-up. Stacking the upper semiconductor package 102 on the lower semiconductor package 101 may even lead to cracking of the solder balls 14 that provide the electrical coupling between the upper and lower semiconductor packages 102 , 101 when the upper semiconductor package 102 is stacked.

Therefore, how to provide a semiconductor package and its manufacturing method can avoid the limitation of the number of stacking pads and the arrangement of passive components, contamination of the stacking pads, structural warping, and the targeting of the lower stacked semiconductor package due to the package body Different package shapes and sizes need to prepare different corresponding production molds, resulting in increased manufacturing cost and complexity, etc., which has become an urgent problem to be solved.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a semiconductor package and its manufacturing method and stacking structure, so as to avoid the problem of limiting the number of stacked pads in the existing lower semiconductor package due to the setting of the package .

Another object of the present invention is to provide a semiconductor package and its manufacturing method and stacking structure, so as to avoid the problem of the existing lower semiconductor package from polluting the stacking pads due to the package body.

Another object of the present invention is to provide a semiconductor package and its manufacturing method and stacking structure, so as to avoid the structural warping problem of the existing lower semiconductor package due to the small size of the package.

Another object of the present invention is to provide a semiconductor package and its manufacturing method and stacking structure, which can effectively arrange passive components to improve the electrical quality of the package.

Another object of the present invention is to provide a semiconductor package and its manufacturing method and stacking structure, which can complete chip packaging with only a single mold, thereby avoiding the need to prepare for different package shapes and sizes in the existing lower semiconductor package. Different corresponding problems such as manufacturing costs and complexity increase caused by the production of molds.

In order to achieve the above and other objects, the manufacturing method of the semiconductor package of the present invention includes: providing a substrate module sheet with a plurality of substrates, each of which is provided with a chip connection area and a plurality of stacked pads on the surface of the substrate; Connecting conductive bumps on the stacked pads and connecting and electrically connecting the semiconductor chip on the chip landing area; performing a packaging manufacturing process to form a package covering the semiconductor chip and the conductive bumps on the substrate module, and exposing the end of the conductive bump to the top surface of the package; and cutting along the substrates to form a plurality of semiconductor packages with the end of the conductive bump exposed on the top surface of the package. In addition, multiple passive components can be placed and electrically connected on the substrate to improve the electrical quality of the package. The substrate can be a thin ball grid array (TFBGA) substrate or a land grid array (Land Grid Array, LGA) substrate.

During the encapsulation and manufacturing process of the semiconductor package, a package that fully covers the semiconductor chip and conductive bumps can be formed on the substrate module; The block ends are exposed on the top surface of the package. In addition, when the semiconductor package is in the packaging and manufacturing process, the substrate module with the semiconductor chip and the conductive bumps connected thereto can be placed in a mold cavity of a packaging mold, wherein the top surface of the mold cavity is pre-laid with a film layer, and press the film layer on the top surface of the mold cavity against the end of the conductive bump, and then fill the mold cavity with encapsulation resin to form a package covering the semiconductor chip and the conductive bump; then The mold and film layer are removed, so as to directly expose the package body from the end of the conductive bump.

Through the aforementioned manufacturing method, the present invention also discloses a semiconductor package, including: a substrate, a chip landing area and a plurality of stacked pads are provided on the surface of the substrate; a semiconductor chip is placed on the chip landing area and electrically connected to the substrate; conductive bumps, placed on the stacked pads; and a package, formed on the substrate and covering the semiconductor chip and the conductive bumps, and exposing the end of the conductive bumps to the top of the package noodle. In addition, multiple passive components can be placed and electrically connected on the substrate to improve the electrical quality of the package.

The present invention also discloses a semiconductor package stack structure, which includes a lower semiconductor package; and an upper semiconductor package, stacked and electrically connected to the lower semiconductor package, wherein the lower semiconductor package includes a surface with a A substrate with a chip landing area and a plurality of stacked pads, a semiconductor chip connected to the chip landing area and electrically connected to the substrate, a conductive bump placed on the stacked pads, and formed on the substrate A package that covers the semiconductor chip and conductive bumps, the end of the conductive bumps is exposed on the top surface of the package, so that the upper semiconductor package can be connected and electrically connected to the lower layer through a plurality of conductive elements The semiconductor package exposes the end of the conductive bump on the top surface of the package.

Therefore, the semiconductor package and its manufacturing method and stacked structure of the present invention provide a substrate module with a plurality of substrates, each of which is provided with a chip landing area and a plurality of stacked pads on the surface of the substrate. Connecting conductive bumps on the stacked pads and connecting and electrically connecting the semiconductor chip on the chip landing area, and then performing the packaging and manufacturing process to form a package covering the semiconductor chip and the conductive bumps on the substrate module, And the end of the conductive bump is exposed to the top surface of the package, and then the cutting operation can be performed along each of the substrates to form a plurality of semiconductor packages with the top surface of the package exposed to the end of the conductive bump. For other semiconductor packages to be connected and electrically connected to the conductive bump end exposed on the top surface of the semiconductor package through a plurality of conductive elements.

In this way, in the existing stacked structure of semiconductor packages, the package height of the semiconductor chip covered in the lower semiconductor package is limited by the height of the solder balls, resulting in poor product reliability, overflow to the solder pad and pollution , or reduce the space available for setting pads in order to avoid pad contamination, resulting in a reduction in the number of I/Os that are electrically connected between stacked semiconductor packages, or to increase the number of I/Os that are electrically connected between semiconductor packages The number of /O limits the size of the package body of the lower layer semiconductor package, resulting in insufficient space for passive components and prone to warpage. At the same time, only a single package mold can be used to manufacture the semiconductor package of the present invention. and its stacked structure to reduce manufacturing cost and complexity.

Description of drawings

FIG. 1 is a stacked structure of a semiconductor package disclosed in US Pat. No. 5,222,014;

FIG. 2 is a schematic diagram of warping of a lower semiconductor package in a stacked structure of conventional semiconductor packages;

3A to 3E are schematic cross-sectional views of the first embodiment of the semiconductor package and its manufacturing method of the present invention;

4A to 4C are schematic cross-sectional views of the second embodiment of the semiconductor package manufacturing method of the present invention;

5 is a schematic cross-sectional view of a third embodiment of a semiconductor package of the present invention; and

FIG. 6 is a schematic diagram of the semiconductor package stack structure of the present invention.

Description of main component symbols

10 semiconductor chip

11 substrate

110 stacked pads

13 packages

14 solder balls

101 lower layer semiconductor package

102 upper semiconductor package

30 semiconductor chips

31 substrate

31A substrate module

311 chip placement area

312 stacked pads

32 conductive bumps

33 packages

35 passive components

40 semiconductor chips

41 Substrate

41A base module

42 conductive bumps

43 packages

45 passive components

46 package mold

460 cavity

47 film layers

50 semiconductor chips

51 substrate

60 semiconductor chips

61 substrates

62 conductive bumps

63 packages

64 conductive elements

601 lower layer semiconductor package

602 upper semiconductor package

611 chip placement area

612 stacked pads

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

first embodiment

Referring to FIGS. 3A to 3E , they are schematic diagrams of a first embodiment of the semiconductor package and its manufacturing method of the present invention.

As shown in FIG. 3A , a substrate module sheet 31A having a plurality of substrates 31 is provided, and a chip landing area 311 and a plurality of stacking pads 312 are provided on the surface of each substrate 31 . The substrate may be a Thin Ball Grid Array (TFBGA) substrate or a Land Grid Array (LGA) substrate or the like.

As shown in FIG. 3B, a conductive bump 32 is placed on the stacked pad 312 of the substrate 31, and a semiconductor chip 30 is placed and electrically connected to the chip landing area 311, wherein the conductive bump 32 is, for example, Solder bumps, and the semiconductor chip 30 can be electrically connected to the substrate 31 by wires, and a plurality of passive components 35 such as capacitors, resistors or inductors can also be fully connected on the substrate 31 .

As shown in FIGS. 3C and 3D , the package manufacturing process is performed. Firstly, a package body 33 that fully covers the semiconductor chip 30 , passive components 35 and conductive bumps 32 is formed on the substrate module sheet 31A.

Then, the top of the package 33 is removed through a thinning operation such as grinding, so that the end of the conductive bump 32 is flush with the top surface of the package 33, so that the end of the conductive bump 32 is exposed to the package. 33.

As shown in FIG. 3E , the cutting operation is performed along each of the substrates 31 to form a thin ball grid array (TFBGA) or a land grid array (LGA) semiconductor with the ends of the conductive bumps 32 exposed on the top surface of a plurality of packages 33. A package, wherein the side of the package body 33 and the substrate 31 are flush with each other.

Through the above method, the present invention also discloses a semiconductor package, including: a substrate 31, the surface of the substrate 31 is provided with a chip connection area 311 and a plurality of stacked pads 312; a semiconductor chip 30 is connected to the chip connection region 311 and is electrically connected to the substrate 31; conductive bumps 32 are placed on the stacked pads 312; and a package 33 is formed on the substrate 31 to cover the semiconductor chip 30 and the conductive bumps 32, And the end of the conductive bump 32 is exposed from the top surface of the package body 33 . In addition, a plurality of passive components 35 can be placed and electrically connected on the substrate 31 to improve the electrical quality of the package.

In addition, since the semiconductor package of the present invention forms a TFBGA or LGA package body 33 covering the semiconductor chip 30 and the conductive bump 32 (but exposing the end of the conductive bump) on the substrate 31, its structural balance can be effectively The problem of warpage is prevented, and problems such as the stacking pads being polluted by the packaging resin and the size limitation of the package in the prior art will not occur.

second embodiment

Referring to FIGS. 4A to 4C , they are schematic diagrams of a second embodiment of the semiconductor package manufacturing method of the present invention.

As shown in FIG. 4A , the manufacturing method of this embodiment is basically the same as that of the previous embodiment. First, a substrate module sheet 41A with a plurality of substrates 41 is provided, so as to place and electrically connect semiconductor chips 40 on each of the substrates 41. , passive components 45 and conductive bumps 42, and the substrate module sheet 41A that is connected with the semiconductor chip 40, passive components 45 and conductive bumps 42 is placed in a mold cavity 460 of a package mold 46, wherein the mold The top surface of the cavity 460 is pre-laid with a film layer 47, such as a polyimide (polyimide) film, and the film layer 47 laid on the top surface of the mold cavity 460 is pressed against the end of the conductive bump 42, and then The mold cavity 460 is filled with encapsulation resin, so as to form the encapsulation body 43 covering the semiconductor chip 40 , the passive element 45 and the conductive bump 42 .

As shown in FIG. 4B , the mold 46 and the film layer 47 are then removed, so that the end of the conductive bump 42 directly exposes the package body 43 .

As shown in FIG. 4C , dicing is performed along each of the substrates 41 to form a plurality of TFBGA or LGA semiconductor packages with the ends of the conductive bumps 42 exposed on the top surfaces of the packages 43 .

third embodiment

Referring to FIG. 5 , it is a schematic cross-sectional view of a third embodiment of the semiconductor package of the present invention.

As shown in the figure, the semiconductor package of this embodiment is substantially the same as the above-mentioned embodiments, the main difference is that the semiconductor chip 50 can be electrically connected to the substrate in addition to the aforementioned lead method, and can also be electrically connected to the substrate by flip-chip Substrate 51.

Also refer to FIG. 6 , which shows a schematic cross-sectional view of the semiconductor package stack structure of the present invention, mainly using the aforementioned TFBGA or LGA semiconductor package as the lower semiconductor package in the stack structure, so as to connect and electrically connect other semiconductor packages thereon. packages to form a semiconductor package stack structure.

The semiconductor package stack structure includes: a lower TFBGA or LGA semiconductor package 601; and an upper semiconductor package 602, stacked and electrically connected to the lower semiconductor package 601, wherein the lower semiconductor package 601 includes A substrate 61 with a chip landing area 611 and a plurality of stacked pads 612 on the surface, a semiconductor chip 60 connected to the chip landing area 611 and electrically connected to the substrate 61, and a semiconductor chip 60 connected to the stacked pads 612 The conductive bump 62 and the package 63 formed on the substrate 61 to cover the semiconductor chip 60 and the conductive bump 62, the end of the conductive bump 62 exposes the top surface of the package 63 for the upper semiconductor The package 602 is mounted and electrically connected to the end of the conductive bump 62 exposed on the top surface of the package 63 of the lower semiconductor package 601 through a plurality of conductive elements 64 such as solder balls.

Therefore, the semiconductor package and its manufacturing method and stacked structure of the present invention provide a substrate module with a plurality of substrates, each of which is provided with a chip landing area and a plurality of stacked pads on the surface of the substrate. Connecting conductive bumps on the stacked pads and connecting and electrically connecting the semiconductor chip on the chip landing area, and then performing the packaging and manufacturing process to form a package covering the semiconductor chip and the conductive bumps on the substrate module, And the end of the conductive bump is exposed to the top surface of the package, and then the cutting operation can be performed along the substrates to form a plurality of TFBGA or LGA semiconductor packages with the top of the package exposed to the end of the conductive bump. The components are used for other semiconductor packages to be connected and electrically connected to the conductive bump ends of the semiconductor package exposed on the top surface of the package through a plurality of conductive elements.

In this way, in the existing stacked structure of semiconductor packages, the package height of the semiconductor chip covered in the lower semiconductor package is limited by the height of the solder balls, resulting in poor product reliability, overflow to the solder pad and pollution , or reduce the space available for setting pads in order to avoid pad contamination, resulting in a reduction in the number of I/Os that are electrically connected between stacked semiconductor packages, or to increase the number of I/Os that are electrically connected between semiconductor packages The number of /O limits the package size of the lower layer semiconductor package, causing problems such as insufficient space for arranging passive components and prone to warping, and at the same time, only a single TFBGA or LGA package mold can be used to manufacture the present invention The semiconductor package and its stacked structure are used to reduce manufacturing cost and complexity.

The above-mentioned embodiments are only used to illustrate the principles and effects of the present invention, but not to limit the present invention. Therefore, any person skilled in the art can modify and modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Varies, depending on implementation type.

Claims (15)

1. the method for making of a semiconductor package part comprises:

The substrate module sheet of a plurality of substrates of one tool is provided, and respectively the surface of this substrate is provided with a chip connecting area and a plurality of weld pad that piles up;

Pile up to connect on the weld pad in this substrate and put conductive projection and on this chip connecting area, connect and put and electrically connect semiconductor chip;

Carry out package fabrication process, coat the packaging body of this semiconductor chip and conductive projection with formation on the substrate module sheet, and make the end of this conductive projection expose outside this packaging body end face; And

Along respectively carrying out cutting operation between this substrate, expose the semiconductor package part that the conductive projection end is arranged to form a plurality of packaging body end faces.

2. the method for making of semiconductor package part according to claim 1, wherein, this semiconductor package part is one of them of thin spherical grid array semiconductor package part and planar lattice array semiconductor package part.

3. the method for making of semiconductor package part according to claim 1, wherein, this semiconductor chip is electrically connected to this substrate in a wherein mode of lead-in wire and flip-chip.

4. the method for making of semiconductor package part according to claim 1 wherein, also connects on this substrate and is equipped with a plurality of passive components.

5. the method for making of semiconductor package part according to claim 1, wherein, this package fabrication process comprises:

On this substrate module sheet, form the packaging body that comprehensively coats this semiconductor chip and conductive projection; And

Carry out the thinning operation, make this conductive projection end expose outside this packaging body end face to remove the part packaging body.

6. the method for making of semiconductor package part according to claim 1, wherein, this package fabrication process comprises:

This is connect the die cavity that the substrate module sheet that is equipped with semiconductor chip and conductive projection places an encapsulating mould, and wherein the end face of this die cavity is laid with a thin layer in advance, and makes the film laminating of this die cavity end face be butted on this conductive projection end;

In this die cavity, fill potting resin, use forming the packaging body that coats this semiconductor chip and conductive projection; And

Remove this mould and thin layer, use directly making this conductive projection end expose outside this packaging body.

7. the method for making of semiconductor package part according to claim 6, wherein, this thin layer is the polyimides film.

8. semiconductor package part comprises:

Substrate, this substrate surface are provided with a chip connecting area and a plurality of weld pad that piles up;

Semiconductor chip connects and places this chip connecting area and be electrically connected to this substrate;

Conductive projection connects and places this to pile up on the weld pad; And

Packaging body is formed on this substrate and coats this semiconductor chip and conductive projection, and makes this conductive projection end expose outside this packaging body end face.

9. semiconductor package part according to claim 8, wherein, this semiconductor package part be thin spherical grid array semiconductor package part and planar lattice array semiconductor package part wherein it

10. semiconductor package part according to claim 8, wherein, this semiconductor chip is electrically connected to this substrate in a wherein mode of lead-in wire and flip-chip.

11. semiconductor package part according to claim 8 wherein, also connects on this substrate and is equipped with a plurality of passive components.

12. a semiconductor package part stacked structure comprises:

One lower floor's semiconductor package part; And

One upper strata semiconductor package part, pile up and be electrically connected on this lower floor's semiconductor package part, wherein, this lower floor's semiconductor package part includes the surface and is provided with a chip connecting area and a plurality of substrate that piles up weld pad, connect the semiconductor chip that places this chip connecting area and be electrically connected to this substrate, connect and place this to pile up the conductive projection of weld pad, and be formed on this substrate to coat the packaging body of this semiconductor chip and conductive projection, this conductive projection end exposes outside this packaging body end face, connects by a plurality of conducting elements for this upper strata semiconductor package part and puts and be electrically connected to the conductive projection end that this lower floor's semiconductor package part exposes outside this packaging body end face.

13. semiconductor package part stacked structure according to claim 12, wherein, this lower floor's semiconductor package part is one of them of thin spherical grid array semiconductor package part and planar lattice array semiconductor package part.

14. semiconductor package part stacked structure according to claim 12, wherein, the semiconductor chip of this lower floor's semiconductor package part is electrically connected to this substrate in a wherein mode of lead-in wire and flip-chip.

15. semiconductor package part stacked structure according to claim 12 wherein, also connects on the substrate of this lower floor's semiconductor package part and is equipped with a plurality of passive components.

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