CN101221949A - Face-centered cubic structure capacitor and manufacturing method thereof - Google Patents

Abstract

The invention discloses a face-centered cubic structure capacitor and a manufacturing method thereof, wherein the face-centered cubic structure capacitor is composed of a first metal layer, a second metal layer and a connecting layer for connecting the first metal layer and the second metal layer, wherein the first metal layer is composed of a plurality of first metal wires, a plurality of second metal wires and a plurality of first metal blocks, the first metal wires and the second metal wires are mutually crossed to form a grid structure, and each first metal block is arranged in a grid of the grid structure; the second metal layer is composed of a plurality of third and fourth metal wires and a plurality of second metal blocks, the third and fourth metal wires are mutually crossed to form a grid structure, and each second metal block is arranged in a grid of the grid structure; the connecting layer is composed of a plurality of third metal blocks and fourth metal blocks, each third metal block is connected with the intersection of each first metal block and the third metal line, each fourth metal block is connected with the intersection of each second metal block and the first metal line, and each fourth metal block is connected with the intersection of each second metal block and the second metal line.

Description

Face-centered cubic structure capacitor and manufacturing method thereof

technical field

The invention relates to a capacitor, in particular to a face-centered cubic structure capacitor (Face Center Cube Capacitor) which utilizes the lateral electric field between metal wires of the same layer to form a capacitor structure.

Background technique

Nowadays, the development of system-on-chip (SOC) technology is becoming more and more mature, and the integration of IC circuits is complex, and the number of components accommodated per unit area increases accordingly. Many passive components that used to be externally connected due to their large area, such as capacitors and inductors, must be integrated. in a single chip.

In the layout of integrated circuits, different layers of metal are used to form plate capacitors. This kind of electric field in the vertical direction is used. As the effective line width becomes smaller and smaller, the chip area occupied by it will also increase. In addition, in the case of reduced line width, achieving the same capacitance in a limited area or volume is also a major technical problem in the layout of integrated circuits, so many solutions have been disclosed in the known technology.

For example, U.S. Patent No. 5,208,725 discloses a capacitor structure, the capacitor structure has a first conductive layer and a second conductive layer, each conductive layer is composed of several strip structures, and each strip structure is parallel to each other. Its main technical feature is the use of finger structures and the use of lateral and vertical electric fields to increase capacitance density.

U.S. Patent No. 6,037,621 discloses a capacitor structure, which has an upper metal layer and a lower metal layer. An island-shaped metal array is arranged between the upper and lower metal layers. Each metal island is connected to one of the upper metal layer and the lower metal layer. The main technical feature is to use the metal-to-metal via (Via) to realize the metal island array, and to use the lateral and vertical electric fields to increase the capacitance density.

The capacitor structure disclosed in U.S. Patent No. 6,297,524 is composed of a first conductive layer and at least one second conductive layer. The conductive layer is a conductive concentric annular line stacked in a concentric annular manner. Each conductive layer It is then connected by a conductive via (VIA). The main technical features of this patent utilize concentric ring structures, use lateral electric fields, and use vias (Via) to penetrate the upper and lower metal layers to increase capacitance density.

The capacitor structure disclosed in US Patent No. 6410954 is composed of a first conductive layer and at least one second conductive layer. The conductive layer is a concentric line with an open ring structure, and the second conductive layer covers the first conductive layer. The main technical feature of this patent also utilizes the concentric ring structure, and with the help of the upper and lower metal interlacing, the lateral and vertical electric fields are used to increase the capacitance density.

U.S. Early Publication No. 20040036143 application proposes a capacitor structure, which has two vertical plates inside and outside on a substrate, and a grid structure is defined by the outer vertical plates. The parasitic capacitance generated between. Its main technical feature lies in the use of grid structure and the use of lateral electric field to increase the capacitance density.

The main technical feature of the capacitive structure disclosed in US Patent No. 6737698 is that it uses a shielding structure to confine the electric field between two shieldings.

The capacitor structure disclosed in U.S. Patent No. 6,765,778 is composed of array stacks, wherein the second stack is closest to the first stack, and the third stack is the second closest to the first stack. These three stacks define an equilateral triangle. vertex, the triangle is formed in a plane perpendicular to the stack. Its main technical feature is the hexagonal vertical stack structure and the use of lateral electric fields to increase capacitance density.

U.S. Early Publication No. 20040174655 application discloses a capacitor structure, which is mainly composed of two layers of finger structures interlaced with each other. Its main technical feature is the use of finger structures. Mismatched states of metals to increase capacitance density.

U.S. Early Publication No. 20050280060 application proposes a capacitor structure, which is configured in a concentric nest-like manner by inner box capacitors and outer box capacitors. capacitance density.

Contents of the invention

The object of the present invention is to provide a capacitor with a face-centered cubic structure and a manufacturing method thereof. The capacitor is realized by utilizing the lateral electric field of the same-layer metal wire and the wire. When the effective line width is reduced, the capacitance per unit volume can be increased. In order to increase the capacitance density.

In order to achieve the above object, the present invention provides a face-centered cubic structure capacitor, which is composed of a first metal layer, a second metal layer and a connecting layer connecting the first metal layer and the second metal layer, wherein the first metal layer The layer is composed of several first metal wires, several second metal wires and several first metal blocks. The first metal wires and the second metal wires cross each other to form a grid structure. Each of the first metal wires Blocks are arranged in each grid of the grid structure; and the second metal layer is composed of several third metal lines, several fourth metal lines and several second metal blocks, the third metal lines and the first Four metal wires intersect each other to form a grid structure, and each second metal block is arranged in each grid of the grid structure; the connection layer is composed of several third metal blocks and several fourth metal blocks , wherein each of the third metal blocks is connected to each of the first metal blocks and the intersection of the third metal line and the fourth metal line, and each of the fourth metal blocks is connected to each of the second metal blocks and the The intersection of the first metal line and the second metal line.

In order to achieve the above object, the present invention provides a face-centered cubic structure capacitor, which is composed of several layers of first metal layers, several layers of second metal layers and a connection layer connecting the first metal layer and the second metal layer; The first metal layer is composed of several first metal lines, several second metal lines and several first metal blocks. The first metal lines and the second metal lines cross each other to form a grid structure, each The first metal block is arranged in each grid of the grid structure; and the layers of second metal layers are composed of several third metal lines, several fourth metal lines and several second metal blocks. The three metal lines and the fourth metal lines cross each other to form a grid structure, and each second metal block is arranged in each grid of the grid structure, wherein each of the first metal layers and each of the first metal layers are connected to each other. The second metal layer is arranged in a staggered manner; the connection layer is composed of several third metal blocks and several fourth metal blocks, wherein each of the third metal blocks connects each of the first metal blocks with the third metal line and the first metal block At the intersection of the four metal lines, each of the fourth metal blocks is connected to each of the second metal blocks and the intersection of the first metal line and the second metal line.

In order to achieve the above object, the present invention provides a method for manufacturing a capacitor with a face-centered cubic structure. First, a first metal layer is formed, and the first metal layer is composed of several first metal wires, several second metal wires, and several Composed of a first metal block, the first metal line and the second metal line cross each other to form a grid structure, the first metal block is arranged on the intersection formed by the first metal line and the second metal line In each grid structure; further form a contact layer, the contact layer is composed of several third metal blocks and several fourth metal blocks, wherein each of the third metal blocks is connected to each of the first metal blocks, each A fourth metal block is connected to the intersection of the first metal line and the second metal line; finally a second metal layer is formed, and the second metal layer is composed of several third metal lines, several fourth metal lines and A plurality of second metal blocks, the third metal line and the fourth metal line cross each other to form a grid structure, the second metal block is arranged on the intersection formed by the third metal line and the fourth metal line In each grid structure, the second metal block is connected to the fourth metal block of the connection layer, and the third metal wire is connected to the third metal block of the connection layer.

According to the capacitor structure and its manufacturing method disclosed in the present invention, the most efficient use can be achieved in a limited volume, and the problem of excessive volume or area occupied by a chip generally using a flat capacitor is improved.

In addition, the three-dimensional network structure it adopts can effectively utilize the electric field in all directions, and can obtain higher capacitance value under the same volume, which can relatively reduce the chip area, thereby reducing the manufacturing cost. For the development and application of SOC technology in the future, passive components can be integrated more efficiently, which has a positive and substantial performance improvement.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

Fig. 1 is a structural schematic diagram of a capacitor with a face-centered cubic structure disclosed by the present invention;

2A to 2C are schematic diagrams of photomasks for making the face-centered cubic structure capacitor disclosed in the present invention;

Fig. 3 is a structural schematic diagram of a capacitor with a face-centered cubic structure disclosed by the present invention;

4A to 4E are the manufacturing process of the face centered cubic structure capacitor disclosed in the present invention.

Among them, reference signs:

100 first metal layer

200 second metal layer

300 connection layers

110 first metal wire

120 second metal wire

130 first metal block

210 third metal wire

220 fourth metal wire

230 Second Metal Block

310 third metal block

320 fourth metal block

400 substrates

410 Dielectric material

420 dielectric layer

411 guide hole

Detailed ways

Please refer to FIG. 1 and FIG. 2A to FIG. 2C at the same time to illustrate the face-centered cubic structure capacitor disclosed in the present invention. FIG. 1 is a schematic structural diagram of a capacitor with a face-centered cubic structure disclosed in the present invention. 2A to FIG. 2C are schematic diagrams of photomasks for fabricating the face-centered cubic structure capacitor disclosed in the present invention, which are used here to help explain the structure shown in FIG. 1 .

As shown in the figure, the face centered cubic capacitor is mainly composed of three layers, which are the first metal layer 100 , the second metal layer 200 and the connecting layer 300 .

The first metal layer 100 is composed of several first metal lines 110 , several second metal lines 120 and several first metal blocks 130 . The first metal lines 110 and the second metal lines 120 intersect each other to form a grid structure. In this embodiment, they are vertical intersects, but not necessarily vertical intersects, as long as the first metal lines 110 and the second metal lines 120 intersect each other. to form a grid structure. The first metal block 130 is disposed in each grid structure formed by the intersection of the first metal lines 110 and the second metal lines 120 . The first metal lines are parallel to each other, and the second metal lines are parallel to each other.

The second metal layer 200 is composed of several third metal lines 210 , several fourth metal lines 220 and several second metal blocks 230 . The third metal lines 210 and the fourth metal lines 220 intersect each other to form a grid structure, in this embodiment, they are vertical intersects, but not necessarily vertical intersects, as long as the third metal lines 210 and the fourth metal lines 220 intersect each other to form a grid structure. The second metal block 230 is disposed in each grid structure formed by the crossing of the third metal lines 210 and the fourth metal lines 220 . The third metal lines are parallel to each other, and the fourth metal lines are parallel to each other.

The connection layer 300 is composed of several third metal blocks 310 and several fourth metal blocks 320 , wherein each third metal block 310 connects each first metal block and the third metal line 210 and the fourth metal line 220 Each fourth metal block 320 connects each second metal block 230 to the intersection of the first metal line 110 and the second metal line 120 .

The grid structure formed by the first metal layer 100 , the second metal layer 200 , and the connection layer 300 connect the first metal layer 100 and the second metal layer 200 to form a capacitor. The capacitance structure disclosed in the present invention realizes capacitance by means of the lateral electric field between metal lines of the same layer. Therefore, as the effective line width decreases, the capacitance per unit area can be increased.

FIG. 1 shows a simplified structure. Extending the structure in FIG. 1, an actual three-dimensional capacitor structure can be obtained, which is formed by repeating the first metal layer 100, the second metal layer 200 and the connection layer 300, wherein each A first metal layer 100 and each second metal layer 200 are alternately arranged, and each connecting layer 300 connects each first metal layer 100 and each second metal layer 200 .

Although not shown, the gaps between the metal lines are filled with dielectric material.

In the layout of integrated circuits, different layers of metal are often used to form plate capacitors. This type of capacitor utilizes the electric field in the vertical direction. However, as the effective line width becomes smaller and smaller, the proportion of the chip area occupied by it also increases significantly.

The face centered cubic structure capacitor disclosed in the present invention can be completed by standard CMOS process, please refer to FIG. 4A to FIG. 4D , which are exemplary process flow of the face centered cubic structure capacitor disclosed in the present invention. FIG. 4A to FIG. 4D take the cross section of FIG. 1 as an example for illustration, and refer to FIG. 2A to FIG. 2C at the same time.

Please refer to FIG. 4A , the capacitor is formed on a substrate 400 . In one embodiment, other components or circuits may be formed on the substrate 400 . For simplicity of description, these components or circuits are not included in the description and illustration.

Firstly, the first metal layer 100 is formed. According to the cross section of FIG. 1 , the first metal layer 100 includes the second metal line 120 and the first metal block 130 . But in fact, it is the pattern shown in FIG. 2A, that is, a first metal layer 100 is formed, and the metal layer 100 is composed of several first metal lines 110, several second metal lines 120 and several first metal blocks 130. Composition, and the first metal wire 110 and the second metal wire 120 intersect each other to form a grid structure, and the first metal block 130 is arranged on each mesh formed by the first metal wire 110 and the second metal wire 120 intersecting each other in the lattice structure. Then, a dielectric material 410 is filled in the voids of the first metal layer 100 .

In another embodiment, a dielectric layer may also be formed first, and then exposed and developed on the dielectric layer with the mask shown in FIG. Portions of block 130 are etched out, and metal material is deposited in corresponding locations.

Referring to FIG. 4B to FIG. 4D, the contact layer 300 is formed next, which first forms a dielectric layer 420, and uses FIG. 2B as a mask to perform exposure and development, leaving a guide hole 411 to be filled with metal, and finally filled with metal. Only the third metal block 310 can be seen in this figure, but in fact it is the pattern shown in FIG. 320, wherein each third metal block 310 is connected to each first metal block, and each fourth metal block 320 is connected to the intersection of the first metal line 110 and the second metal line 120 .

In another embodiment, the contact layer 300 may also be formed first, and then a dielectric material is filled in the gap of the contact layer 300 .

Referring to FIG. 4E, the second metal layer 200 is formed, and exposure and development are performed using FIG. 2C as a mask. The second metal layer 200 is composed of several third metal lines 210, several fourth metal lines 220 and several second metal blocks. 230, and the third metal line 210 and the fourth metal line 220 intersect each other to form a grid structure, and the second metal block 230 is arranged on each intersecting formed by the third metal line 210 and the fourth metal line 220 in the grid structure. The second metal block 230 is connected to the fourth metal block 320 of the connection layer 300 , and the third metal line 210 and the fourth metal line 220 are connected to the third metal block 310 of the connection layer 300 . Finally, a dielectric material (not shown) is filled in the gaps of the second metal layer 300 .

In another embodiment, a dielectric layer may also be formed first, and then exposed and developed on the dielectric layer with the mask shown in FIG. Portions of block 330 are etched out, and metal material is deposited in corresponding locations.

To form the structure shown in Figure 3, repeat the above steps.

The capacitance structure disclosed in the present invention realizes capacitance by means of the lateral electric field between metal lines of the same layer. Therefore, as the effective line width decreases, the capacitance per unit area can be increased. That is to say, under the same capacitance value, the capacitance structure provided by the present invention can effectively reduce the area required for layout, thereby reducing the cost required for chip manufacturing.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding changes All changes and modifications should belong to the scope of protection of the appended claims of the present invention.

Claims (12)

1. A capacitor with a face-centered cubic structure, characterized in that it comprises: a first metal layer, which is composed of several first metal lines, several second metal lines and several first metal blocks, the first metal lines and the second metal lines cross each other to form a grid structure, Each of the first metal blocks is disposed in each grid of the grid structure; a second metal layer, which is composed of several third metal lines, several fourth metal lines and several second metal blocks, the third metal lines and the fourth metal lines cross each other to form a grid structure, each of the second metal blocks is disposed in each grid of the grid structure; and A connection layer, composed of several third metal blocks and several fourth metal blocks, wherein each of the third metal blocks connects each of the first metal blocks and the intersection of the third metal line and the fourth metal line Each of the fourth metal blocks connects each of the second metal blocks to intersections of the first metal line and the second metal line. 2 . The face centered cubic structure capacitor according to claim 1 , wherein the first metal lines are parallel to each other, and the second metal lines are parallel to each other. 3 . The face-centered cubic structure capacitor according to claim 1 , wherein the third metal lines are parallel to each other, and the fourth metal lines are parallel to each other. 4 . 4 . The face-centered cubic structure capacitor according to claim 1 , wherein the first metal wire and the second metal wire perpendicularly cross each other to form a grid structure. 5. A capacitor with a face-centered cubic structure, characterized in that it includes: Several layers of first metal layers, which are composed of several first metal lines, several second metal lines and several first metal blocks, the first metal lines and the second metal lines cross each other to form a grid structure , each of the first metal blocks is arranged in each grid of the grid structure; Several layers of second metal layers, which are composed of several third metal lines, several fourth metal lines and several second metal blocks, the third metal lines and the fourth metal lines cross each other to form a grid structure , each of the second metal blocks is arranged in each grid of the grid structure, wherein each of the first metal layers and each of the second metal layers are alternately arranged; and Several connection layers, each connection layer connects each first metal layer and each second metal layer, the connection layer is composed of several third metal blocks and several fourth metal blocks, each of the The third metal block connects each of the first metal blocks to the intersection of the third metal line and the fourth metal line, and each of the fourth metal blocks connects each of the second metal blocks to the first metal line and the fourth metal line. the intersection of the second metal line. 6 . The face centered cubic structure capacitor according to claim 5 , wherein the first metal lines are parallel to each other, and the second metal lines are parallel to each other. 7 . The face centered cubic structure capacitor according to claim 5 , wherein the third metal lines are parallel to each other, and the fourth metal lines are parallel to each other. 8 . The face-centered cubic structure capacitor according to claim 5 , wherein the first metal wire and the second metal wire perpendicularly cross each other to form a grid structure. 9. A method for manufacturing a face-centered cubic structure capacitor, characterized in that it comprises: forming a first metal layer, the first metal layer is composed of several first metal lines, several second metal lines and several first metal blocks, the first metal lines and the second metal lines cross each other to form a grid structure, the first metal block is arranged in each grid structure formed by the intersecting of the first metal wire and the second metal wire; A contact layer is formed, the contact layer is composed of several third metal blocks and several fourth metal blocks, wherein each of the third metal blocks is connected to each of the first metal blocks, and each of the fourth metal blocks is connected to the the intersection of the first metal line and the second metal line; and forming a second metal layer, the second metal layer is composed of several third metal lines, several fourth metal lines and several second metal blocks, the third metal lines and the fourth metal lines cross each other to form A grid structure, the second metal block is arranged in each grid structure formed by the intersecting of the third metal line and the fourth metal line, wherein the second metal block and the fourth metal block of the connection layer connection, the third metal line and the fourth metal line are connected to the third metal block of the connection layer. 10. The manufacturing method according to claim 9, further comprising a step of filling the voids of the first metal layer with a dielectric material. 11. The manufacturing method according to claim 9, further comprising a step of filling the voids of the connecting layer with a dielectric material. 12. The manufacturing method according to claim 9, further comprising a step of filling the voids of the second metal layer with a dielectric material.

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