CN101246442B - memory access control method - Google Patents

Abstract

Cyclic redundancy check (CRC) is used to improve the error checking capability during memory access. During the reading process, part of the read data is sent to the outside of the memory through the CRC bus; and the CRC result and the rest of the read data are sent to the outside of the memory through the data bus.

Description

memory access control method

technical field

The present invention relates to a memory access control method, and in particular to a memory access control method that utilizes a cyclic redundancy check (CRC) to improve error checking capabilities. the

Background technique

In a communication system or a computer system, a cyclic redundancy check (CRC) can be used to improve the error checking capability. After data transmission or data storage, CRC can be used to check whether errors occurred during data transmission. In the process of data transmission, both the receiving and sending parties need to perform CRC calculations, and then one party can compare the CRC results calculated by both parties to know whether the received data has any errors. the

Please refer to FIG. 1 , which shows the prior art of applying CRC-16 to memory access control of a computer system. Here, the system clock is 800 MHz, the data bus DQ<7:0> is 8 bits, and the CRC bus CRC<1:0> is 2 bits for example. When CRC-16 is applied, the resulting CRC result is 16 bits. the

As shown in FIG. 1 , a main control circuit (such as a CPU) issues read commands R-A and R-B to the memory. In response to the read commands R-A and R-B, after several cycles, the memory fetches the internal data D-A and D-B, where "internal data" means that the data has not yet been placed in the data bus DQ<7:0>. The data D-A includes 8 bits A0-A7, and the data D-B includes 8 bits B0-B7. The memory controller will perform CRC operation CRC-AB according to the internal data D-A and D-B. the

When the memory is outputting data D-A and D-B, some groups of bits (such as A3 and B3) will be placed on the CRC bus CRC<1:0>, while other groups of bits will be placed on the data bus DQ<7: 0> on. Please note that in Figure 1, the blank box between A0 and A1 means that no data is being transmitted on the data bus DQ<7:0> at this time. the

When the data is sent out through the data bus DQ<7:0>, the CRC operation CRC-AB can be started. As shown in Figure 1, after the CRC operation CRC-AB is completed, the CRC operation result CRC-AB can be transmitted through the CRC bus CRC<1:0>. the

In this way, the data D-A and D-B can be read out from the memory, and the CRC result is output to the main control circuit. the

However, the disadvantages of this prior art technology are: (1) the hardware structure is complicated, the circuit area is high and the power consumption is high; (2) the delay (tCCD latency) between two read commands is very compact (tight), For example, it is 1.25ns, which makes the design difficult; (3) The time delay between sending the read command and outputting the data from the memory is too long; (4) In the process of calculating the CRC, data A and data B need to be temporarily stored, which increases the Design difficulty; (5) The operation of CRC needs to be completed in a very short time (taking Figure 1 as an example, 1.25ns), which is not easy to realize.

It is desirable to have a memory access control method that can improve the above-mentioned shortcomings of the prior art. the

Contents of the invention

The present invention provides a memory access control method. In the process of memory reading, the calculation result of cyclic redundancy check (CRC) is sent through the data bus, and a part of the read data is Sent over the Cyclic Redundancy Check (CRC) bus. During the memory writing process, data is received on the data bus and its corresponding CRC result is sent on the CRC bus. the

The invention provides a memory access control method. When performing CRC calculation, it is not necessary to keep two or more pieces of data at the same time, but only need to temporarily keep the data in CRC calculation. the

The present invention provides a memory access control method, comprising: sending a first read command to a memory; responding to the first read command, retrieving the first read data from the memory; executing the first read data CRC operation to obtain the first CRC result; transmit a certain part of the first read data through the data bus and transmit the remaining part of the first read data through the CRC bus; and transmit through the data bus First CRC result. the

In addition, the present invention also provides a memory access control method, including: issuing a first read command and a second read command to the memory; responding to the first read command, retrieving the first read command from the memory Data; execute the cyclic redundancy check (CRC) operation of the first read data to obtain a first cyclic redundancy check (CRC) result; respond to the second read command, fetch the second read from the memory Fetch data; execute the cyclic redundancy check (CRC) operation of the second read data to obtain the second cyclic redundancy check (CRC) result; transmit a part of the first read data through the data bus and pass A cyclic redundancy check (CRC) bus to transmit other parts of the first read data; transmit the first cyclic redundancy check (CRC) result via the data bus; transmit the second read data via the data bus a part and other parts of the second read data are transmitted through a CRC bus; and a second CRC result is transmitted through the data bus. the

In addition, the present invention further provides a memory access control method, including: sending a first write command and a first read command to the memory; transmitting the first write related to the first write command through the data bus data to the memory; perform a CRC operation on the first written data to obtain a first CRC result; transmit the first CRC result through the CRC bus; respond to a first read command, and retrieve the first read from the memory data; perform a CRC operation on the first read data to obtain a second CRC result; transmit a certain part of the first read data through the data bus and transmit the remaining part of the first read data through the CRC bus; and transmitting the second CRC result through the data bus. the

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings. the

Description of drawings

FIG. 1 shows a timing diagram of memory access control according to the prior art. the

FIG. 2 shows a timing diagram of memory read control according to an embodiment of the invention. the

FIG. 3 shows a timing diagram of the read-before-write control of the memory according to the second embodiment of the present invention. the

FIG. 4 is a schematic diagram showing the timing sequence of the write-before-read control of the memory according to the third embodiment of the present invention. the

R-A, R-B, R-C: Read command

D-A, A0～A7, D-B, B0～B7, D-C, C0～C7: Information

CRC-AB, CRC-A, CRC-B, CRC-C: CRC operation

W-A, W-B, W-C: write command

Detailed ways

In the present invention, during the memory reading process, the CRC result is sent on the data bus and part of the read data is sent on the CRC bus. During memory writing, data is received on the data bus and CRC results are sent on the CRC bus. In addition, when performing CRC calculation, it is not necessary to keep two or more pieces of data at the same time as in the prior art, but only need to temporarily keep the piece of data that is being CRC calculated. the

The first embodiment: read first and then read (read to read)

Please refer to FIG. 2 , which shows a timing diagram of memory read control according to the first embodiment of the present invention. Here, the system clock is 800MHz, the data bus DQ<7:0> is 8 bits, and the CRC bus CRC<1:0> is 2 bits as an example, and the CRC operation is explained using CRC-16 as an example. (The resulting CRC result is 16 bits). Of course, this embodiment is not limited thereto. For example, this embodiment may also apply other CRC technologies, such as CRC-32, to further improve the error checking capability. the

As shown in FIG. 2 , the main control circuit (such as CPU) sends read commands R-A and R-B to the memory. In response to the read commands R-A and R-B, after several cycles, the memory fetches the internal data D-A and D-B successively. Here, "internal data" means that the data has not yet been placed in the data bus DQ<7:0>. The data D-A includes 8 bits A0-A7, and the data D-B includes 8 bits B0-B7. the

After the data D-A is taken out, the CRC operation can be performed on the data D-A as soon as possible, as shown in FIG. 2 for CRC-A. Similarly, after the data D-B is taken out, the CRC operation can be performed on the data D-B as soon as possible, such as CRC-B shown in FIG. 2 . the

When data D-A is to be output, certain bits (such as A2 and A3) will be placed on the CRC bus CRC<1:0>, while other bits (such as A0～A1 and A4～A7) will be placed on Data bus on DQ<7:0>. Please note that in this embodiment, the CRC operation result CRC-A of the data D-A is placed on the data bus DQ<7:0> instead of the CRC bus CRC<1:0>. the

Similarly, when the data D-B is to be output, some groups of bits (such as B2 and B3) will be placed on the CRC bus CRC<1:0>, while other groups of bits (such as B0~B1 and B4~B7) Place it on the data bus DQ<7:0>. Likewise, the CRC operation result CRC-B of data D-B is placed on data bus DQ<7:0> instead of CRC bus CRC<1:0>. the

In this way, the data D-A and D-B can be read out from the memory, and the CRC result is output to the main control circuit. the

Although the command sequence in the first embodiment is read-read, those skilled in the art can know from the above description how to change the first embodiment to apply to other similar command sequences such as read-read-read. the

Second embodiment: first read and then write (read to write)

Please refer to FIG. 3 , which shows a timing diagram of memory read-before-write control according to a second embodiment of the present invention. Here, the system clock is 800MHz, the data bus DQ<7:0> is 8 bits, and the CRC bus CRC<1:0> is 2 bits as an example, and the CRC operation is explained using CRC-16 as an example. (The resulting CRC result is 16 bits). Of course, this embodiment is not limited thereto. For example, this embodiment may also apply other CRC technologies, such as CRC-32, to further improve the error checking capability. the

As shown in FIG. 3 , a main control circuit (such as a CPU) issues a read command R-A, and write commands W-B and W-C to the memory. In response to the read command R-A, after several cycles, the memory will fetch the internal data D-A. The data D-A includes 8 bits A0-A7. the

After the data D-A is taken out, the CRC operation can be performed on the data D-A as soon as possible, as shown in CRC-A in FIG. 3 . the

When data D-A is to be output, certain bits (such as A2 and A3) will be placed on the CRC bus CRC<1:0>, while other bits (such as A0～A1 and A4～A7) will be placed on Data bus on DQ<7:0>. Please note that in this embodiment, the CRC operation result CRC-A of the data D-A is placed on the data bus DQ<7:0> instead of the CRC bus CRC<1:0>. the

After the main control circuit sends the write command W-B, after several cycles, the main control circuit transmits the data B0-B7 to the memory through the data bus DQ<7:0>. After the data B0-B7 are received, the write command W-B can be executed to write the data D-B (including 8 byte groups B0-B7) into the memory. the

In this embodiment, it is not necessary to wait until all the data B0-B7 are received before starting the CRC calculation. Even, after receiving part of the data B0-B7, the CRC calculation can be started, such as CRC-B shown in FIG. 3 . After the CRC operation CRC-B is completed, the CRC operation CRC-B can be sent back to the main control circuit through the CRC bus CRC<1:0> for error checking. the

Similarly, after the main control circuit sends the write command W-C, after several cycles, the main control circuit transmits the data C0-C7 to the memory through the data bus DQ<7:0>. After all the data C0-C7 are received, the write command W-C can be executed to write the data D-C (including 8 byte groups C0-C7) into the memory. the

In this embodiment, it is not necessary to wait until all the data C0-C7 are received before starting the CRC calculation. Even, after receiving part of the data C0-C7, the CRC operation can be started, such as CRC-C shown in FIG. 3 . After the CRC operation CRC-C is completed, the CRC operation CRC-C can be sent back to the main control circuit through the CRC bus CRC<1:0> for error checking. the

In this way, the data D-A is read from the memory, the data D-B and D-C are written into the memory, and the CRC results (CRC-A, CRC-B and CRC-C) are sent back to the main control circuit. the

Although the command sequence shown in the second embodiment is read-write-write, those skilled in the art can know how to change the second embodiment to apply read-write-read or other similar command sequences from the above description. the

The third embodiment: write first and then read (write to read)

Please refer to FIG. 4 , which shows a timing diagram of the write-before-read control of the memory according to the third embodiment of the present invention. Here, the system clock is 800MHz, the data bus DQ<7:0> is 8 bits, and the CRC bus CRC<1:0> is 2 bits as an example, and the CRC operation is explained using CRC-16 as an example. (The resulting CRC result is 16 bits). Of course, this embodiment is not limited thereto. For example, this embodiment may also apply other CRC technologies, such as CRC-32, to further improve the error checking capability. the

As shown in FIG. 4 , the main control circuit (such as CPU) sends write commands W-A and W-B, and read commands R-C to the memory. the

After the main control circuit sends the write command W-A, after several cycles, the main control circuit transmits the data A0-A7 to the memory through the data bus DQ<7:0>. After the data A0-A7 are received, the write command W-A can be executed to write the data D-A (including 8 byte groups A0-A7) into the memory. the

In this embodiment, it is not necessary to wait until all the data A0-A7 are received before starting the CRC calculation. Even, after receiving part of the data A0-A7, the CRC calculation can be started, such as CRC-A shown in FIG. 4 . After the CRC operation CRC-A is completed, the CRC operation CRC-A can be sent back to the main control circuit through the CRC bus CRC<1:0> for error checking. the

Similarly, after the main control circuit sends the write command W-B, after a few cycles, the main control circuit transmits the data B0-B7 to the memory through the data bus DQ<7:0>. After all the data B0-B7 are received, the write command W-B can be executed to write the data D-B (including 8 byte groups B0-B7) into the memory. the

Similarly, in this embodiment, it is not necessary to wait until all the data B0-B7 are received before starting the CRC calculation. Even, after receiving part of the data B0-B7, the CRC operation can be started, such as CRC-B shown in FIG. 4 . After the CRC operation CRC-B is completed, the CRC operation CRC-B can be sent back to the main control circuit through the CRC bus CRC<1:0> for error checking. the

In response to the read command R-C, after several cycles, the memory will fetch the internal data D-C. Data D-C includes 8 bits C0-C7. the

After obtaining the internal data D-C, the CRC operation can be performed on the data D-C as soon as possible, as shown in FIG. 4 CRC-C. the

When outputting data D-C, certain bits (such as C2 and C3) will be placed on the CRC bus CRC<1:0>, while other bits (such as C0~C1 and C4~C7) will be placed on Data bus on DQ<7:0>. Please note that in this embodiment, the CRC operation result CRC-C of the data D-C is placed on the data bus DQ<7:0> instead of the CRC bus CRC<1:0>. the

In this way, the data D-A and D-B can be written into the memory and the data D-C can be read from the memory, and the CRC results (CRC-A, CRC-B and CRC-C) can be sent back to the main control circuit. the

Although the command sequence shown in the third embodiment is write-write-read, those skilled in the art can understand from the above description how to change the third embodiment to apply to write-read-write or other similar command sequences. the

In summary, the advantages of several embodiments of the present invention are: (1) the hardware structure is less complex, the circuit area is reduced and the power consumption is reduced; (2) the delay (tCCD latency) between two instructions is relatively moderate ( relaxed), such as 2.5ns, the design is easier; (3) in the process of calculating the CRC, there is no need to temporarily store several data at the same time, and the design difficulty is reduced; (4) the allowable calculation time of the CRC is longer (as shown in Figure 2 For example, 1.875ns), easier to realize; (5) There is still a high error checking rate. the

The embodiments of the present invention can be applied to high-speed/large-data-capacity memory (for example, DDR4), so as to meet the requirements of high-speed and large-data transmission. the

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and changes without departing from the spirit and scope of the present invention. Modification, therefore, the scope of protection of the present invention should be defined by the appended claims. the

Claims (13)

1. A memory access control method, characterized in that it comprises the following steps: issuing a first read command to a memory; Responding to the first read command, retrieving a first read data from the memory; performing an error checking operation on the first read data to obtain a first error checking result; transmitting a portion of the first read data via a data bus and transmitting another portion of the first read data via an error checking bus; and The first error checking result is transmitted through the data bus. 2. The method according to claim 1, further comprising: after issuing the first read command, issue a second read command to the memory; Responding to the second read command, retrieving a second read data from the memory; performing an error checking operation on the second read data to obtain a second error checking result; transmitting a portion of the second read data over the data bus and another portion of the second read data over the error checking bus; and The second error checking result is transmitted through the data bus. 3. The method of claim 1, further comprising: after issuing the first read command, issuing a first write command to the memory; transmitting a first write data related to the first write command to the memory through the data bus; performing an error checking operation on the first written data to obtain a second error checking result; and The second error checking result is transmitted through the error checking bus. 4. The method of claim 3, further comprising: after issuing the first write command, issue a second write command to the memory; transmitting a second write data related to the second write command to the memory through the data bus; performing an error checking operation on the second written data to obtain a third error checking result; and The third error checking result is transmitted through the error checking bus. 5. The method of claim 1, wherein the error checking operation is a cyclic redundancy check. 6. The method of claim 2, wherein the error checking operation is a cyclic redundancy check. 7. The method of claim 3, wherein the error checking operation is a cyclic redundancy check. the 8. The method of claim 4, wherein the error checking operation is a cyclic redundancy check. 9. A memory access control method, characterized in that it comprises the following steps: issuing a first read command and a second read command to a memory; Responding to the first read command, retrieving a first read data from the memory; performing a cyclic redundancy check on the first read data to obtain a first cyclic redundancy check result; Responding to the second read command, retrieving a second read data from the memory; performing a cyclic redundancy check on the second read data to obtain a second cyclic redundancy check result; transmitting a portion of the first read data via a data bus and transmitting the other portion of the first read data via a cyclic redundancy check bus; transmitting the first cyclic redundancy check result through the data bus; transmitting a portion of the second read data over the data bus and another portion of the second read data over the cyclic redundancy check bus; and The second CRC result is transmitted through the data bus. 10. A memory access control method, characterized in that it comprises the following steps: issuing a first write command and a first read command to a memory; transmitting a first write data related to the first write command to the memory through a data bus; performing an error checking operation on the first written data to obtain a first error checking result; transmitting the first error checking result through an error checking bus; Responding to the first read command, retrieving a first read data from the memory; performing an error checking operation on the first read data to obtain a second error checking result; transmitting a portion of the first read data over the data bus and another portion of the first read data over the error checking bus; and The second error checking result is transmitted through the data bus. 11. The method of claim 10, further comprising: issuing a second write command to the memory; transmitting a second write data related to the second write command to the memory through the data bus; performing an error checking operation on the second written data to obtain a third error checking result; and The third error checking result is transmitted through the error checking bus. 12. The method of claim 10, wherein the error checking operation is a cyclic redundancy check. the 13. The method of claim 11, wherein the error checking operation is a cyclic redundancy check. the

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