CN101246869A - Chip flip packaging structure for reducing substrate warpage and manufacturing method thereof - Google Patents

Abstract

A chip flip-chip packaging structure for reducing substrate warping includes a substrate, a chip (realdie), a plurality of first bumps, a dummy die, and a plurality of second bumps. The substrate has a first surface and a second surface opposite thereto. The chip is located on the first surface of the substrate and has an active surface. The first bumps are arranged between the active surface of the chip and the first surface of the substrate, so that the chip is electrically connected to the first surface of the substrate by the first bumps. The dummy chip is located on the second surface of the substrate and corresponds to the chip. The plurality of second bumps are arranged between the dummy chip and the second surface of the substrate, so that the dummy chip is connected to the second surface of the substrate by the second bumps.

Description

Chip flip-chip packaging structure for reducing substrate warpage and manufacturing method thereof

technical field

The invention relates to a chip flip-chip packaging structure and a manufacturing method thereof, and in particular to a chip flip-chip packaging structure suitable for reducing substrate warpage and a manufacturing method thereof.

Background technique

Flip-chip packaging is currently the most widely used semiconductor packaging technology. In the flip-chip packaging technology, an underfill is usually formed and filled between the flip-chip and the substrate. When performing a baking process to mature the primer, since the thermal expansion coefficients of the substrate and the primer are different, the substrate may be warped. In addition, after the reflow process, the difference in coefficient of thermal expansion (CTE dismatch) between the die and the substrate is also the cause of substrate warpage. In order to prevent the substrate from warping, heat sinks and heat dissipation rings are usually arranged on the substrate to reduce the degree of substrate warping.

FIG. 1 is a schematic cross-sectional view of a known flip-chip packaging structure. Please refer to FIG. 1 , the flip-chip package structure 100 mainly includes a substrate 110 , a flip-chip 120 , a primer 130 and a heat sink 140 . Wherein, the substrate 110 has an upper surface 111 and a lower surface 112 , and the flip chip 120 is located on the upper surface 111 of the substrate 110 . The flip chip 120 has an active surface 121 and a back surface 122 . A plurality of bumps 123 are formed on the active surface 121 for bonding the flip chip 120 and the substrate 110 . The primer 130 is filled between the flip chip 120 and the substrate 110 . The heat dissipation plate 140 is thermally coupled to the back surface 122 of the flip chip 120 by a thermal interface material 124 to enhance the heat dissipation effect of the flip chip 120 . And the heat dissipation plate 140 has a joint part 141 , and the joint part 14 is combined with an adhesive 113 around the upper surface 111 of the substrate 110 . Finally, a plurality of solder balls 150 are disposed on the lower surface 112 of the substrate 110 for externally connecting a circuit board.

Although disposing the heat dissipation plate 140 with the bonding portion 141 on the substrate 110 can reduce the warpage of the substrate 110 , however, the use of the heat dissipation plate has limited improvement on the warpage of large-sized products, and also increases the production cost. In addition, the bonding portion 141 of the heat sink 140 needs to be evenly attached to the upper surface 111 of the substrate 110 during the packaging process, which also increases the difficulty of the process.

Contents of the invention

The object of the present invention is to provide a flip-chip packaging structure with reduced substrate warpage and a manufacturing method thereof, so as to solve the problem of substrate warpage in the flip-chip packaging structure.

In order to achieve the above object, the present invention proposes a flip-chip packaging structure that reduces substrate warpage, which includes a substrate, a real die, a plurality of first bumps, a dummy die and a plurality of first bumps. Two bumps. The substrate has a first surface and a second surface opposite to it. The chip is located on the first surface of the substrate and has an active surface. The first bumps are disposed between the active surface of the chip and the first surface of the substrate, so that the chip is electrically connected to the first surface of the substrate through the first bumps. The dummy chip is located on the second surface of the substrate and corresponds to the chip. A plurality of second bumps are arranged between the dummy chip and the second surface of the substrate, so that the dummy chip is connected to the second surface of the substrate by the second bumps.

In an embodiment of the invention, the size of the virtual chip is smaller than the size of the chip.

In an embodiment of the present invention, the flip-chip packaging structure for reducing substrate warpage further includes a first primer and a second primer. The first primer is filled between the chip and the first surface of the substrate, and covers the first bump. The second primer is filled between the dummy chip and the second surface of the substrate, and covers the second bump.

In an embodiment of the present invention, the glass transition temperature of the second primer is higher than the glass transition temperature of the first primer.

The present invention also proposes a flip-chip packaging structure for reducing substrate warpage, which includes a substrate, a chip, a plurality of first bumps, a first primer and a second primer. The substrate has a first surface and a second surface opposite to it. The chip is located on the first surface of the substrate and has an active surface. The first bumps are disposed between the active surface of the chip and the first surface of the substrate, so that the chip is electrically connected to the first surface of the substrate through the first bumps. The first primer is filled on the chip and the first surface of the substrate, and covers the first bump. The second primer is disposed on the second surface of the substrate and corresponds to the first primer. Wherein, the glass transition temperature of the second primer is higher than the glass transition temperature of the first primer.

In an embodiment of the present invention, the flip-chip packaging structure for reducing substrate warpage further includes a dummy chip and a plurality of second bumps. Wherein, the dummy chip is located on the second surface of the substrate and corresponds to the chip. The second bumps are arranged between the dummy chip and the second surface of the substrate, so that the dummy chip is connected to the second surface of the substrate by the second bumps.

In an embodiment of the invention, the size of the virtual chip is smaller than the size of the chip.

The present invention also proposes a manufacturing method of a flip-chip packaging structure that reduces substrate warpage, including the following steps. Firstly, a substrate, a chip and a dummy chip are provided. Wherein, the substrate has a first surface and a second surface opposite to it, the chip has an active surface and a plurality of first bumps arranged on the active surface, and a plurality of first bumps are arranged on one surface of the dummy chip. Two bumps. Afterwards, the active surface of the chip is opposed to the first surface of the substrate, and the first bumps are reflowed, so that the chip is arranged on the first surface of the substrate in a way of flip-chip bonding through the first bumps. Finally, the dummy chip is arranged on the second surface of the substrate, and the second bumps are soldered back, so that the dummy chip is arranged on the second surface of the substrate in a way of flip-chip bonding through the second bumps.

In an embodiment of the present invention, the manufacturing method of the flip-chip packaging structure further includes the following steps. Firstly, a first primer is filled between the chip and the first surface of the substrate, so that the first primer covers the first bumps. Afterwards, a heating process is performed to cure the first primer.

In an embodiment of the present invention, the manufacturing method of the flip-chip packaging structure further includes the following steps. First, a second primer is filled between the dummy chip and the second surface of the substrate, so that the second primer covers the second bumps. Afterwards, a heating process is performed to cure the second primer.

In an embodiment of the present invention, the glass transition temperature of the second primer is higher than the glass transition temperature of the first primer.

In an embodiment of the invention, the size of the virtual chip is smaller than the size of the chip.

The present invention also proposes a manufacturing method of a flip-chip packaging structure that reduces substrate warpage, including the following steps. Firstly, a substrate and a chip are provided. Wherein, the substrate has a first surface and a second surface opposite to it; the chip has an active surface and a plurality of first bumps arranged on the active surface. Afterwards, the active surface of the chip is opposed to the first surface of the substrate, and the first bumps are reflowed, so that the chip is arranged on the first surface of the substrate in a flip-chip bonding manner through the first bumps. Next, filling a first primer between the chip and the first surface of the substrate, so that the first primer covers the first bumps. Afterwards, a heating process is performed to cure the first primer. Next, a second primer corresponding to the first primer is formed on the second surface of the substrate. Finally, a heating process is performed to cure the second primer.

In an embodiment of the present invention, the glass transition temperature of the second primer is higher than the glass transition temperature of the first primer.

The flip-chip packaging structure and its manufacturing method for reducing substrate warping of the present invention mainly include setting a dummy chip flip-chip bonded to the substrate on the back of the substrate and/or performing primer filling and baking processes to cause the substrate to reverse. The warping of the substrate can be suppressed after the reflow and glue dispensing process, and then the problem of substrate warping in the known flip-chip packaging structure can be solved.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a known flip-chip packaging structure.

2A-2H are schematic cross-sectional flow diagrams of a fabrication method of a flip-chip packaging structure with reduced substrate warpage according to an embodiment of the present invention.

3A-3F are schematic cross-sectional flow diagrams of a manufacturing method of a flip-chip packaging structure with reduced substrate warpage according to another embodiment of the present invention.

Explanation of main component symbols in the attached drawings:

100: Chip flip-chip package structure

110: Substrate

111: upper surface

112: lower surface

113: Adhesive glue

120: flip chip

121: active side

122: back

123: bump

130: primer

140: cooling plate

141: Junction

210: Substrate

210a: first surface

210b: second surface

220: chip

220a: active surface

222: First bump

230: virtual chip

230a: surface

232: second bump

240: the first primer

250, 250': second primer

Detailed ways

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited and described in detail with accompanying drawings as follows.

2A-2H are schematic cross-sectional flow diagrams of a fabrication method of a flip-chip packaging structure with reduced substrate warpage according to an embodiment of the present invention. First, as shown in FIG. 2A , a substrate 210 , a chip 220 and a dummy chip 230 are provided. The substrate 210 has a first surface 210a and a second surface 210b opposite thereto; the chip 220 has an active surface 220a and a plurality of first bumps 222 disposed on the active surface 220a; and the surface 230a of the dummy chip 230 A plurality of second bumps 232 are disposed thereon.

Afterwards, as shown in FIG. 2B, the active surface 220a of the chip 220 is opposed to the first surface 210a of the substrate 210, and these first bumps 222 are reflowed, so that the chip 220 is flip-chip by these first bumps 222. The bonding method is configured on the first surface 210 a of the substrate 210 . As shown in FIG. 2B , since the thermal expansion coefficients of the substrate 210 and the chip 220 are different, the substrate 210 will warp downward after the reflow process.

In order to improve the downward warpage of the substrate 210 after the reflow process, as shown in FIG. 2C , the present invention first turns the substrate 210 upside down, and then disposes the dummy chip 230 on the second surface 210 b of the substrate 210 , and these second bumps 232 are reflowed, so that the dummy chip 230 is disposed on the second surface 210b of the substrate 210 by flip-chip bonding through the second bumps 232 . As shown in FIG. 2D , since the thermal expansion coefficients of the substrate 210 and the dummy chip 230 are different, the substrate 210 will also warp downward after the reflow process, thereby overcoming the problem of the substrate 210 in FIG. 2B . The resulting warping and leveling of the substrate 210 . In this way, the general flow of the manufacturing method of the flip-chip packaging structure with reduced substrate warpage of the present invention is completed. Furthermore, the position of the virtual chip 230 disposed on the second surface 210b of the substrate 210 corresponds to the position of the chip 220 disposed on the first surface 210a of the substrate 210, and the size of the virtual chip 230 is preferably smaller than that of the chip 220 The size of the substrate 210 is helpful to equalize the original warping of the substrate 210 .

In order to protect the first bump 222 connected between the substrate 210 and the chip 220 from damage and damage, after the steps shown in FIG. 2D are completed, as shown in FIG. A first primer 240 is filled between a surface 210 a such that the first primer 240 covers the first bumps 222 . Afterwards, as shown in FIG. 2F , a heating process is performed to cure the first primer 240 .

However, after the first primer 240 is heated, as shown in FIG. 2F , the substrate 210 will warp downward again. Therefore, as shown in FIG. 2G, the substrate 210 can be turned upside down first, and a second primer 250 is filled between the dummy chip 230 and the second surface 210b of the substrate 210, so that the second primer 250 covers these first primers. Two bumps 232 . After that, as shown in FIG. 2H , a heating process is performed to cure the second primer 250 . Since the substrate 210 will warp downward again after the second primer 250 is heated, the warping of the substrate 210 in FIG. 2F can be overcome and the substrate 210 can be leveled. Since the material properties of the selected second primer 250 will affect the degree of warpage of the substrate 210, users can choose second primers 250 with different glass transition temperatures to improve and control the warpage of the substrate 210. degree. In an embodiment of the present invention, the glass transition temperature of the second primer 250 is preferably higher than the glass transition temperature of the first primer 240 . In this way, after the process of dispensing and heating the second primer 250, the degree of warping of the substrate 210 can suppress the phenomenon of warping of the substrate 210 after the first primer 240 is baked, thereby leveling the substrate 210 .

3A-3F are schematic cross-sectional flow diagrams of a manufacturing method of a flip-chip packaging structure with reduced substrate warpage according to another embodiment of the present invention. First, as shown in FIG. 3A , a substrate 210 and a chip 220 are provided. The substrate 210 has a first surface 210a and a second surface 210b opposite thereto; and the chip 220 has an active surface 220a and a plurality of first bumps 222 disposed on the active surface 220a. Afterwards, please refer to FIG. 3B, the active surface 220a of the chip 220 is opposed to the first surface 210a of the substrate 210, and these first bumps 222 are reflowed, so that the chip 220 is flipped by these first bumps 222. It is disposed on the first surface 210 a of the substrate 210 in a mounting and bonding manner. As shown in FIG. 3B , since the thermal expansion coefficients of the substrate 210 and the chip 220 are different, the substrate 210 will warp downward after the reflow process.

In order to protect the first bump 222 connected between the substrate 210 and the chip 220 from damage and moisture, after the steps shown in FIG. 3B are completed, as shown in FIG. A first primer 240 is filled between the 210 a, so that the first primer 240 covers the first bumps 222 . Afterwards, as shown in FIG. 3D , a heating process is performed to cure the first primer 240 . As shown in FIG. 3D , after the filling and heating processes of the first primer 240 , the degree of downward warping of the substrate 210 is more obvious.

Next, as shown in FIG. 3E , a second primer 250' corresponding to the first primer 240 is formed on the second surface 210b of the substrate 210. Finally, as shown in FIG. 3F , a heating process is performed to cure the second primer 250 ′, so that the filling and heating process of the second primer 250 ′ overcomes the warpage of the substrate 210 caused in the previous step of FIG. 3D phenomenon, and then level the substrate 210 .

In summary, the flip-chip packaging structure and its manufacturing method for reducing substrate warpage of the present invention are mainly to arrange a dummy chip flip-chip bonded to the substrate on the back of the substrate and/or perform primer filling and baking processes , to make the substrate warp in the opposite direction, so as to suppress the warpage of the substrate after the reflow and glue dispensing process, and then level the substrate. In addition, users can choose different sizes of dummy chips and primers with different glass transition temperatures to control the degree of reverse warpage of the substrate, and then level the substrate.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the content defined in the scope of claims of the application.

Claims (13)

1. A flip-chip packaging structure that reduces substrate warpage, characterized in that it includes: a substrate having a first surface and a second surface opposite thereto; a chip located on the first surface of the substrate and having an active surface; A plurality of first bumps are arranged between the active surface of the chip and the first surface of the substrate, so that the chip is electrically connected to the substrate by the first bumps said first surface; a dummy chip located on the second surface of the substrate and corresponding to the chip; and A plurality of second bumps are arranged between the dummy chip and the second surface of the substrate, so that the dummy chip is connected to the second surface of the substrate by the second bumps. 2. The flip-chip packaging structure for reducing substrate warpage according to claim 1, wherein the size of the dummy chip is smaller than the size of the chip. 3. The flip-chip packaging structure for reducing substrate warpage according to claim 1, characterized in that it comprises a first primer and a second primer, wherein the first primer is filled between the chip and the between the first surface of the substrate and cover the first bump, and the second primer is filled between the dummy chip and the second surface of the substrate and covers the second bump piece. 4 . The flip-chip packaging structure for reducing substrate warpage according to claim 3 , wherein the glass transition temperature of the second primer is higher than the glass transition temperature of the first primer. 5. A flip-chip packaging structure that reduces substrate warpage, characterized in that it includes: a substrate having a first surface and a second surface opposite thereto; a chip located on the first surface of the substrate and having an active surface; A plurality of first bumps are arranged between the active surface of the chip and the first surface of the substrate, so that the chip is electrically connected to all the substrates by the first bumps the first surface; a first primer, filled in the chip and the first surface of the substrate, and covering the first bump; and A second primer, disposed on the second surface of the substrate, and corresponding to the first primer, wherein the glass transition temperature of the second primer is greater than the glass transition temperature of the first primer temperature. 6. The flip-chip packaging structure for reducing substrate warpage according to claim 5, characterized in that it comprises a dummy chip and a plurality of second bumps, wherein the dummy chip is located on the second bump of the substrate. surface, and corresponding to the chip, and the second bump is arranged between the dummy chip and the second surface of the substrate, so that the dummy chip is connected to the second bump by the second bump The second surface of the substrate. 7. The flip-chip packaging structure for reducing substrate warpage according to claim 6, wherein the size of the dummy chip is smaller than the size of the chip. 8. A method for manufacturing a flip-chip packaging structure that reduces substrate warpage, characterized in that it includes: A substrate, a chip and a dummy chip are provided, wherein the substrate has a first surface and a second surface opposite thereto, the chip has an active surface and a plurality of first bumps arranged on the active surface, and the dummy A plurality of second bumps are arranged on the surface of the chip; The active surface of the chip is opposite to the first surface of the substrate, and the first bump is reflowed, so that the chip is flip-chip bonded by the first bump disposed on the first surface of the substrate; and Disposing the dummy chip on the second surface of the substrate, and reflowing the second bumps, so that the dummy chip is flip-chip bonded by the second bumps on the on the second surface of the substrate. 9. The manufacturing method of flip-chip packaging structure for reducing substrate warpage according to claim 8, characterized in that it comprises: filling a first primer between the chip and the first surface of the substrate, so that the first primer covers the first bump; performing a heating process to cure the first primer; filling a second primer between the dummy chip and the second surface of the substrate, so that the second primer covers the second bump; and A heating process is performed to cure the second primer. 10. The manufacturing method of flip-chip package structure for reducing substrate warpage according to claim 9, characterized in that the glass transition temperature of the second primer is higher than the glass transition temperature of the first primer . 11. The manufacturing method of flip-chip packaging structure with reduced substrate warpage according to claim 8, characterized in that the size of the dummy chip is smaller than the size of the chip. 12. A method for manufacturing a flip-chip packaging structure that reduces substrate warpage, characterized in that it includes: A substrate and a chip are provided, wherein the substrate has a first surface and a second surface opposite thereto, and the chip has an active surface and a plurality of first bumps arranged on the active surface; The active surface of the chip is opposite to the first surface of the substrate, and the first bump is reflowed, so that the chip is flip-chip bonded by the first bump configured on the first surface of the substrate; filling a first primer between the chip and the first surface of the substrate, so that the first primer covers the first bump; performing a heating process to cure the first primer; forming a second primer corresponding to the first primer on the second surface of the substrate; and A heating process is performed to cure the second primer. 13. The manufacturing method of flip-chip packaging structure for reducing substrate warpage according to claim 12, characterized in that, the glass transition temperature of the second primer is higher than the glass transition temperature of the first primer .

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