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CN101256997A - Package structure capable of reducing package stress - Google Patents

Package structure capable of reducing package stress Download PDF

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Publication number
CN101256997A
CN101256997A CNA2008100834258A CN200810083425A CN101256997A CN 101256997 A CN101256997 A CN 101256997A CN A2008100834258 A CNA2008100834258 A CN A2008100834258A CN 200810083425 A CN200810083425 A CN 200810083425A CN 101256997 A CN101256997 A CN 101256997A
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CN
China
Prior art keywords
sealant
transition temperature
glass transition
chip
structure capable
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Granted
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CNA2008100834258A
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Chinese (zh)
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CN100580918C (en
Inventor
王维中
王盟仁
黄东鸿
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN200810083425A priority Critical patent/CN100580918C/en
Publication of CN101256997A publication Critical patent/CN101256997A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

The invention discloses a packaging structure capable of reducing packaging stress, which mainly comprises a loader, an intermediate substrate, a plurality of conductive elements, a first sealant, a chip and a second sealant. The intermediate substrate is arranged on the loader, the conductive element is electrically connected with the intermediate substrate and the loader, the first sealant covers the conductive element, the plurality of bumps of the chip are jointed to the intermediate substrate, and the second sealant covers the bumps, wherein the first glass transition temperature of the first sealant is higher than the second glass transition temperature of the second sealant. Because the glass transition temperature between the first sealant and the second sealant is different, and the first glass transition temperature of the first sealant is higher than the second glass transition temperature of the second sealant, the stress in the packaging structure is reduced, and the yield of products is further improved.

Description

可降低封装应力的封装构造 Package structure that reduces package stress

技术领域technical field

本发明涉及一种封装构造，特别涉及一种可降低封装应力的封装构造。The invention relates to a packaging structure, in particular to a packaging structure capable of reducing packaging stress.

背景技术Background technique

已知封装构造主要包含承载器、芯片、中介基板以及密封胶，其中该芯片与该中介基板可通过该芯片的多个凸块形成电性连接，而该中介基板与该承载器的电性则需另由多个导电元件来形成电性连接，且为了保护该芯片的该凸块与该导电元件，必须以该密封胶将该凸块与该导电元件包覆，然而在封装工艺的过程中，由于该承载器、该芯片与该中介基板三者的热膨胀系数不同，但却使用相同的密封胶，使得该承载器、该芯片与该中介基板因受热产生形变而造成内应力，故已知封装构造会因为应力作用而导致电性连接失败，增加产品不成品率。The known packaging structure mainly includes a carrier, a chip, an intermediary substrate and a sealant, wherein the chip and the intermediary substrate can be electrically connected through a plurality of bumps of the chip, and the electrical properties of the intermediary substrate and the carrier are A plurality of conductive elements are required to form an electrical connection, and in order to protect the bump and the conductive element of the chip, the bump and the conductive element must be covered with the sealant. However, during the packaging process Since the thermal expansion coefficients of the carrier, the chip and the intermediary substrate are different, but the same sealant is used, the carrier, the chip and the intermediary substrate are deformed by heat and cause internal stress, so it is known The package structure will lead to electrical connection failure due to stress, increasing the product failure rate.

发明内容Contents of the invention

本发明的主要目的在于提供一种可降低封装应力的封装构造，承载器、中介基板、多个第一导电元件、第一密封胶、芯片以及第二密封胶。该承载器的上表面设置有多个连接垫，该承载器的下表面设置有多个球垫，该中介基板设置于该承载器的该上表面，该中介基板具有第一表面、第二表面及多个导通孔，该导通孔电性导通该第一表面的多个第一接点与该第二表面的多个第二接点，该第一导电元件设置于该承载器与该中介基板之间并电性连接该中介基板与该承载器，该第一密封胶包覆该第一导电元件，该第一密封胶具有第一玻璃转化温度，该芯片倒装焊接合于该中介基板，该芯片的多个凸块接合至该中介基板的该第一接点，该第二密封胶包覆该凸块，该第二密封胶具有第二玻璃转化温度，其中该第一密封胶的该第一玻璃转化温度大于该第二密封胶的该第二玻璃转化温度。本发明的功效在于包覆该第一导电元件的该第一密封胶与包覆该凸块的该第二密封胶二者间的玻璃转化温度不同，且该第一密封胶的该第一玻璃转化温度大于该第二密封胶的该第二玻璃转化温度，此种封装构造可降低封装构造内的应力作用，使得产品成品率提高。The main purpose of the present invention is to provide a packaging structure capable of reducing packaging stress, a carrier, an intermediary substrate, a plurality of first conductive elements, a first sealant, a chip and a second sealant. The upper surface of the carrier is provided with a plurality of connection pads, the lower surface of the carrier is provided with a plurality of ball pads, the intermediate substrate is arranged on the upper surface of the carrier, the intermediate substrate has a first surface, a second surface and a plurality of via holes, the via holes electrically connect the plurality of first contacts on the first surface and the plurality of second contacts on the second surface, the first conductive element is arranged on the carrier and the intermediary The substrates are electrically connected to the intermediate substrate and the carrier, the first sealant covers the first conductive element, the first sealant has a first glass transition temperature, and the chip is flip-chip bonded to the intermediate substrate , a plurality of bumps of the chip are bonded to the first joints of the interposer substrate, the second sealant covers the bumps, the second sealant has a second glass transition temperature, wherein the first sealant has a second glass transition temperature The first glass transition temperature is higher than the second glass transition temperature of the second sealant. The efficacy of the present invention lies in that the glass transition temperature between the first sealant covering the first conductive element and the second sealant covering the bump is different, and the first glass of the first sealant The transition temperature is higher than the second glass transition temperature of the second sealant, and this kind of packaging structure can reduce the stress in the packaging structure, so that the yield of products can be improved.

依本发明的一种可降低封装应力的封装构造主要包含承载器、中介基板、多个第一导电元件、第一密封胶、芯片以及第二密封胶。该承载器具有上表面与下表面，该上表面设置有多个连接垫，该下表面设置有多个球垫，该中介基板设置于该承载器的该上表面，该中介基板具有第一表面、第二表面及多个导通孔，该第一表面设置有多个第一接点，该第二表面设置有多个第二接点，该导通孔电性导通该第一接点与该第二接点，该第一导电元件设置于该承载器与该中介基板之间并电性连接该中介基板与该承载器，该第一密封胶包覆该第一导电元件，该第一密封胶具有第一玻璃转化温度，该芯片倒装焊接合于该中介基板，该芯片具有多个凸块，该凸块接合至该中介基板的该第一接点，该第二密封胶包覆该凸块，该第二密封胶具有第二玻璃转化温度，其中该第一密封胶的该第一玻璃转化温度大于该第二密封胶的该第二玻璃转化温度。A packaging structure capable of reducing packaging stress according to the present invention mainly includes a carrier, an intermediary substrate, a plurality of first conductive elements, a first sealant, a chip, and a second sealant. The carrier has an upper surface and a lower surface, the upper surface is provided with a plurality of connection pads, the lower surface is provided with a plurality of ball pads, the intermediate substrate is arranged on the upper surface of the carrier, and the intermediate substrate has a first surface , a second surface and a plurality of via holes, the first surface is provided with a plurality of first contacts, the second surface is provided with a plurality of second contacts, and the via hole is electrically connected to the first contact and the second contact Two contacts, the first conductive element is arranged between the carrier and the intermediary substrate and electrically connected the intermediary substrate and the carrier, the first sealant covers the first conductive element, and the first sealant has a first glass transition temperature, the chip is flip-chip bonded to the intermediary substrate, the chip has a plurality of bumps, the bumps are bonded to the first contact of the intermediary substrate, the second sealant covers the bumps, The second sealant has a second glass transition temperature, wherein the first glass transition temperature of the first sealant is greater than the second glass transition temperature of the second sealant.

附图说明Description of drawings

图1为依据本发明第一具体实施例的一种可降低封装应力的封装构造的截面示意图。FIG. 1 is a schematic cross-sectional view of a packaging structure capable of reducing packaging stress according to a first embodiment of the present invention.

图2为依据本发明第二具体实施例的另一种可降低封装应力的封装构造的截面示意图。2 is a schematic cross-sectional view of another packaging structure capable of reducing packaging stress according to a second embodiment of the present invention.

附图标记说明Explanation of reference signs

100封装构造       110承载器100 package structure 110 carrier

111上表面         112下表面111 upper surface 112 lower surface

113连接垫         114球垫113 connection pad 114 ball pad

120中介基板       121第一表面120 intermediary substrate 121 first surface

122第二表面       123导通孔122 second surface 123 via hole

124第一接点       125第二接点124 first contact 125 second contact

126集成化无源元件 130第一导电元件126 Integrated passive components 130 First conductive component

140第一密封胶     150芯片140 first sealant 150 chips

151有源面         152凸块151 active surface 152 bump

160第二密封胶     170第二导电元件160 second sealant 170 second conductive element

具体实施方式Detailed ways

请参阅图1，依据本发明的一具体实施例揭示一种可降低封装应力的封装构造100，其包含有一承载器110、中介基板120、多个第一导电元件130、第一密封胶140、芯片150以及第二密封胶160。该承载器110具有上表面111与下表面112，该承载器110可选自于有机基板或导线架，在本实施例中，该承载器110为有机基板，该上表面111设置有多个连接垫113，该下表面112设置有多个球垫114，该中介基板120设置于该承载器110的该上表面111，该中介基板120的材料为硅，该中介基板120具有第一表面121、第二表面122及多个导通孔123，该第一表面121设置有多个第一接点124，该第二表面122设置有多个第二接点125，该导通孔123电性导通该第一接点124与该第二接点125，优选地，该中介基板120另具有至少一集成化无源元件(Integrated Passive Device，IPD)126，该集成化无源元件126嵌设于该中介基板120的该第一表面121。该第一导电元件130设置于该承载器110与该中介基板120之间并电性连接该中介基板120与该承载器110，该第一导电元件130可为凸块且电性连接该中介基板120的该第二接点125与该承载器110的该连接垫113，该第一密封胶140包覆该第一导电元件130，该第一密封胶140具有第一玻璃转化温度(first glass transition temperature，Tg1)，该第一密封胶140的该第一玻璃转化温度介于120至160度之间，优选地，该第一密封胶140的该第一玻璃转化温度为140度。该芯片150倒装焊接合于该中介基板120，在本实施例中，该芯片150为功能性芯片，该芯片150的一有源面151具有多个凸块152，该凸块152接合至该中介基板120的该第一接点124使该芯片150与该中介基板120形成电性连接，且通过该中介基板120电性连接于该承载器110，在本实施例中，该中介基板120的尺寸大于该芯片150的尺寸，或者，如图2所示，该芯片150的尺寸可等于该中介基板120的尺寸。请再参阅图1，该第二密封胶160包覆该凸块152，该第二密封胶160具有第二玻璃转化温度(second glass transition temperature，Tg2)，其中该第一密封胶140的该第一玻璃转化温度大于该第二密封胶160的该第二玻璃转化温度，该第二密封胶160的该第二玻璃转化温度小于100度且该第二密封胶160的该第二玻璃转化温度介于50至90度之间，优选地，该第二密封胶160的该第二玻璃转化温度为70度，此外，该封装构造100另包含有多个第二导电元件170，该第二导电元件170可为焊球且设置于该承载器110的该球垫114，以外接印刷电路基板(图未绘出)。由于包覆该第一导电元件130的该第一密封胶140与包覆该凸块152的该第二密封胶160二者间的玻璃转化温度并不相同，故本发明的功效在于通过该第一密封胶140的该第一玻璃转化温度大于该第二密封胶160的该第二玻璃转化温度，使得该封装构造100内的应力降低，进而提高产品成品率。Please refer to FIG. 1 , according to a specific embodiment of the present invention, a packaging structure 100 capable of reducing packaging stress is disclosed, which includes a carrier 110, an intermediary substrate 120, a plurality of first conductive elements 130, a first sealant 140, The chip 150 and the second sealant 160 . The carrier 110 has an upper surface 111 and a lower surface 112. The carrier 110 can be selected from an organic substrate or a lead frame. In this embodiment, the carrier 110 is an organic substrate, and the upper surface 111 is provided with a plurality of connections. Pad 113, the lower surface 112 is provided with a plurality of ball pads 114, the intermediary substrate 120 is arranged on the upper surface 111 of the carrier 110, the material of the intermediary substrate 120 is silicon, and the intermediary substrate 120 has a first surface 121, The second surface 122 and a plurality of via holes 123, the first surface 121 is provided with a plurality of first contacts 124, the second surface 122 is provided with a plurality of second contacts 125, the via holes 123 are electrically connected to the The first contact 124 and the second contact 125, preferably, the intermediary substrate 120 further has at least one integrated passive device (Integrated Passive Device, IPD) 126, and the integrated passive device 126 is embedded in the intermediary substrate 120 of the first surface 121 . The first conductive element 130 is disposed between the carrier 110 and the intermediary substrate 120 and is electrically connected to the intermediary substrate 120 and the carrier 110. The first conductive element 130 can be a bump and is electrically connected to the intermediary substrate. The second contact 125 of 120 and the connection pad 113 of the carrier 110, the first sealant 140 covers the first conductive element 130, the first sealant 140 has a first glass transition temperature (first glass transition temperature) , Tg 1 ), the first glass transition temperature of the first sealant 140 is between 120 and 160 degrees, preferably, the first glass transition temperature of the first sealant 140 is 140 degrees. The chip 150 is flip-chip soldered to the intermediary substrate 120. In this embodiment, the chip 150 is a functional chip. An active surface 151 of the chip 150 has a plurality of bumps 152, and the bumps 152 are bonded to the The first contact 124 of the intermediary substrate 120 enables the chip 150 to form an electrical connection with the intermediary substrate 120, and is electrically connected to the carrier 110 through the intermediary substrate 120. In this embodiment, the size of the intermediary substrate 120 larger than the size of the chip 150 , or, as shown in FIG. 2 , the size of the chip 150 may be equal to the size of the interposer substrate 120 . Please refer to FIG. 1 again, the second sealant 160 covers the bump 152, the second sealant 160 has a second glass transition temperature (second glass transition temperature, Tg 2 ), wherein the first sealant 140 The first glass transition temperature is greater than the second glass transition temperature of the second sealant 160, the second glass transition temperature of the second sealant 160 is less than 100 degrees and the second glass transition temperature of the second sealant 160 Between 50°C and 90°C, preferably, the second glass transition temperature of the second sealant 160 is 70°C, in addition, the packaging structure 100 further includes a plurality of second conductive elements 170, the second conductive The components 170 can be solder balls and are disposed on the ball pads 114 of the carrier 110 and externally connected to a printed circuit board (not shown). Since the glass transition temperatures between the first sealant 140 covering the first conductive element 130 and the second sealant 160 covering the bump 152 are different, the effect of the present invention lies in The first glass transition temperature of a sealant 140 is higher than the second glass transition temperature of the second sealant 160 , so that the stress in the packaging structure 100 is reduced, thereby improving product yield.

本发明的保护范围当视后附的权利要求所界定的为准，本领域技术人员在不脱离本发明的精神和范围内所作的任何变化与修改，均属于本发明的保护范围。The scope of protection of the present invention shall be defined by the appended claims. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall all belong to the scope of protection of the present invention.

Claims (10)

1、一种可降低封装应力的封装构造，其包含：1. A packaging structure capable of reducing packaging stress, comprising: 承载器，其具有上表面与下表面，该上表面设置有多个连接垫，该下表面设置有多个球垫；The carrier has an upper surface and a lower surface, the upper surface is provided with a plurality of connecting pads, and the lower surface is provided with a plurality of ball pads; 中介基板，其设置于该承载器的该上表面，该中介基板具有第一表面、第二表面及多个导通孔，该第一表面设置有多个第一接点，该第二表面设置有多个第二接点，该导通孔电性导通该第一接点与该第二接点；An intermediary substrate, which is arranged on the upper surface of the carrier, the intermediary substrate has a first surface, a second surface and a plurality of via holes, the first surface is provided with a plurality of first contacts, and the second surface is provided with a plurality of second contacts, the via hole electrically connects the first contact and the second contact; 多个第一导电元件，其设置于该承载器与该中介基板之间并电性连接该中介基板与该承载器；a plurality of first conductive elements, which are arranged between the carrier and the intermediary substrate and electrically connect the intermediary substrate and the carrier; 第一密封胶，其包覆该第一导电元件，该第一密封胶具有第一玻璃转化温度；a first sealant covering the first conductive element, the first sealant having a first glass transition temperature; 芯片，其倒装焊接合于该中介基板，该芯片具有多个凸块，该凸块接合至该中介基板的该第一接点；以及a chip flip-chip bonded to the interposer substrate, the chip having a plurality of bumps bonded to the first contacts of the interposer substrate; and 第二密封胶，其包覆该凸块，该第二密封胶具有第二玻璃转化温度，其中该第一密封胶的该第一玻璃转化温度大于该第二密封胶的该第二玻璃转化温度。A second sealant covering the bump, the second sealant having a second glass transition temperature, wherein the first glass transition temperature of the first sealant is greater than the second glass transition temperature of the second sealant . 2、如权利要求1所述的可降低封装应力的封装构造，其中该第二密封胶的该第二玻璃转化温度小于100度。2. The packaging structure capable of reducing packaging stress as claimed in claim 1, wherein the second glass transition temperature of the second sealant is less than 100 degrees. 3、如权利要求1所述的可降低封装应力的封装构造，其中该第一密封胶的该第一玻璃转化温度介于120至160度之间。3. The package structure capable of reducing package stress as claimed in claim 1, wherein the first glass transition temperature of the first sealant is between 120°C and 160°C. 4、如权利要求1所述的可降低封装应力的封装构造，其中该芯片为功能性芯片。4. The packaging structure capable of reducing packaging stress as claimed in claim 1, wherein the chip is a functional chip. 5、如权利要求1所述的可降低封装应力的封装构造，其中该芯片的尺寸等于该中介基板的尺寸。5. The packaging structure capable of reducing packaging stress as claimed in claim 1, wherein the size of the chip is equal to the size of the intermediary substrate. 6、如权利要求1所述的可降低封装应力的封装构造，其中该中介基板的尺寸大于该芯片的尺寸。6. The packaging structure capable of reducing packaging stress as claimed in claim 1, wherein the size of the intermediary substrate is larger than the size of the chip. 7、如权利要求1所述的可降低封装应力的封装构造，其中该中介基板的材料为硅。7. The packaging structure capable of reducing packaging stress as claimed in claim 1, wherein the material of the intermediary substrate is silicon. 8、如权利要求1所述的可降低封装应力的封装构造，其另包含有多个第二导电元件，该第二导电元件设置于该承载器的该球垫。8. The packaging structure capable of reducing packaging stress as claimed in claim 1, further comprising a plurality of second conductive elements, the second conductive elements are disposed on the ball pads of the carrier. 9、如权利要求1所述的可降低封装应力的封装构造，其中该承载器选自于有机基板或导线架。9. The packaging structure capable of reducing packaging stress as claimed in claim 1, wherein the carrier is selected from an organic substrate or a lead frame. 10、如权利要求1所述的可降低封装应力的封装构造，其中该中介基板另具有至少一集成化无源元件。10. The packaging structure capable of reducing packaging stress as claimed in claim 1, wherein the intermediary substrate further has at least one integrated passive component.
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