CN101288159B - Semiconductor device having a polysilicon electrode - Google Patents
Semiconductor device having a polysilicon electrode Download PDFInfo
- Publication number
- CN101288159B CN101288159B CN2006800213073A CN200680021307A CN101288159B CN 101288159 B CN101288159 B CN 101288159B CN 2006800213073 A CN2006800213073 A CN 2006800213073A CN 200680021307 A CN200680021307 A CN 200680021307A CN 101288159 B CN101288159 B CN 101288159B
- Authority
- CN
- China
- Prior art keywords
- gate electrode
- polysilicon
- semiconductor substrate
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 23
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 239000007790 solid phase Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 abstract description 18
- 150000002500 ions Chemical class 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000004913 activation Effects 0.000 abstract description 4
- 238000010849 ion bombardment Methods 0.000 abstract description 2
- 238000002425 crystallisation Methods 0.000 description 13
- 230000008025 crystallization Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000002513 implantation Methods 0.000 description 8
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001376 precipitating effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
一种制造例如MOS晶体管的半导体器件的方法。所述器件包括在半导体基片(12)中形成的多晶硅栅极(10)和掺杂区(22，24)，它们通过一个沟道区(26)分隔开。所述半导体基片的暴露表面例如通过离子轰击被非结晶化，以便在加温退火期间禁止掺杂剂离子的随后扩散。低热预算对于所述激活和多晶硅再生长是有利的，以便确保用于所述源极/漏极区域的突变掺杂分布图。因此所述栅电极的上部(10b)保持非晶态。所述栅电极的上部被除去以便允许与所述多晶硅下部(10a)产生低电阻接触。
A method of manufacturing a semiconductor device such as a MOS transistor. The device includes a polysilicon gate (10) and doped regions (22, 24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed surface of the semiconductor substrate is amorphized, for example by ion bombardment, to inhibit subsequent diffusion of dopant ions during thermal annealing. A low thermal budget is advantageous for the activation and polysilicon regrowth in order to ensure an abrupt doping profile for the source/drain regions. The upper portion (10b) of the gate electrode thus remains amorphous. The upper portion of the gate electrode is removed to allow a low resistance contact to the polysilicon lower portion (10a).
Description
Technical field
The present invention relates to a kind of manufacturing has through the noncrystalline and method of the semiconductor device of the polysilicon electrode of crystallization treatment again.Specifically, but not uniquely, the present invention relates to the method that a kind of manufacturing has the MOS transistor of polygate electrodes.
Background technology
Need constantly reduce device size in field of manufacturing semiconductor devices.Thisly reduce to allow on the wafer of an intended size, to incorporate into more device.Equally, also need to keep the performance of (if can not improve) device.Along with the device size of component is done lessly, some undesirable electronic effect will become more obvious.
The good example that the device of this influence wherein takes place is MOSFET.Here, source electrode that distinguishes by semiconductor channel and drain extensions each doped portion of comprising doped semiconductor wafers.Mix if substrate is the N type, then implant P type dopant, for example boron.Mix if substrate is the p type, then implant N type dopant, for example phosphorus or arsenic.Therefore, provide a p-n junction, it is that the electric current that flows between described source electrode and drain region produces a potential barrier.Therefore be applied to the height of the described potential barrier of voltage control on the insulated gate electrodes that is arranged in above the raceway groove, and control flows is crossed the electric current of described channel region.
Expectation form have shallow but the source electrode that the knot of sudden change distributes with drain extensions so that avoid by the relative caused disadvantageous electronic effect of channel region of weak point.Knot forms in semiconductor wafer or the substrate by dopant is implanted to typically.By using the described channel region of the described grid cover that has formed that dopant is implanted in the end face of described semiconductor wafer.Activate described dopant by heating anneal then.To semi-conductive heating dopant deeper is diffused in the described semiconductor subsequently, can reduces to tie the sudden change of distribution thus.This is a generally acknowledged problem.
U.S. Patent application No.US-2004/0115889 has disclosed a kind of noncrystalline implantation that can carry out in the front and back of implanting dopant species and has handled.Implanting material (for example silicon or germanium) can make the upper area of described semiconductor chip become amorphous.After noncrystalline implantation and n type or p type doping implantation, carry out heating anneal to activate described dopant and to make the crystallization again of described noncrystalline domain.
Fig. 1 a is illustrated in the height constructed profile that is similar to the substrate during the noncrystalline step that discloses in US-2004/0115889.The gate electrode of being made up of polysilicon (polysilicon) 10 insulate with semiconductor chip 12 by gate-dielectric 14 at first.Shown in arrow 100, the exposed surface of described semiconductor chip is by the implanting germanium atom and by noncrystallineization.The energy that is carried by the germanium of described implantation is used to disintegrate the rule crystallization grid near described polysilicon surface, produces a noncrystalline domain thus.Then N type or p type dopant ion are implanted (not shown) in the amorphous regions of described substrate.
Carry out heating anneal with the solid phase epitaxial regrowth that drives described amorphous regions and together with activating described dopant.This noncrystalline and re-growth processes has been illustrated the dopant activation level and the abrupt junction that are used to provide outstanding and has distributed.With reference to Fig. 1 b, the source electrode of described activation and drain extended 22,24 are separated with the justified margin of described grid 10 and by described undoped channel region 26.The described noncrystalline amorphous/crystalline boundary that is used to produce, it forbids the diffusion of dopant ion, helps abrupt junction to form thus.
With carried out the relevant problem of noncrystalline implantation before dopant activates is that at least a portion of described polysilicon gate also becomes amorphous.Make grid the more required heat budget of crystallization be much higher than the required heat budget of bulk semiconductor.When using the low temperature budget, this will cause the part crystallization again of grid.As Fig. 1 b illustrated, the bottom of grid 10a is by successfully regrowth, and top 10b keeps noncrystalline attitude.
Fig. 2 is the curve chart of the result of the test of the resistivity value of the polysilicon gate of expression after the heating anneal (regrowth) of the noncrystalline in advance implantation (PAI) of germanium and 1 minute.' D02 ' figure that is represented by rhombus represents without the resistance of crossing PAI.The curve chart that can find out the PAI of the germanium that is used to have higher-energy shows at the resistance than the very big increase under the low heat budget.
Fig. 3 has represented to experience the PAI of germanium and has schemed at the cross section X-TEM of one minute grid of 680 ℃ of following heating anneals.This is represented by the data point of highlighted being shown as ' X ' in Fig. 2.The top of the described grid of being indicated by described arrow in Fig. 2 remains amorphous.The higher relatively resistance of this grid and the poor device performance that is caused are owing to this noncrystalline part.
Under about heat budget more than 780 ℃, described grid becomes perfect recrystallization, and therefore has lower, more favourable resistance.Yet under these high temperature, described source electrode and drain junction begin deactivation, and this is caused by the increase diffusion of dopant.Therefore, do not exist the grid can be by fully crystallization and described knot can be held sufficiently the process window (process window) of sudden change again.
Summary of the invention
An object of the present invention is to provide a kind of improving one's methods of semiconductor device of making.
Another object of the present invention provides a kind of manufacturing and comprises by the grid of crystallization and be held the method for semiconductor device of the knot of sufficient sudden change more fully.
According to the present invention, a kind of method of making semiconductor device is provided, described method comprises the steps: to form the gate electrode of polysilicon on semiconductor chip, make noncrystallineization of exposed surface of described semiconductor chip and gate electrode, mixed in zone in abutting connection with the semiconductor chip of described gate electrode, then, the top that makes the part of described gate electrode and described semiconductor chip carry out crystallization again and remove described gate electrode.By the top of after described crystallisation step again, removing described gate electrode, be improved for the selection degree of freedom of treatment temperature.Can freely use low heat budget to distribute with the knot of guaranteeing to expect and be held, the crystallization degree again of gate electrode is not critical simultaneously.Any residue amorphous silicon in the described gate electrode is removed easily to guarantee carrying out low resistance contact with it.
Term ' noncrystallineization ' means that the crystal region basically with material converts any processing of noncrystalline domain basically to.Relational language, for example ' noncrystalline ' and ' amorphous ' takes from employing the implication of above-mentioned definition afterwards.
Remove the upper amorphous part of gate electrode can be for example by the uppermost exposed surface of described electrode being polished or etching is carried out.These are handled, and each is all very simple, and need be except the extras the existing device in CMOS or advanced CMOS production line.
The surface, the top of about 20-50nm of described gate electrode is removed, even this will depend on the regrowth degree of silicon gate.As above-mentioned, the noncrystalline part of removing gate electrode subsequently will allow to utilize low temperature.For example, the solid phase epitaxial regrowth in noncrystallineization zone is to carry out by described substrate being heated to 600 ℃ of temperature in-750 ℃ of scopes.The duration of heating will be depended on the temperature of employing.
The high resistance portion of removing gate electrode allows and its generation low resistance contact.This contact can further be strengthened by form the silicide contacts district on described gate electrode.Preferably, it is following realization: promptly precipitating metal level on the described gate electrode, heating described substrate so that form the silicide contacts district on described gate electrode then after removing step described.
In a preferred embodiment, semiconductor device constructed in accordance is incorporated in the integrated circuit (IC) chip.CMOS or the advanced CMOS processing plant that it is good that this can use construction make.
Description of drawings
Only embodiments of the invention are described referring now to accompanying drawing in the mode of example, wherein:
Fig. 1 is illustrated in the grid that runs through MOS transistor in two stages of known fabrication processes and the height constructed profile of channel region;
Fig. 2 for expression with the heat budget that changes by the curve chart of the resistance of noncrystallineization and regrowth, described result obtains from experiment;
Fig. 3 be at 680 ℃ by the X-TEM image of noncrystallineization and one minute grid of regrowth; With
Fig. 4 represents to run through by the grid of MOS transistor made according to the method for the present invention and the constructed profile of channel region.
Be to be appreciated that described accompanying drawing only is a schematic diagram.Identical reference number is used to represent identical or similar part in the whole text.
Embodiment
The invention provides the straightforward procedure that MOS transistor simultaneous adaptation that a kind of manufacturing has the low resistance polysilicon grid forms noncrystalline and low-temp recovery long process shallow, that abrupt junction is required.Fig. 1 and 4 will be used to illustrate an example embodiment of the method according to this invention now.
With reference to figure 1a, a dielectric layer is deposited on the silicon chip 12.For example, described dielectric layer can be made up of silicon dioxide or silicon nitride.On described substrate, deposit the polysilicon layer 10 of a thick about 100nm then.
The precipitation of gate dielectric 14 and polysilicon layer 10 is to use known deposition technique (for example epitaxial growth, chemical vapor deposition (CVD) or ald (ALD)) to carry out.
Use molded described polysilicon layer of standard lithographic printing technology and described dielectric layer so that provide the gate stack with polygate electrodes 10 on described silicon chip 12 then, described polygate electrodes 10 is separated by a gate-dielectric 14 and described silicon chip 12.For example, can utilize photoresist to shield on the substrate and the corresponding a plurality of zones of desired locations that will form the isolated gate lamination.Can use etching step to remove the unnecessary zone of polysilicon layer 10 and dielectric layer 14 then.On substrate, remove described photoresist then to keep isolation gate stack.Be to be appreciated that and in a typical integrated circuit (IC)-components, on single wafer, will form the gate stack of many separation.Yet in order to keep illustrating simplicity of the present invention, only explanation is about the single gate lamination method of (as shown in Figure 1a).
Shown in arrow 100, carry out germanium and implant noncrystallineization of exposed surface that makes described silicon chip and described gate electrode 10 then.Described implantation is with 5e14 to 1e15at/cm
3Dosage carry out with 8 to 30kev energy.Atom bombardment action on highest face temperature is disintegrated described crystalline texture, and the amorphous silicon of finite depth is provided thus.This noncrystallineization is used to limit subsequently, and diffusion of dopant ions provides the shallow source/drain regions of expectation thus to the degree of depth of described silicon wafer 12.
Now, can form in abutting connection with each zone of insulation spacer (not shown) substrate below shielding in p type doping treatment subsequently of described gate electrode.
Refer again to Fig. 1 b, with 0.2-10keV, 5e14 and 5e15at/cm
3Between dosage boron implant ion.This boron is implanted and is used for mixing with the zone 22,24 of the silicon chip of described gate electrode 10 adjacency.Described doped region is the most at last as p type doped conductive source and drain region.In another embodiment, can provide the N type semiconductor device by in the zone of described substrate, implanting N type phosphonium ion on the contrary.
Carry out the solid phase epitaxial regrowth of process annealing then with the noncrystalline part 22,24 (part that comprises gate electrode) that activates described device.Except 10a part and described semiconductor chip 22,24 to described gate electrode carry out the crystallization again, described annealing also is used to activate the boron dope agent of described implantation.
One minute the heat budget of maintenance that (typically is 650 ℃) between 600-750 ℃ is used to carry out this annealing.Imagination is for using higher temperature between a short-term, only otherwise exceeding described temperature just can destroy described abrupt junction and distribute.With reference to figure 1b, provide again crystallization source electrode and drain region 22 and 24 and the two is separated thus by described undoped channel region 26.In addition, heating anneal can make the silicon of grid 10 crystallize to a degree again so that form polysilicon bottom 10a and amorphous silicon top 10b.
According to a preferred embodiment of the present invention, then by its uppermost exposed surface being polished to remove the top 10b of gate electrode.Can utilize chemico-mechanical polishing (CMP).CMP is used for removing top 20-50nm from the surface, the top of described grid 10.Yet, the thickness that imagination is removed part depend on described grid during described solid phase epitaxial regrowth by the degree of crystallization again.Advantageously, described polishing will be removed the whole noncrystalline high resistance area of described grid basically, allow to form low resistance contact thus.Because the character that CMP handles, the degree of polishing has on described wafer+/-change of 20nm.
In a further advantageous embodiment, remove the noncrystalline part of described polysilicon gate by selectable etching.In this case, for example can use based on the acid of HF and carry out Wet-type etching to remove the amorphous silicon part 10b of described gate electrode.Advantageously, have only the high resistance portion of grid to be removed.
In another embodiment, use plasma (dry type) etching to remove the top 10b of described gate electrode.
Fig. 4 represents to remove head portion 10b gate stack afterwards.
Use standard deposition technique deposit thickness on described gate electrode to be the nickel dam (not shown) of 20-40nm then.Heat described substrate then so that the part of described nickel and following polysilicon is transformed into the silicide contacts district.Described silicide advantageously provides the even low resistance contact with described device.For example use Wet-type etching to remove any useless nickel then.Though used nickel in the present embodiment, also can imagine and use other metal be suitable for forming silicide to replace.
The further front-end processing of carrying out substrate then is to provide the contact to described semiconductor device, and it then can be at the inner element of formation that continues of an integrated circuit (IC) chip.Yet, further processing will be described, because it is not directly related with the present invention.
Put it briefly, the method for a kind of manufacturing semiconductor device (for example MOS transistor) is provided.Described device comprises polysilicon gate and the doped region that forms in semiconductor chip, they by a channel region separately.The exposed surface of described semiconductor chip for example by ion bombardment by noncrystallineization, so that during thermal annealing, forbid the diffusion subsequently of dopant ion.Low heat budget is favourable for described activation and polysilicon regrowth, so that guarantee to be used for the sudden change dopant profile of described regions and source.Therefore the top of gate electrode keeps noncrystalline.The top of described gate electrode is removed so that allow and produces low resistance contact with described polysilicon bottom.
By reading the disclosure, other variation and modification will be conspicuous for those skilled in the art.This variation and revise can be included in semi-conductive design, manufacturing and the use known and except feature described herein or the equivalent and the further feature that replace described feature to use.Though claim is expressed as the particular combinations of feature in this application, but should be appreciated that described scope of disclosure also comprises in the literary composition or expresses or hint or summarize any novel characteristics and the combination thereof that draws, no matter and whether it can relax the handled any or whole constructed problem of the present invention.The applicant states at this, in the application or during being derived from the application's the accepting of further application, and can be according to this category feature and/or its combination constitute new claim arbitrarily.
Claims (8)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05105323 | 2005-06-16 | ||
| EP05105323.9 | 2005-06-16 | ||
| PCT/IB2006/051879 WO2006134553A2 (en) | 2005-06-16 | 2006-06-13 | Semiconductor device having a polysilicon electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101288159A CN101288159A (en) | 2008-10-15 |
| CN101288159B true CN101288159B (en) | 2010-10-06 |
Family
ID=37532687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800213073A Active CN101288159B (en) | 2005-06-16 | 2006-06-13 | Semiconductor device having a polysilicon electrode |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7790545B2 (en) |
| EP (1) | EP1894243A2 (en) |
| JP (1) | JP5010589B2 (en) |
| CN (1) | CN101288159B (en) |
| WO (1) | WO2006134553A2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194752B (en) * | 2010-03-11 | 2013-06-12 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing CMOS (complementary metal oxide semiconductor) device structure |
| US8748256B2 (en) * | 2012-02-06 | 2014-06-10 | Texas Instruments Incorporated | Integrated circuit having silicide block resistor |
| US9958424B2 (en) * | 2012-10-01 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of identifying airborne molecular contamination source |
| CN106952918A (en) * | 2016-01-05 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of separate gate flash memory |
| US10522557B2 (en) | 2017-10-30 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Surface topography by forming spacer-like components |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0727815A2 (en) * | 1995-02-14 | 1996-08-21 | Nec Corporation | Method for manufacturing semiconductor device with salicide portions |
| US5966597A (en) * | 1998-01-06 | 1999-10-12 | Altera Corporation | Method of forming low resistance gate electrodes |
| US6335253B1 (en) * | 2000-07-12 | 2002-01-01 | Chartered Semiconductor Manufacturing Ltd. | Method to form MOS transistors with shallow junctions using laser annealing |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03297148A (en) * | 1990-04-16 | 1991-12-27 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPH0458524A (en) * | 1990-06-27 | 1992-02-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH07263684A (en) * | 1994-03-25 | 1995-10-13 | Mitsubishi Electric Corp | Method for manufacturing field effect transistor |
| JPH0923007A (en) * | 1995-07-07 | 1997-01-21 | Sony Corp | Semiconductor device and its manufacture |
| US6297115B1 (en) * | 1998-11-06 | 2001-10-02 | Advanced Micro Devices, Inc. | Cmos processs with low thermal budget |
| JP2000260728A (en) * | 1999-03-08 | 2000-09-22 | Nec Corp | Manufacture of semiconductor device |
| US6424001B1 (en) * | 2001-02-09 | 2002-07-23 | Micron Technology, Inc. | Flash memory with ultra thin vertical body transistors |
| JP2003332565A (en) * | 2002-05-08 | 2003-11-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2003022984A (en) * | 2002-05-31 | 2003-01-24 | Sharp Corp | Method for manufacturing semiconductor device |
| US20040115889A1 (en) * | 2002-12-17 | 2004-06-17 | Amitabh Jain | Ultra shallow junction formation |
| US7247566B2 (en) * | 2003-10-23 | 2007-07-24 | Dupont Air Products Nanomaterials Llc | CMP method for copper, tungsten, titanium, polysilicon, and other substrates using organosulfonic acids as oxidizers |
| EP1650796A3 (en) * | 2004-10-20 | 2010-12-08 | STMicroelectronics (Crolles 2) SAS | Process for a contact plug on a region of an integrated circuit, in particular on the electrodes of a transistor |
-
2006
- 2006-06-13 CN CN2006800213073A patent/CN101288159B/en active Active
- 2006-06-13 US US11/917,103 patent/US7790545B2/en active Active
- 2006-06-13 JP JP2008516483A patent/JP5010589B2/en active Active
- 2006-06-13 WO PCT/IB2006/051879 patent/WO2006134553A2/en active Application Filing
- 2006-06-13 EP EP06756123A patent/EP1894243A2/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0727815A2 (en) * | 1995-02-14 | 1996-08-21 | Nec Corporation | Method for manufacturing semiconductor device with salicide portions |
| US5966597A (en) * | 1998-01-06 | 1999-10-12 | Altera Corporation | Method of forming low resistance gate electrodes |
| US6335253B1 (en) * | 2000-07-12 | 2002-01-01 | Chartered Semiconductor Manufacturing Ltd. | Method to form MOS transistors with shallow junctions using laser annealing |
Non-Patent Citations (1)
| Title |
|---|
| US 6335253 B1,说明书第4栏第30行至第7栏第18行. |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101288159A (en) | 2008-10-15 |
| WO2006134553A3 (en) | 2008-06-19 |
| JP5010589B2 (en) | 2012-08-29 |
| WO2006134553A2 (en) | 2006-12-21 |
| US7790545B2 (en) | 2010-09-07 |
| JP2008544517A (en) | 2008-12-04 |
| EP1894243A2 (en) | 2008-03-05 |
| US20090159992A1 (en) | 2009-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7531436B2 (en) | Highly conductive shallow junction formation | |
| US7355255B2 (en) | Nickel silicide including indium and a method of manufacture therefor | |
| KR100440840B1 (en) | Method of manufacturing semiconductor device and semiconductor device | |
| TWI302729B (en) | Semionductor device having cell transistor with recess channel structure and method of manufacturing the same | |
| CN101288159B (en) | Semiconductor device having a polysilicon electrode | |
| TW200416898A (en) | Semiconductor component and method of manufacture | |
| JP3545526B2 (en) | Method for manufacturing semiconductor device | |
| US7138307B2 (en) | Method to produce highly doped polysilicon thin films | |
| CN105280501A (en) | Stress memorization techniques for transistor devices | |
| US6451644B1 (en) | Method of providing a gate conductor with high dopant activation | |
| CN111105991A (en) | Method for manufacturing semiconductor structure | |
| US7615430B2 (en) | Field effect transistor and method of manufacturing a field effect transistor | |
| US7825025B2 (en) | Method and system for improved nickel silicide | |
| JPS60113472A (en) | Manufacturing method of semiconductor device | |
| CN100401476C (en) | Manufacturing method of semiconductor device | |
| US7348229B2 (en) | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method | |
| KR100238872B1 (en) | Method of manufacturing semiconductor device | |
| US20230127783A1 (en) | Field effect transistor with reduced source/drain resistance | |
| KR100705233B1 (en) | Method of manufacturing semiconductor device | |
| KR20000066155A (en) | Shallow junction &silicide forming method of semiconductor devices | |
| KR100850071B1 (en) | Method for fabricating salicide of semiconductor device | |
| CN119730358A (en) | Method for manufacturing semiconductor device | |
| JP2004281693A (en) | Semiconductor device and manufacturing method thereof | |
| KR20100129624A (en) | Manufacturing method of phase change memory device | |
| KR20030055686A (en) | Method for menufacturing metal silicide layer of semiconducotr device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: IMEC CORP. Free format text: FORMER OWNER: KONINKL PHILIPS ELECTRONICS NV Effective date: 20120326 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20120326 Address after: Leuven Patentee after: IMEC Corp. Address before: Eindhoven Patentee before: NXP B.V. |