CN101281489B

CN101281489B - FIFO memory implementing method and apparatus

Info

Publication number: CN101281489B
Application number: CN200710073942A
Authority: CN
Inventors: 李艳花; 杨焱
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2007-04-03
Filing date: 2007-04-03
Publication date: 2010-05-26
Anticipated expiration: 2027-04-03
Also published as: CN101281489A

Abstract

The invention provides a first in first out memory device, which comprises a memory, a write address controller and a read address controller, the memory is connected to the read address controller and the write address controller respectively, the memory device also includes a comparator and a subtracter, wherein the comparator is connected to the write address controller and the read address controller respectively and to the memory through the substracter; the memory is a memory having at least two ports; the substracter is used for subtracting zero from a pointer difference value of the memory to get a used depth; and the comparator is used for comparing the read point and the write pointer of the memory to get a pointer difference value, and compares the used depth with the memory depth and a predefined full value to get full, to fill and predefined full state signals for feed-backing to the write address controller, besides, the comparator is used for comparing the used depth with zero to get empty and to empty state signals for feed-backing to the read address controller. The invention also provides a realizing method of the device, such that the FIFO control of data cache becomes better and more convenient.

Description

First-in first-out memory implementation method and device

Technical Field

The present invention relates to the field of data communication, and in particular, to a method and apparatus for implementing a data transmission fifo of an integrated circuit.

Background

The data buffer unit is an indispensable hardware unit when implementing a communication system. In an FPGA (Field Programmable Gate Array) and an ASIC (application specific integrated circuit), manufacturers have developed their FIFO (First In First Out) units for users, including synchronous FIFO and asynchronous FIFO modules. In order to ensure that data is correctly written or read without overflow or empty reading, it is necessary to ensure that the FIFO cannot be written when the FIFO is full; and a read operation cannot be performed in an empty state. Therefore, the difficulty in FIFO design is how to judge the empty/full status of the FIFO.

The interface structure of a conventional FIFO cell is shown in fig. 1. Wherein,

FIFO 101: the FIFO unit in the traditional implementation mode is realized by using a register group, has no address bus, can only provide signals of 'empty' and 'full', and part of the FIFO can provide signals of 'will empty' and 'will full';

full signal 102: whether the data space of the FIFO is full, namely, the FIFO is full of data, if so, the signal is pulled high;

full signal 103: whether the data space of the FIFO is about to be full, namely only one data depth is left to be written, if so, the signal is pulled high;

data and control signals 104: other control signals including write signals, write data buses, and the like;

null signal 105: whether the data space of the FIFO is empty or not, namely, the data is read out completely, if so, the signal is pulled high;

the null signal 106: whether the data space of the FIFO is about to be empty, namely only one data depth is left to be read out, if so, the signal is pulled up;

data and control signals 107: including read signals, read data buses, and other control signals.

In this conventional FIFO interface structure, there is one of the biggest drawbacks: the control signal is too simple. Since the data writing and reading positions of the FIFO elements are not visible to the user, i.e. the user does not know how much data depth of the FIFO remains and is used during writing or reading data, unless the situation of full or about to be full, empty or about to be empty has been reached. However, in some data transmission situations, for example, where data needs to be written or read in blocks, it is not sufficient that the FIFO only provides the above signals, and the user may need to know the remaining data space of the FIFO or try to specify a predetermined value for a full signal or an empty signal, and when transmitting block data or group data, it is desirable to make a decision in advance on the empty-full status of the FIFO. In summary, the operation of the user is limited due to the defect of the FIFO unit in controllable function.

Accordingly, the prior art is deficient and needs improvement.

Disclosure of Invention

The invention aims to provide a method and a device for realizing a first-in first-out memory, which generate a signal of a predefined full state and a signal of a predefined empty state by judging a read address and a write address, so that a user can judge the empty and full states of the FIFO in advance.

The technical scheme of the invention is as follows:

a first-in first-out memory device comprises a memory, a write address controller and a read address controller, wherein the memory is respectively connected with the write address controller and the read address controller; the device also comprises a comparator and a subtracter; the comparator is respectively connected with the write address controller and the read address controller and is connected with the memory through the subtracter; the memory is at least a dual port memory; the subtracter is used for reducing the pointer difference value of the memory to zero to obtain the used depth; the comparator is used for comparing the used depth with the memory depth and the predefined full value respectively to obtain full, full and predefined full state signals, and feeding the full, full and predefined full state signals back to the write address controller; the controller is also used for comparing the used depth with 0 to obtain a null state signal and a null state signal, and feeding the null state signal back to the read address controller; the write address controller is also used for feeding back full, full and predefined full signals to the outside; the read address controller is also used for feeding back a null signal to the outside.

The said first-in first-out memory device, wherein, the said subtracter is also used for subtracting the said pointer difference from the memory depth, get the remaining depth; the comparator is also used for comparing the residual depth with a predefined null value to obtain a predefined null state signal and feeding the predefined null state signal back to the read address controller; the read address controller is also used for feeding back a predefined empty state signal to the outside.

The FIFO memory device, wherein the comparator is further configured to compare the remaining depth with 0 to obtain full and near full status signals, and to feed back the full and near full status signals to the write address controller; and the controller is also used for comparing the residual depth with the memory depth to obtain a null state signal and a null state signal, and feeding the null state signal back to the read address controller.

The FIFO memory device, wherein the predefined full value and the predefined empty value are set by a user.

The fifo memory device may further include a comparator connected to the write address controller and the read address controller via a data bus, wherein the data bus defines the predefined full value and the predefined empty value.

The FIFO memory device further comprises a register connected to the comparator for storing the predefined full value and the predefined empty value.

A first-in first-out memory implementation method is applied to a first-in first-out memory device comprising a comparator and a subtracter, and comprises the steps that A1, a read address control unit and a write address control unit respectively send a read pointer address and a write pointer address to the subtracter, and subtraction operation is carried out to obtain a pointer difference value; a2, the subtracter reduces the pointer difference value to zero to obtain the used depth, and sends the used depth to the comparator; a3, the comparator compares the used depth with the memory depth and the predefined full value respectively to obtain full, full and predefined full status signals, and feeds the full, full and predefined full status signals back to the write address controller; a4, comparing the used depth with 0 by the comparator to obtain a null and null state signal, and feeding back the null and null state signal to the read address controller; a5, the read address control unit, or the write address control unit feeds back the respective status signals to the outside.

The fifo memory implementation method further includes, in step a2, the steps of: the subtracter subtracts the pointer difference value from the memory depth to obtain the residual depth, and sends the residual depth to the comparator; step a4 further includes the steps of: and the comparator compares the residual depth with a predefined null value to obtain a predefined null state signal, and feeds the predefined null state signal back to the read address controller.

In step a3, the comparator compares the residual depth with 0 to obtain a full and full status signal, and feeds back the full and full status signals to the write address controller.

In step a4, the comparator compares the residual depth with the memory depth to obtain a null and a null state signal, and feeds the null and the null state signals back to the read address controller.

The fifo memory implementation method further includes, before step a1, the steps of: the user sets the predefined full value.

The fifo memory implementation method further includes, before step a1, the steps of: the user sets the predefined null value.

In the fifo implementation method, in step a6, the read address control unit or the write address control unit feeds back the status signals to the user.

The FIFO memory implementation method, wherein the method further comprises the steps of: a7, user sends write signal and read signal to write address control unit and read address control unit according to each state signal; a8, the write address control unit obtains the write signal and writes the data into the memory; a9, the read address control unit obtains the read signal to read the data from the memory.

By adopting the scheme, the invention generates the signal of the predefined full state and the signal of the predefined empty state by judging the read address and the write address, so that a user can judge the empty and full state of the FIFO in advance, and the preprocessing capability of the system is improved; as more states are added into the FIFO, the control of the data buffer FIFO is more perfect and convenient. When the FPGA or the ASIC is designed, for the condition that FIFO is needed to be used for data caching, a designer can select to stop writing data when the remaining space is less than a certain amount, such as the length of a message or the length of a group of effective data, according to the own needs, so that the data written each time can be ensured to be complete messages; similarly, when data is read out, the complete message can be ensured to be read out every time. The device can form a synchronous FIFO or an asynchronous FIFO, is applied to equipment based on the technical fields of ASIC, FPGA and the like, and is particularly suitable for communication and network equipment.

Drawings

FIG. 1 is a schematic diagram of a FIFO interface of the prior art;

FIG. 2 is a schematic diagram of a FIFO interface of the apparatus of the present invention;

FIG. 3 is a schematic diagram of the internal structure of a FIFO of the apparatus of the present invention;

FIG. 4 is a schematic diagram of one implementation of the FIFO return signal of the method of the present invention;

FIG. 5 is a schematic diagram of a predefined full state implementation of the method of the present invention;

FIG. 6 is a schematic diagram of a predefined empty state implementation of the method of the present invention;

fig. 7 is a flow chart of the method of the present invention.

Detailed Description

The following describes in detail preferred embodiments of the present invention.

As shown in fig. 2, the present invention provides a first-in first-out memory device, which enhances the control function of FIFO, and comprises a memory (RAM), a write address controller, and a read address controller, wherein the memory is respectively connected to the write address controller and the read address controller; it also includes a comparator and a subtractor.

Wherein the comparator is connected with the write address controller and the read address controller respectively, and is connected with the memory through the subtracter. The method comprises the following steps that a double-port RAM is adopted as a data storage unit, and interfaces are arranged between the double-port RAM and a write address control unit, a read address control unit and a subtracter unit of the double-port RAM; the dual-port RAM write address control unit has interfaces with the dual-port RAM and the comparator unit and outputs the state to the comparator; the dual-port RAM read address control unit has interfaces with the dual-port RAM and the comparator unit and outputs the state to the comparator; the subtracter unit is only provided with an interface with the double-port RAM and the comparator unit; the comparator unit generates empty and full states, has interfaces with the subtracter unit, the dual-port RAM write address control unit and the dual-port RAM read address control unit, and sends the states to the dual-port RAM read/write address control unit.

Wherein the memory is at least a dual port memory; in FIFOs, dual port memories are commonly used, where one port is used for writing data and the other port is used for reading data. Write and read operations can be performed simultaneously on memory word cells. Because the invention must produce the signal of predefined full and predefined empty through the judgement to reading address and writing address separately; therefore, it is necessary to use a memory having at least two ports. In order to make the system simple to implement, the device of the invention can use a dual-port RAM as a core of data storage, the storage capacity (depth) of the dual-port RAM is determined according to the situation, and an improved FIFO unit is realized on the basis of the dual-port RAM. The clock of the dual-port RAM is respectively provided by a dual-port RAM writing address control unit and a dual-port RAM reading address control unit, and is controlled by a reading unit and a writing unit. In fact, the apparatus and method of the present invention can also be used in a three-port memory or a multi-port memory, and the present invention is not limited in any way thereto.

The comparator is used for comparing the read pointer and the write pointer of the memory to obtain a pointer difference value.

The subtracter is used for reducing the pointer difference value of the memory to zero to obtain the used depth; the subtractor may be further configured to subtract the pointer difference from the memory depth to obtain a residual depth.

And the comparator is also used for comparing the used depth with the memory depth and a predefined full value respectively to obtain full, full and predefined full state signals, and feeding the full, full and predefined full state signals back to the write address controller. Obtaining a full state signal when the used depth equals a memory depth; when the used depth is only 1 less than the memory depth, namely only one data depth can be written, obtaining a to-full state signal; a predefined full status signal is obtained when the used depth equals a predefined full value.

And the comparator is also used for comparing the used depth with 0 to obtain a null state signal and a null state signal, and feeding the null state signal back to the read address controller. When the used depth is equal to 0, obtaining a null state signal; a null state signal is obtained when the used depth is only 1 more than 0, i.e. only one data depth remains to be read out.

And when the comparator obtains the residual depth transmitted by the subtracter, the comparator can be also used for comparing the residual depth with a predefined null value to obtain a predefined null state signal, and feeding the predefined null state signal back to the read address controller.

At this time, the comparator may be further configured to compare the remaining depth with 0 to obtain a full state signal and a full state signal, and feed back the full state signal to the write address controller; and the controller is also used for comparing the residual depth with the memory depth to obtain a null state signal and a null state signal, and feeding the null state signal back to the read address controller.

The write address controller is used for completing the write operation of the dual-port RAM and feeding back full, full and predefined full signals to the outside, so that a user who uses the outside sees that the full signal is not an address bus, and the FIFO is operated instead of the RAM.

The read address controller is used for completing the read operation of the dual-port RAM and feeding back signals of null, null and predefined null to the outside. The present invention is not limited in this respect.

Wherein said predefined full value and said predefined empty value are set by a user, such that more information can be added to the FIFO structure, enabling feedback of more controllable signals to the user.

The FIFO memory device may be connected to the write address controller and the read address controller via data buses, respectively, for the predefined full value and the predefined empty value, where the data buses define the predefined full value and the predefined empty value; a register may also be provided in connection with the comparator for storing the predefined full value and the predefined empty value.

The fifo memory device, wherein the clock of the write address controller and the clock of the read address controller are clocks of different sources. The clocks provided by the dual-port RAM write address control unit and the dual-port RAM read address control unit may be of the same source or different sources, and for the case of the same source, a synchronous FIFO is formed, and for the case of the different source, an asynchronous FIFO is formed, which is not limited in any way by the present invention.

As shown in fig. 7, the present invention also provides a fifo implementation method applied in a fifo device including a comparator and a subtractor, which includes the steps of,

a1, a read address control unit and a write address control unit respectively send the read pointer address and the write pointer address to the subtracter for subtraction operation to obtain a pointer difference value; wherein the clock of the write address controller and the clock of the read address controller may be the same source clock or different source clocks. When the read pointer and the write pointer are equal, i.e., point to the same memory location, the FIFO may be in both a full or empty state. Whether the FIFO is in a full state or in an empty state, i.e. whether the write pointer catches up to the read pointer from behind or whether the read pointer catches up to the write pointer from behind, can be determined or distinguished in different ways. The specific implementation method belongs to the prior art and is not described herein.

Before the step a1, the method may further include the steps of: the user sets the predefined full value and/or sets the predefined empty value. The setting can be realized by setting a data bus, including setting a predefined full value bus and a predefined empty value bus; this may be achieved by storing the predefined full value and/or the predefined empty value in a register, which is not a limitation of the present invention.

A2, the subtracter reduces the pointer difference value to zero to obtain the used depth, and the used depth is sent to the comparator. At this time, in step a2, the subtractor may further subtract the pointer difference from the RAM depth to obtain a residual depth, and send the residual depth to the comparator.

A3, the comparator compares the used depth with the memory depth and the predefined full value respectively to obtain full, full and predefined full status signals, and feeds the full, full and predefined full status signals back to the write address controller; the method may further include obtaining a not-full status signal and feeding the signal back to the write address controller, which is not limited in the present invention. When the comparator obtains the remaining depth, step a3 may further include the steps of: and the comparator compares the residual depth with 0 to obtain full and full state signals, and feeds the full and full state signals back to the write address controller.

A4, comparing the used depth with 0 by the comparator to obtain a null and null state signal, and feeding back the null and null state signal to the read address controller; obtaining a non-empty status signal and feeding back to the read address controller may also be included, and the present invention is not limited thereto. When the comparator obtains the remaining depth, step a4 may further include the steps of: and the comparator compares the residual depth with a predefined null value to obtain a predefined null state signal, and feeds the predefined null state signal back to the read address controller. And the comparator can also compare the residual depth with the memory depth to obtain empty and empty state signals, and the empty and empty state signals are fed back to the read address controller.

A5, the read address control unit, or the write address control unit feeds back the respective status signals to the outside. Wherein, the read address control unit or the write address control unit can directly or indirectly feed back each status signal to the user. At this time, the fifo implementation method further includes the steps of:

a7, user sends write signal and read signal to write address control unit and read address control unit according to each state signal;

a8, the write address control unit obtains the write signal and writes the data into the memory;

a9, the read address control unit obtains the read signal to read the data from the memory.

An improved FIFO interface structure of the present invention is shown in fig. 2, and is specifically described as follows:

full signal 102: whether the data space of the FIFO is full (all data are written), if so, the signal is pulled high, which is the same as that of the conventional FIFO;

full signal 103: if the data space of the FIFO is about to be full (only one data depth is left to be written in), if so, the signal is pulled high, which is the same as that of the traditional FIFO;

data and control signals 104: other control signals including a write signal, a write data bus, and the like, the same as those of the conventional FIFO;

null signal 105: whether the data space of the FIFO is empty (data is read out completely), if so, the signal is pulled high, which is the same as that of the traditional FIFO;

the null signal 106: if the data space of the FIFO is about to be empty (only one data depth is left to be read out), if so, the signal is pulled high, which is the same as that of the traditional FIFO;

data and control signals 107: other control signals including read signals, read data bus, etc., as with conventional FIFOs;

FIFO 201: namely the FIFO unit implemented by the present invention;

predefined full signal 202: whether the data space of the FIFO is predefined to be full (the residual data depth is less than or equal to a predefined value), if so, the signal is pulled high;

predefined null signal 203: whether the data space of the FIFO is predefined to be empty (the readable data depth is less than or equal to a predefined value), if so, the signal is pulled high;

predefined full value bus 204 (i.e., data bus): predefining a reference value of a full state, and when the FIFO residual depth is less than or equal to the reference value, the predefined full state is determined;

predefined null value bus 205: and predefining a reference value of the empty state, wherein the empty state is predefined when the FIFO readable depth is less than or equal to the reference value.

An internal structure of an FIFO implemented in the present invention is shown in fig. 3, which is specifically described as follows:

FIFO 201: namely the FIFO cell of the implementation of the invention shown in fig. 2;

dual port RAM 301: the carrier for storing data can be only a common dual-port RAM for forming a synchronous or asynchronous FIFO, and the clock of the dual-port RAM301 is respectively provided by a dual-port RAM write address control unit 304 and a dual-port RAM read address control unit 305 and controlled by the two units;

subtractor section 302: performing subtraction operation, namely subtracting zero from the difference value of the current double-port RAM pointer or subtracting the depth of the current double-port RAM pointer from the RAM to obtain the size of the used and residual address spaces, and sending the value to the comparator unit 303;

comparator unit 303: comparing to obtain the current difference value of the double-port RAM pointers; comparing the used depth of the dual-port RAM with the RAM depth and a predefined full value to obtain full, to-full and predefined full states, and returning a result 309 to the dual-port RAM write address control unit 304; comparing the remaining depth of the RAM with 0 and a predefined empty value to obtain empty, to-be-empty, predefined empty states, and returning a result 308 to the dual-port RAM read address control unit 305;

dual-port RAM write address control unit 304: completing the writing operation of the dual-port RAM, writing data into the dual-port RAM every time a writing clock arrives, and feeding back a full signal 102, a full signal 103 and a predefined full signal 202 to the outside, so that a user who uses the outside sees that the full signal is a full signal instead of an address bus, and the FIFO is operated instead of the RAM;

dual-port RAM read address control unit 305: completing the read operation of the dual-port RAM, reading out one data from the dual-port RAM every time a read clock arrives, and feeding back a null signal 105, a null signal 106 and a predefined null signal 203 to the outside;

predefined null value 306: the dual-port RAM read address control unit 305 sends the predefined empty value 306 to the comparator unit 303, and when the data content of the dual-port RAM301 is less than or equal to the predefined empty value 306, the FIFO201 enters a predefined empty state;

predefined full value 307: the dual-port RAM write address control unit 304 sends a predefined full value 307 to the comparator unit 303, and when the free depth of the dual-port RAM301 is less than or equal to the predefined full value 307, the FIFO201 enters a predefined full state;

returning a result 308: whether the current state is empty or not, and whether the current state is empty or not, are empty or predefined;

return result 309: whether it is currently full, will be full, predefined full state.

The method for implementing the FIFO return signal in the invention is shown in FIG. 4, and is specifically explained as follows:

FIFO depth 401: this value is the total depth of the FIFO, i.e. the total depth of the dual port RAM;

FIFO remaining depth and used depth 402: the return value is the remaining depth of the FIFO, namely the remaining storage space of the dual-port RAM, and the used depth of the FIFO, namely the used storage space of the dual-port RAM;

FIFO predefined full and predefined empty state 403: this return value indicates the predefined full and empty status of the FIFO, which status is passed to the dual port RAM write address control unit 304 and the dual port RAM read address control unit 305 and sent out of the FIFO.

A schematic diagram of a predefined full state implementation of the method of the present invention is shown in fig. 5, which specifically illustrates the following:

FIFO used depth 501: this depth represents the depth value in the FIFO to which data has been written;

Ai-Bi state 502: the FIFO has used a state where the depth 501 is equal to the predefined full value 307, at which point the predefined full threshold has been reached;

ai > Bi State 503: the FIFO has used a state where the depth 501 is equal to a predefined full value 307, when a predefined full threshold has been crossed;

predefined full state 504: the FIFO has entered a predefined full state.

A schematic diagram of a predefined empty state implementation of the method of the present invention is shown in fig. 6, which specifically illustrates the following:

di is FIFO free depth 601: this depth represents the depth value of the FIFO to which no data is written, i.e. the depth still remaining;

di ═ Ci state 602: a state where the FIFO empty depth 601 equals the predefined empty value 306, at which point the predefined empty threshold has been reached;

di < Ci state 603: a state where the FIFO empty depth 601 equals the predefined empty value 306, at which point the predefined empty threshold has been crossed;

predefined empty state 604: the FIFO has entered a predefined full state.

The invention may also provide similar efficacy with the following modifications: when writing FIFO and reading FIFO, the predefined full/empty value is set according to the specific algorithm of user, so the FIFO can be used as special service quality and queue management field to realize the control function on data buffer.

The depth of the dual-port RAM and the value of the predefined full/empty FIFO can be flexibly changed to realize different requirements, for example, when the dual-port RAM is used as a buffer, the depth of the dual-port RAM can be properly increased, the value of the predefined full/empty FIFO can be increased, and the value of the predefined empty FIFO can be reduced; when used as a quality of service implementation, the dual port RAM depth can be reduced appropriately, the predefined full value reduced, and the predefined empty value increased.

The invention may also be used in the following products or methods: as the realization of FPGA, the method can become the early verification of ASIC, and as the embedded synchronous and asynchronous FIFO module, the method can be applied to the communication products of chips. The FPGA may be a Flash FPGA or an SRAM FPGA, and the present invention is not limited thereto.

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

Claims

1. A first-in first-out memory device comprises a memory, a write address controller and a read address controller, wherein the memory is respectively connected with the write address controller and the read address controller; the circuit is characterized by also comprising a comparator and a subtracter; wherein,

the comparator is respectively connected with the write address controller and the read address controller and is connected with the memory through the subtracter;

the memory is at least a dual port memory;

the subtracter is used for subtracting zero from a pointer difference value obtained by comparing a read pointer and a write pointer of the memory through the comparator to obtain the used depth;

the comparator is used for comparing the used depth with the memory depth and the predefined full value respectively to obtain full, full and predefined full state signals, and feeding the full, full and predefined full state signals back to the write address controller; the controller is also used for comparing the used depth with 0 to obtain a null state signal and a null state signal, and feeding the null state signal back to the read address controller;

the write address controller is also used for feeding back full, full and predefined full signals to the outside;

the read address controller is also used for feeding back a null signal to the outside.

2. The fifo memory device of claim 1, wherein the subtractor is further configured to subtract the pointer difference from a memory depth to obtain a residual depth; and,

the comparator is also used for comparing the residual depth with a predefined null value to obtain a predefined null state signal and feeding the predefined null state signal back to the read address controller;

the read address controller is also used for feeding back a predefined empty state signal to the outside.

3. The fifo device of claim 2, wherein the comparator is further configured to compare the remaining depth with 0 to obtain a full and a full status signal, and to feed back the full and full status signals to the write address controller; and the controller is also used for comparing the residual depth with the memory depth to obtain a null state signal and a null state signal, and feeding the null state signal back to the read address controller.

4. The fifo memory device of claim 2, wherein the predefined full value and the predefined empty value are user-set.

5. The FIFO memory device of claim 4, wherein the comparator is connected to the write address controller and the read address controller via a data bus, the data bus defining the predefined full value and the predefined empty value.

6. The FIFO memory device of claim 4, further comprising a register coupled to the comparator for storing the predefined full value and the predefined empty value.

7. A first-in first-out memory implementation method is applied in a first-in first-out memory device comprising a comparator and a subtracter, and comprises the steps of,

a1, a read address control unit and a write address control unit respectively send the read pointer address and the write pointer address to the subtracter for subtraction operation to obtain a pointer difference value;

a2, the subtracter reduces the pointer difference value to zero to obtain the used depth, and sends the used depth to the comparator;

a3, the comparator compares the used depth with the memory depth and the predefined full value respectively to obtain full, full and predefined full status signals, and feeds the full, full and predefined full status signals back to the write address controller;

a4, comparing the used depth with 0 by the comparator to obtain a null and null state signal, and feeding back the null and null state signal to the read address controller;

a5, the read address control unit, or the write address control unit feeds back the respective status signals to the outside.

8. The FIFO memory implementation method of claim 7, wherein step A2 further comprises the steps of: the subtracter subtracts the pointer difference value from the memory depth to obtain the residual depth, and sends the residual depth to the comparator; and,

step a4 further includes the steps of: and the comparator compares the residual depth with a predefined null value to obtain a predefined null state signal, and feeds the predefined null state signal back to the read address controller.

9. The FIFO memory implementation method of claim 8, wherein in step A3, the comparator compares the residual depth with 0 to get a full, ready status signal, and feeds back to the write address controller.

10. The FIFO memory implementation method of claim 8, wherein in step A4, the comparator compares the residual depth with the memory depth to get a null, a null state signal, and feeds back to the read address controller.

11. The fifo memory implementation method according to any one of claims 7 to 10, further comprising, before step a1, the steps of: the user sets the predefined full value.

12. The fifo memory implementation method according to any one of claims 7 to 10, further comprising, before step a1, the steps of: the user sets the predefined null value.

13. The fifo implementation method of any one of claims 7 to 10, wherein in step a5, the read address control unit or the write address control unit feeds back the status signals to a user.

14. The fifo implementation method of claim 13, further comprising the steps of: