CN101290866A - groove etching method - Google Patents

Abstract

Provided herein are methods for recess etching that facilitate improved lateral to vertical etch ratio requirements, thereby enabling deeper recess etching while maintaining relatively shallow vertical etch depths. This enhanced lateral etch approach is advantageous for a variety of applications where the ratio of lateral to vertical etch depth is limited or where the formation of grooves or cavities is required. In some embodiments, a method of recess etching includes providing a substrate having a structure formed thereon; forming a recess in the substrate at least partially underlying the structure using a first etching process; forming a selector on the substrate. a permanent passivation layer; and extending grooves in the substrate using a second etch process. The selective passivation layer is generally formed on areas of the substrate adjacent to the structure but generally not within the recesses. The first and second etching processes may be the same or different processes.

Description

groove etching method

technical field

Embodiments of the present invention generally relate to the fabrication of devices on semiconductor substrates, and more particularly to recess etching methods for use during the fabrication of such devices.

Background technique

A large scale integration (ULSI) circuit may include more than a million electronic devices (eg, transistors) formed on a semiconductor wafer, such as a silicon (Si) wafer, and cooperate to perform different functions in the device. Typically, the transistors used in ULSI circuits are complementary metal oxide semiconductor (CMOS) field effect transistors. CMOS transistors typically have a source region, a drain region, and a channel region between the source and drain. To control conduction between the source and drain, a gate structure including a polysilicon gate electrode is formed over the channel region and separated from the channel region by a gate insulator.

The performance of such devices can be improved by, for example, strain engineering. For example, stress can be applied to the atomic lattice of the deposited material in order to improve the electrical properties of the material itself or an underlying or overlying material deformed by the stress exerted by the stressed deposited material which may increase the carrier mobility of a semiconductor such as silicon . This increased mobility thereby increases the saturation current of doped silicon semiconductors in order thereby to improve their performance. In the CMOS example, local lattice strain can be introduced into the channel region of a transistor by depositing transistor constituent materials with internal compressive or tensile stress.

In some embodiments, this is accomplished by partially etching away the silicon substrate beneath the gate structure and depositing a silicon-germanium layer thereon in order to introduce strain in the device. Typically, the silicon substrate below the gate structure is etched laterally to a point adjacent to the channel region of the substrate in order to enhance the Si-Ge strain effect. However, as technology nodes continue to shrink, such as from the 65nm node to the 45nm node, and even to the 32nm node, there are tighter constraints on the etch processes used to form these structures. For example, a shallower junction depth limits the possible vertical etch distance of a silicon substrate. Also, the ratio of vertical to lateral etch distances decreases, thereby unnecessarily limiting conventional etch processes used to fabricate these structures, which may require greater vertical to lateral etch ratios. Furthermore, the microloading effect caused by the tighter pitch of the structures formed on the substrate further exacerbates the problems caused by the increased vertical etch and lateral etch requirements of the etch process.

Therefore, there is a need for an improved etching process for recess etching.

Contents of the invention

Provided herein are methods for recess etching that facilitate improved lateral to vertical etch ratio requirements, thus enabling deeper recess etch while maintaining relatively shallow vertical etch depths. This enhanced lateral etch approach is advantageous for a variety of applications where the ratio of lateral to vertical etch depth is limited or where the formation of grooves or cavities is desired. In some embodiments, the recess etching method includes providing a substrate having a structure formed thereon; forming a recess in the substrate at least partially below the structure using a first etching process; a permanent passivation layer; and extending grooves in the substrate using a second etch process. The selective passivation layer is generally formed on regions of the substrate adjacent to the structure but generally not in the recesses. The first and second etching processes may be the same or different processes.

In certain embodiments, a recess etching method includes providing a substrate having a shaped mask formed thereon; etching a feature into the substrate through the shaped mask using a first etch process; forming a protective layer over the protective layer; removing the bottom of the protective layer to expose the substrate; and etching a cavity into the substrate using a second etching process.

Description of drawings

So that the manner in which the features of the invention may be understood in detail, a more specific description of the invention outlined above has been given by reference to embodiments which are partially shown in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, since the invention may have other equally effective embodiments.

1A-1E schematically depict the stages of gate electrode preparation according to some embodiments of the present invention.

Figure 2 depicts a method of recess etching according to certain embodiments of the present invention as shown in Figures 1A-E.

3A-3E schematically describe the stages of gate electrode preparation according to some embodiments of the present invention.

Figure 4 depicts a method of recess etching according to certain embodiments of the present invention as shown in Figures 3A-D.

Figure 5 depicts a schematic diagram of an exemplary plasma processing apparatus of the type used to perform a portion of the method of the present invention.

To facilitate understanding, identical reference numerals have been used wherever possible to refer to identical elements that are common to the drawings. The figures are simplified and not drawn to scale for ease of understanding.

Detailed ways

ADVANTEDGETM反应器，或

或

蚀刻反应器，这些均由加利佛尼亚圣克拉拉的应用材料公司提供。

ADVANTEDGETM、

或

反应器还可以用作同样由应用材料公司提供的

集成半导体基片加工系统的加工模块。下面参考图5描述适当蚀刻反应器的示范实施例。1A-E depict stages in the fabrication of exemplary gate structures according to some embodiments of the present invention. Figure 2 depicts an exemplary method for recess etching according to some embodiments of the present invention, and is described below with reference to Figures 1A-E. Suitable reactors suitable for use with the techniques disclosed herein include, for example, discrete plasma sources

ADVANTEDGETM reactor, or

or

etch reactors, these were supplied by Applied Materials, Santa Clara, CA.

ADVANTEDGE™,

or

The reactor can also be used as a

The processing module of the integrated semiconductor substrate processing system. An exemplary embodiment of a suitable etch reactor is described below with reference to FIG. 5 .

The method 200 begins at 202, where in an exemplary embodiment of the invention, a substrate 102 (as shown in FIG. 1A ) having an exemplary gate structure 100 formed thereon may be provided. Substrate 102 may be a silicon substrate, although other types of substrates may also be suitable. The exemplary gate structure 100 may include a gate insulator 104 having a gate electrode 106 formed thereon and a hard mask 108 formed atop the gate electrode 106 . A liner 110 and a spacer structure 112 are typically placed on each side of the gate structure 100 . There may also be a capping layer 114 on the gate structure 100 .

The material forming exemplary gate structure 100 may be any material suitable for use in a gate structure. For example, gate insulator 104 may be made of hafnium dioxide (HfO2), silicon dioxide (SiO2), or a similar material. The gate electrode 106 may comprise polysilicon or other conductive material, such as a metal or metal-containing material. Hardmask 108 may include high temperature oxide (HTO), tetraethoxysilane (TEOS) oxide, silicon oxynitride (SiON), silicon nitride (SiN), or similar materials. Liner 110 may comprise thermal oxide (HTO) or similar material. Spacer structure 112 may include silicon nitride. Capping layer 114 may include silicon oxide. It is contemplated that other materials may be suitable for use based on the teaching provided here.

Next, at 204, to form the recess 116 in the substrate below the gate structure 100 (as shown in FIG. 1B), a first etching process is used. The first etch process is an isotropic etch process with a vertical etch composition as shown by etching the substrate 102 to a vertical depth V, and laterally etching the substrate 102 below the gate structure 100 to a lateral depth L1. An alternative description of the groove 116 may include measuring the vertical distance between the inner edge of the groove 116 and the adjacent edge of the gate electrode 106 , as shown by distance D1 in FIG. 1B .

The first etch process may be any suitable isotropic etch process. In an illustrative example for etching a silicon substrate, it is possible to provide a process gas comprising nitrogen trifluoride (NF3), optionally in combination with at least chlorine (Cl2), oxygen (O2) and a gas such as argon (Ar) One of the inert gases. It is possible to form a plasma from the process gas using a source power between about 200-1000 Watts at a frequency of about 13.56 MHz. To facilitate etching in all directions (isotropically) on the substrate 102, low bias power, or alternatively no bias power is provided.

In some embodiments, the first etch process may be performed until the desired vertical etch depth V is reached. Alternatively, it is possible to perform the first etching process until the groove 116 obtains the desired lateral etching depth L1. It is possible to time the first etch process so that it is performed within a desired period of time.

Next, at 206, passivation may be selectively formed in regions of the substrate 102 (as shown in FIGS. 1C and 1D ) that are adjacent to the gate structure 100 but not underneath the gate structure 100 (ie, not within the recess 116). layer 120 (an oxide layer in one embodiment). Passivation layer 120 may be selectively formed on substrate 102, possibly by selectively exposing substrate 102 to a plasma of a passivation gas, such as an oxygen-containing gas in the example of an oxide layer. In some embodiments, passivating gases may include oxygen-based gases such as oxygen (O2) or radon-oxygen (He-O2); carbon-based gases such as difluoromethane (CH2F2) or other polymeric form gases ; boron trichloride; or similar gases. It is also possible to use auxiliary process gases such as one or more inert gases such as argon. In order to selectively form the passivation layer 120, it is possible to form an anisotropic plasma (shown by arrow 118 in FIG. 1C) by using source power as described above in combination with bias power. Alternatively, it is possible to form a plasma using only bias power. In some embodiments, the bias power may be between about 100-700 watts or about 200 watts for a signal at about 13.56 MHz. The anisotropic plasma facilitates the selective formation of passivation layer 120 on exposed regions of substrate 102 but not within protected regions of substrate 120 such as recesses 116 . In order to form the passivation layer 120 of a suitable thickness (such as a few nanometers, or between about 1-10 nm, or about 3 nm), the plasma may be formed for a sufficiently long period of time. In some embodiments, the plasma is formed in a few seconds, or about 7 seconds, or for a long time long enough to form a proper plasma.

Next, at 208 , the recess 116 may be extended to a desired lateral depth L2 (as shown in FIG. 1E ) under the gate structure 100 , possibly using a second etch process. This final lateral depth L2 generally depends on the specific structure to be formed or the requirements of a specific application. Alternatively, the elongated groove 116 may be described as having a vertical distance D2 from the inner edge to the gate electrode 106 (as shown in FIG. 1E ). In one non-limiting example, in a 45nm technology node gate structure - which has a width of, for example, about 320 Angstroms or less according to the International Technology Roadmap for Semiconductors (ITRS), the final distance D2 may be at least about 150 Angstroms, depending on final demand.

The second etching process may be the same as the first etching process described above. Advantageously, the passivation layer 120 protects the substrate 102 from additional unintended vertical etching, thereby substantially maintaining the vertical depth V to which the substrate has been etched during 204 . Thus, the inner edge of the extended groove 116 is advantageously close to the channel region of the substrate 102 disposed below the gate insulator 104 and the gate electrode 106, thereby enabling control based on strain atop the substrate 102 and within the groove 106. The formation of a layer (eg, a Si-Ge layer or a Si-C layer) enables enhancement of the silicon-germanium (Si-Ge) strain effect for PMOS (or silicon-carbide (Si-C) for NMOS). In addition, the formation of a passivation layer facilitates the formation of a passivation layer on top of the gate structure 100, which allows independent control of cap oxide turn-on, hard mask (HM) and spacer depletion, thereby facilitating widening the use of Controlling the process window of the hardmask 108, spacer layer 112, and feature-dependent microloading.

In an example of a one-step selective passivation/lateral etch process, upon completion of 208, the method may end. Alternatively, one or more of 204-208 may be repeated as required in a multi-step process in order to achieve greater lateral groove depths and desired feature profiles. In some embodiments, it is possible to control 208 (second recess step) to provide lower selectivity to the passivation layer for increased lateral etching (increased recess depth) and for removal of the passivation layer. Alternatively or in combination, in some embodiments, a passivation layer removal step may be added in order to control the thickness of the passivation layer during the multi-step process.

Upon completion of the recess etch process, any residual passivation layer may be removed, such as by a wet clean process or any suitable process for the type of residual passivation layer and including the substrate and gate structures or other features formed thereon . The substrate with the features formed thereon may now proceed to other processes in order to complete the fabrication of the device, such as in the gate structure example, epitaxial growth of the strain control layer on top of the substrate and within the recesses and similar locations.

Although the above discussion relates to the fabrication of one exemplary type of gate structure, it is also possible to form other types of gate structures including different combinations of materials using the inventive methods disclosed herein. Additionally, the fabrication of other devices and structures used in integrated circuits that may use recess etching during the fabrication sequence may also benefit from the present invention. For example, in one non-limiting or exemplary example, the inventive recess etch method may be used to direct the flash stack to grain selectivity between the WSix and polysilicon layers.

ADVANTEDGETM反应器，或

或

蚀刻反应器。下面参考图5描述适当蚀刻反应器的示范实施例。In certain embodiments, and as shown in Figures 3A-E and Figure 4, it may be advantageous to fabricate spherical recessed channel array transistors (S-RCAT). Figures 3A-E depict stages in the preparation of exemplary S-RCAT structures according to certain embodiments of the invention. Figure 4 depicts one exemplary method for recess etching according to some embodiments of the present invention, and is described below with reference to Figures 3A-E. Suitable reactors that may be suitable for use with the teachings disclosed herein include, for example, discrete plasma sources

ADVANTEDGETM reactor, or

or

etch reactor. An exemplary embodiment of a suitable etch reactor is described below with reference to FIG. 5 .

Method 400 begins at 402, where in an exemplary embodiment of the invention, a substrate 302 may be provided having a shaped mask layer 306 formed thereon. Substrate 302 may be a silicon substrate, although other types of substrates may also be suitable for use. Shaped masking layer 306 generally has at least one feature 308 defined therein, and may be any suitable masking layer for shaping substrate 302 as described herein, such as a photoresist layer (e.g., positive or negative). photoresist) or a hard mask (such as silicon nitride (Si3N4), silicon oxide (SiO2) or similar). In some embodiments, one or more intervening layers 304 may be provided between the shaped mask layer 306 and the substrate 302 . For example, in some embodiments, the intervening layer 304 may include a pad oxide layer, or a silicon oxide (SiO2) layer. Although described with reference to certain embodiments having certain layers as shown in FIGS. 3A-D , it is contemplated that other layers may also be present on substrate 302 when S-RCAT or other structures are fabricated according to the techniques disclosed herein.

Next, at 404, features 308 are etched into substrate 302 using a first etch process, as shown in FIG. 3B. The first etch process may be any suitable etch process that primarily etches feature 308 vertically into substrate 302 to a desired depth. In one exemplary example for etching a silicon substrate, at least one halogen-containing gas may be provided, such as nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), hydrogen bromide (HBr) or the like. For example, in certain embodiments, it may be possible to provide NF3 up to about 100 seem, SF6 up to about 50 seem, and/or HBr up to about 400 seem. In some embodiments, it is also possible to provide at least one of chlorine (Cl2), oxygen (O2) or nitrogen (N2). For example, in certain embodiments, Cl2 up to about 400 seem, O2 up to about 30 seem, and/or N2 up to about 50 seem may be provided.

It is possible to form a plasma from the process gas using a source power of between about 200-1200 watts at a suitable frequency, such as about 13.56 MHz. It is also possible to provide a bias power of between about 150-300 Watts at a suitable frequency, such as about 2 MHz. In certain embodiments, it is possible to maintain the pressure within the processing chamber between about 4-70 mTorr. It is possible to perform the first etch process until a desired vertical etch depth is reached, for example by monitoring the etch process or by performing the etch process at predetermined intervals.

Next, at 406 , protective layer 310 may be formed within feature 308 (as shown in FIG. 3C ). In some embodiments, protective layer 310 may be formed in an ion-enhanced oxidation process, such as by exposing substrate 102 to an oxygen-containing gas such as oxygen (O 2 ) and one or more gases such as argon (Ar). A plasma of an inert gas is formed to form an oxide layer within the features 308 and on the substrate 302 . The ion-enhanced oxidation process facilitates deep penetration into the sidewalls of the features 308 to form a protective layer 310 that can withstand subsequent processes.

In certain embodiments, it is possible to provide between about 100-500 seem of O2 and between about 100-300 seem of Ar into the processing chamber. It is possible to maintain the pressure of the process chamber between about 4-20 mTorr. It is possible to form a plasma from the process gas using a source power of between about 500-1500 Watts at a suitable frequency, such as about 13.56 MHz. It is also possible to provide a bias power of between about 150-300 Watts at a suitable frequency, such as about 2 MHz. It is possible to maintain the plasma until the spacer structure 310 reaches a desired thickness, for example by monitoring the etching process or by performing the etching process at predetermined intervals.

A protective layer 310 is typically formed along the bottom 312 of the feature 308 (as shown in FIG. 4C ), in addition to the sidewalls. Likewise, at 408, the bottom 312 of the protective layer 310 may be removed or opened to expose the surface 314 of the substrate 302 (as shown in FIG. 4D). Bottom 312 of protective layer 310 may be unlocked by any suitable process for etching the material forming protective layer 310 in such a way that bottom 312 may be removed prior to removing all material disposed on the sidewalls of feature 308 . For example, in some embodiments where protective layer 310 includes oxygen, it is possible to form a plasma from a fluorine-containing gas such as carbon tetrafluoride (CF4). It is also possible to provide an inert gas such as argon (Ar). In certain embodiments, it is possible to provide CF4 between about 100-200 seem and Ar between about 100-200 seem.

It is possible to maintain the pressure of the process chamber between about 4-20 mTorr. It is possible to form a plasma from the process gas using a source power of between about 200-1000 watts at a suitable frequency, such as about 13.56 MHz. It is also possible to provide a bias power of between about 150-300 Watts at a suitable frequency, such as about 2 MHz. It is possible to maintain the plasma until the bottom 312 of the protective layer 310 is completely or mostly removed, for example by monitoring the etching process or by performing the etching process for a predetermined period of time. The ion-enhanced oxidation process used at 406 to form protective layer 310 may be beneficial in providing a strong deep oxide layer on the sidewalls of features 308 that can withstand the etch process used to remove bottom 312 of protective layer 310 .

Next, at 410 , grooves or cavities 316 may be formed in substrate 302 . Cavity 316 may be formed by a second etch process. The second etch process may be any suitable isotropic etch process that etches cavity 316 to the desired dimensions in substrate 302 . In an illustrative example for etching a silicon substrate, at least one fluorine-containing process gas such as nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or the like may be provided. In some embodiments, it is also possible to provide at least one of chlorine (Cl2), oxygen (O2), nitrogen (N2), argon (Ar) or helium (He). For example, in certain embodiments, Cl2 up to about 200 seem, O2 up to about 50 seem, N2 up to about 50 seem, Ar up to about 50 seem, and/or He up to about 4000 seem may be provided.

It is possible to form a plasma from the process gas using a source power of between about 200-1000 watts at a suitable frequency, such as about 13.56 MHz. It is also possible to provide a bias power of between about 150-300 Watts at a suitable frequency, such as about 2 MHz. In certain embodiments, it is possible to maintain the pressure of the processing chamber between about 4-50 mTorr. The second etch process may be performed until the desired size of the cavity 316 is reached, for example by monitoring the etch process or by performing the etch process at predetermined intervals.

It is possible to repeat the formation of protective layer 310 and the etching of cavity 316 in substrate 302 until cavity 316 of the desired size is formed, although to the detriment of widening feature 308 . Upon completion of the recess etch process, any residual oxide layer (e.g., protective layer 310) may be removed, such as by a wet clean process or for residual layer types and other materials including the substrate and other features formed thereon. any suitable process. The substrate with the features formed thereon may now proceed with other processes in order to complete the fabrication of the device, such as in the S-RCAT example, filling the recesses and fabricating the desired gate structure atop the substrate.

Thus, according to an embodiment of the invention as described above with reference to FIGS. 3A-E and FIG. 4 , there is provided a method for etching a substrate which may include providing a substrate having a shaped mask layer formed thereon; using A first etch process etches the feature into the substrate through the shaped mask; forms a protective layer on the sidewalls of the feature; removes the bottom of the protective layer so that the substrate is exposed; and etches the cavity into the substrate using a second etch process middle.

In some embodiments of the foregoing examples, the shape masking layer is at least one of a photoresist or a hard mask. In some embodiments, the first etch process may include providing at least one halogen-containing gas; and forming a plasma from the process gas using a source power of between about 200-1200 watts. In some embodiments, forming the protective layer may include exposing the substrate to a plasma formed from an oxygen-containing gas and one or more inert gases to form an oxide layer within the features.

In some embodiments, forming the protective layer may further include providing O2 between about 100-500 sccm and Ar between about 100-300 sccm; Plasma is formed. In some embodiments, removing the bottom of the protective layer may include providing CF4 between about 100-200 sccm and Ar between about 100-200 sccm; using a source power between about 200-1000 watts from the process gas A plasma is formed; and the plasma is maintained until substantially the bottom of the protective layer is removed without removing the protective layer from the sidewalls of the feature.

In some embodiments, etching the cavity into the substrate may include forming an isotropic plasma of a desired dimension to etch the cavity into the substrate. In some embodiments, etching the cavity into the substrate may further include providing at least one halogen-containing process gas; and forming a plasma from the process gas using a source power of between about 200-1500 watts. In some embodiments, the processing gas of the second etching process may include at least one of chlorine (Cl2), oxygen (O2), nitrogen (N2), argon (Ar) or helium (He). In certain embodiments, it is possible to provide up to about 50 seem of NF3, and/or up to about 50 seem of SF6. In certain embodiments, Cl2 up to about 200 seem, O2 up to about 50 seem, N2 up to about 50 seem, Ar up to about 300 seem, and/or He up to about 400 seem may be provided.

FIG. 5 depicts a schematic diagram of a schematic etch reactor 500 that may be used to practice portions of the present invention. Reactor 500 includes a process chamber 510 with a substrate support pedestal 516 in an electrical conductor (wall) 530 and a controller 540 .

Chamber 510 is equipped with a substantially flat insulator ceiling 520 . Other embodiments of chamber 510 may have other types of ceilings, such as domed ceilings. An antenna comprising at least one induction coil element 512 is arranged on top plate 520 (two coaxial elements 512 are shown). The induction coil element 512 is connected to a plasma power source 518 through a first matching network 519 . The plasma source 518 is typically capable of generating up to 3000W of power at an adjustable frequency ranging from 50kHz to 13.56MHz.

The support pedestal (cathode) 516 is connected to a bias power source 522 through a second matching network 524 . Bias source 522 is typically capable of generating up to 500W at approximately 13.56MHz. Bias power may be continuous or pulsed. In other embodiments, bias power source 522 may be a DC or pulsed DC source.

Controller 540 includes a central processing unit (CPU) 544, memory 542, and support circuitry 546 for CPU 544, and facilitates control of components of chamber 510 and the etching process, as described in detail above.

During operation, semiconductor substrate 514 is placed on pedestal 516 and process gases are applied from gas panel 538 through access hatch 526 and gas mixture 550 is formed. Gas mixture 550 is ignited into plasma 555 in chamber 510 by applying power from plasma source 518 and bias power source 522 to induction coil element 512 and cathode 516, respectively. The pressure inside chamber 510 is controlled using throttle valve 527 and vacuum pump 536 . Typically, chamber wall 530 is connected to electrical ground 534 . The temperature of wall 530 is controlled using a liquid-containing conduit running through wall 530 .

The temperature of the substrate 514 is controlled by stabilizing the temperature of the support base frame 516 . In one embodiment, helium gas is provided from gas source 548 via gas conduit 549 into channels (not shown) formed in the surface of the pedestal beneath the substrate. Helium may be used to facilitate heat transfer between the pedestal 516 and the substrate 514 . During processing, the pedestal 516 is heated to a steady state temperature, possibly by resistive heaters (not shown) within the pedestal, and the helium gas then facilitates uniform heating of the substrate 514 . Using this thermal control, the temperature of substrate 514 is maintained between approximately 20 and 80 degrees Celsius.

Those skilled in the art will appreciate that other etch chambers may be suitable for practicing the invention, including chambers with remote plasma sources, electron cyclotron resonance (ECR) plasma chambers, and the like.

To facilitate control of processing chamber 510 as described above, controller 540 may be any form of a general purpose computer processor that can be used in an industrial setting to control the various chambers and sub-processors. The memory 542 or computer readable medium of the CPU 544 may be one or more readily available memories, such as random access memory (RAM), read only memory (ROM), floppy disks, hard disks, or any other form of digital storage, local or remote. To support the processor in a conventional manner, support circuitry 546 is connected to CPU 544. These circuits include cache memory, power supplies, clock circuits, input/output circuits and subsystems and the like. The inventive method is typically stored in memory 542 as a software program which, when executed, may control etch reactor 500 in order to perform the inventive method. It is also possible for a second CPU (not shown) to store and/or execute software programs remotely from the hardware controlled by CPU 544.

The invention may be practiced using other semiconductor substrate processing systems in which processing parameters may be adjusted by those skilled in the art in order to achieve the desired characteristics without departing from the spirit of the invention by using the teachings disclosed herein.

Accordingly, methods for recess etching have been provided that facilitate improved lateral to vertical etch ratio capability, thereby enabling deeper lateral recess etching while maintaining relatively shallow vertical etch depths. This enhanced lateral etch approach advantageously provides benefits for a variety of applications that limit the ratio of vertical to lateral etch depth (eg, applications that require greater lateral etch and/or less vertical etch).

Although the foregoing description is directed to an embodiment of the invention, other and additional embodiments of the invention may be devised without departing from the essential scope of the invention, which is defined by the claims.

Claims (15)

1. method that is used for etch substrate comprises:

Substrate with the structure that forms thereon is provided;

Use the substrate of first etch process below being arranged in structure at least in part to form groove;

On substrate, form the selectivity passivation layer;

Use second etch process extending flute in substrate.

2. the method for claim 1 is characterized in that the contiguous structure in substrate but substantially forms the selectivity passivation layer on the zone in groove.

3. the method for claim 1 is characterized in that first etch process comprises:

Provide and comprise Nitrogen trifluoride (NF ₃) and, alternatively, chlorine (Cl ₂), oxygen (O ₂) or inert gas at least a processing gas.

4. the method for claim 1 is characterized in that the selectivity passivation layer comprises by substrate is exposed to and comprises oxygen (O at least ₂) or helium-oxygen (He-O ₂) the plasma of oxygen-containing gas form oxide skin(coating).

5. the method for claim 1 is characterized in that forming the selectivity passivation layer and comprises:

Substrate is exposed to comprises that at least carbon based gas, polymer form gas or boron chloride (BCl ₃) in a kind of plasma of passivation gas.

6. method as claimed in claim 5 is characterized in that passivation gas comprises difluoromethane (CH ₂F ₂).

7. the method for claim 1 is characterized in that forming the selectivity passivation layer and comprises:

Substrate is exposed to plasma;

Substrate bias power is applied to the substrate support pedestal of supporting substrate.

8. the method for claim 1 is characterized in that grid structure has about 320 dusts or littler width, and wherein groove is extended in substrate and comprise:

With the degree of depth of groove etching to about at least 150 dusts.

9. the method for claim 1 also comprises:

Form the selectivity passivation layer and use second etch process that groove is extended in substrate repeating on the substrate, up to reaching the expection depth of groove.

10. the method for claim 1 also comprises:

On the substrate top and in the groove, form the strain key-course.

11. method as claimed in claim 10 is characterized in that the strain key-course comprises silicon and germanium layer or silicon and carbon-coating.

12. a method that is used for etch substrate comprises:

Substrate with the setting mask layer that forms thereon is provided;

Use first etch process feature to be etched in the substrate by the setting mask;

On the sidewall of feature, form protective layer;

Remove the bottom of protective layer, so that expose substrate;

Use second etch process that cavity is etched in the substrate.

13. method as claimed in claim 12 is characterized in that first etch process comprises:

A kind of halogen-containing processing gas is provided at least;

Use forms plasma about 200-1200 watt source power from processing gas.

14. method as claimed in claim 12 is characterized in that forming protective layer and comprises:

Substrate is exposed to from the plasma of oxygen-containing gas and the formation of one or more inert gases, so that form oxide skin(coating) in feature.

15. method as claimed in claim 14 also comprises:

Be provided at the O between about 100-500sccm ₂And the Ar between about 100-300sccm;

Use forms plasma about 500-1500 watt source power from processing gas.

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