CN101292346A - Process for integrating planar and non-planar CMOS transistors on bulk substrates and devices fabricated by this process - Google Patents

Abstract

A process enabling the integration of planar (10) and non-planar (20, 30) transistors on a bulk semiconductor substrate, wherein the channels of all transistors can be defined over a continuous width range.

Description

Process for integrating planar and non-planar CMOS transistors on bulk substrates and devices fabricated by this process

technical field

[0001] The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to methods of incorporating non-planar transistors with variable channel widths into bulk semiconductor CMOS processes.

Background technique

[0002] Planar transistors have been fabricated on bulk semiconductor substrates for decades. Transistor 100 shown in FIG. 1A is such a planar device. An active region having opposing sidewalls 106 , 107 and a top surface 108 is formed between insulating regions 110 on the bulk semiconductor substrate 101 .

The insulating region 110 substantially covers the opposing sidewalls 106 and 107 . The top semiconductor surface 108 is divided into a source region 116 , a drain region 117 and a channel region covered by a gate insulating layer 112 and a gate electrode 113 . In planar transistor designs, the device is typically controlled (ie, gated) by capacitive coupling between the top semiconductor surface 108 and the gate electrode 113 . Because the channel is gated by a single gate electrode-semiconductor interface, planar transistors are often referred to as single-gate devices.

[0003] Recently, non-planar transistors have been within the scope of improvements to address the Short Channel Effect (SCE) that affects planar nanoscale transistors. The semiconductor channel of a non-planar transistor is non-planar, and the gate electrode is coupled to the channel via more than one surface, typically via a non-planar formed sidewall portion. Transistor 150 shown in FIG. 1B is one such non-planar device. The active semiconductor region has opposing sidewalls 106 , 107 and a top surface 108 formed on the substrate including the insulating region 103 on the carrier 102 . The top surface 108 and the opposite sidewalls 106 , 107 are divided into a source region 116 , a drain region 117 and a channel region covered by a gate insulating layer 112 and a gate electrode 113 . The transistor is designed to be gated by opposing sidewalls 106, 107 and the top surface 108 of the device (reducing the SCE effect). Because the channel is gated by multiple gate electrode-semiconductor interfaces, non-planar transistors are often referred to as multi-gate devices.

[0004] Non-planar devices, ie, multi-gate devices, have generally been formed on substrates containing an insulating layer, often referred to as semiconductor-on-insulator (SOI). Although non-planar devices formed on SOI have many advantages, there are also many disadvantages. For example, the channel width of a non-planar transistor on SOI is limited by the final thickness of the active silicon layer of the insulating region formed on the SOI substrate. Thus, circuit designers are limited to one fundamental width, and many times that width for all transistors of a circuit formed on a substrate. As shown in FIG. 1C , a plurality of non-planar bodies, each having a source region 116 and a drain region 117 , are electrically coupled in parallel through a common gate electrode 113 through a gate insulating layer 112 to form a device 175 . Device 175 limits circuit design flexibility because the current carrying width can only be increased discretely, not continuously. Compared with traditional planar transistors, non-planar transistors such as device 175 (as shown in FIG. 1C ) will incur layout penalties due to the limitation of lithography pitch. Another disadvantage of devices formed on SOI is the known "floating body" effect, caused by buried insulating layers, which causes the loss of the ground plane for the transistors. In addition, non-planar transistors formed on SOI substrates may suffer from poorer thermal conductivity and increased overall cost compared to devices formed on bulk substrates.

Description of drawings

[0005] FIG. 1A is a perspective view illustrating a conventional planar type single-gate transistor formed on a bulk semiconductor substrate, and FIG. 1B is a perspective view illustrating a conventional non-planar type multi-gate transistor formed on an SOI substrate.

[0006] FIG. 2 is a perspective view illustrating a circuit device of an embodiment of the present invention, the circuit device having a planar type transistor and a non-planar type transistor.

[0007] FIGS. 3A-3G are perspective views illustrating a method of fabricating a device having planar and non-planar transistors according to an embodiment of the present invention.

Detailed ways

[0008] A novel CMOS device structure and method of making the device are described. In the following description, numerous specific details are set forth, such as specific materials, dimensions and processes, etc., in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing processes have not been described in particular detail in order not to unnecessarily obscure the present invention.

According to the embodiment of the present invention shown in Figure 2, three transistors (planar device 10, non-planar device 20 with the first channel width and non-planar device 30 with the second channel) form On a single "bulk semiconductor" substrate 201 . Transistors 10, 20 and 30 are each bonded to a semiconductor substrate (to prevent floating body effects), and both planar and non-planar transistor designs have channel widths that can be independently defined to any value, not just discrete values. By having non-planar transistors 20, 30 with different sidewall heights, different channel widths can be specified, and the performance requirements of individual parts of a single device can be passed between planar transistors (with fundamental SCE effects) and non-planar transistors. Any combination of type transistors (with reduced SCE effect) is individually satisfied. In a particular embodiment of the invention, the microprocessor core (including the logic area) is made of planar transistors, while the microprocessor's cache memory (including memory such as SRAM) is made of non-planar transistors. In another particular embodiment of the invention, parts of the circuit that require a large total current, such as the driver part, are made of planar transistors with a wider current-carrying channel than the non-planar transistors used for other parts of the circuit. The channel width of the transistor.

[0010] Embodiments of the non-planar transistors of the present invention include, but are not limited to, dual-gate, FinFET, tri-gate, pi-gate or omega-gate designs. In some embodiments, all non-planar transistors are "tri-gate" designs with top gates, while in other embodiments all non-planar transistors are "dual-gate" designs with only sidewall gates.

[0011] Substrate 201 is composed of a "bulk semiconductor" such as, but not limited to, a single crystal silicon substrate or a gallium arsenide substrate. In another embodiment of the present invention, the substrate 201 is a bulk silicon semiconductor having a doped epitaxial silicon layer with an impurity concentration level between 1×10 ¹⁶ -1×10 ¹⁹ atoms/cm ³ , with p conductivity type or n conductivity type. In another embodiment of the present invention, the substrate 201 is a bulk silicon semiconductor substrate having an undoped, ie intrinsic, epitaxial silicon layer. In "bulk semiconductor" substrates, unlike SOI substrates, there is no "buried" insulating layer between the semiconductor parts used to make the active devices and the semiconductor parts used for handling.

[0012] As shown in FIG. 2, transistors 10, 20, and 30 include active regions 204, 224, and 244 on a bulk semiconductor substrate. The distance between insulating regions 210 defines a single transistor active region width. Active regions 204, 224, 244 have top surfaces 218, 238, 258 and bottom surfaces 208, 228, 248, respectively. As shown in FIG. 2 , bottom surfaces 208 , 228 , and 248 are defined to be substantially flush with the bottom surface of isolation region 210 . For simplicity of illustration, the semiconductor active region of FIG. 2 is said to be "above" the substrate, which is the portion of the semiconductor below reference planes 208, 228, and 248. However, if a different reference plane is selected, the active region can also be considered to be "in" the substrate. The sidewall of the active region is partially exposed from the gate insulating layer, and the control gate electrode is called "gate-coupled sidewall". As shown in FIG. 2 , insulating region 210 substantially covers sidewalls 206 and 207 of active region 204 of transistor 10 . Therefore, the planar single-gate transistor 10 does not have gate-coupling sidewalls because the distance between the top surface 218 and the bottom surface 208 is approximately equal to the boundary thickness of the insulating region 210 . Likewise, the active region of transistor 10 is only primarily coupled to top surface 218 of control gate 213 , and the channel width is equal to the width of top surface 218 . However, for non-planar device 20 , the portion of sidewall pair 226 , 227 extending on the top surface of adjacent insulating region 210 is “gate-coupled,” which portion contributes to the overall channel width of device 20 . As shown in FIG. 2 , the “gate coupling sidewall” height of transistor 20 is equal to the distance between top surface 238 and bottom surface 228 minus the thickness of adjacent insulating region 210 . In an embodiment of the invention, as shown in transistor 30 of FIG. 2 , the height of the gate-coupling sidewalls is substantially equal to the width of the top surface 258 active region. In another embodiment of the present invention, the gate-coupling sidewall height of the non-planar transistor is between half the width of the active region and twice the width of the active region. In a particular embodiment of the invention, the non-planar transistor has an active region width and a gate-coupling sidewall height less than 30 nanometers, more specifically less than 20 nanometers.

[0013] The current-carrying width of the non-planar transistor according to the embodiment of the present invention can actually be continuously and individually set to any desired value by changing the height of the gate-coupling sidewall. As described in FIG. 2 , the sidewalls 226 , 227 of transistor 20 have a first gate-coupling sidewall height, while the sidewalls 246 , 247 of transistor 30 have a second, different gate-coupling sidewall height. Thus, transistor 20 has a first current-carrying channel width, and transistor 30 has a second, different current-carrying channel width. Because the current-carrying channel width of non-planar transistors increases as the height of the gate-coupling sidewall increases, in the embodiment shown in FIG. 2 , transistor 20 has a channel width greater than that of transistor 30 . Therefore, embodiments of the present invention have non-planar transistors with continuously variable channel widths, thereby providing circuit design flexibility that was difficult to obtain with previous non-planar transistors.

[0014] In an embodiment of the present invention, no layout efficiency penalty is incurred for non-planar transistors having a channel width greater than the minimum width. Design efficiency is the ratio of the absolute current-carrying width of a non-planar device design to that of a typical planar device occupying the same design width. In the embodiment of the present invention, the height of the gate-coupling sidewall of a single non-planar transistor is set to provide the desired full current-carrying width. Therefore, the setting of the current carrying width does not depend on the increase in the number of parallel non-planar devices with discrete channel widths. Because channel width increases with sidewall height rather than top surface area, no additional design width is required to increase the channel width of non-planar transistors fabricated in accordance with certain embodiments of the present invention. As such, these particular embodiments increase the packing density of the device and may have greater layout efficiency than a single unit (unity).

之间的氮氧化硅膜片。在本发明另一实施例中，栅电介质层212是高K栅介质层，诸如金属氧化物介质，诸如(但不限于)氧化钽、氧化钛、二氧化铪、氧化锆和氧化铝。栅介质层212可为其它类型高K介质，诸如(但不限于)铅锆钛酸盐(lead zirconium titanate(PZT))。[0015] As shown in FIG. 2, the transistors 10, 20, and 30 have a gate insulating layer 212. In the non-planar embodiment described, the gate insulating layer 212 surrounds the active region and is in contact with the exposed semiconductor surface. In these embodiments, the gate dielectric layer 212 is in contact with the sidewalls and top surfaces of the active regions of the transistors 20 and 30 , as shown in FIG. 2 . In other embodiments, such as special FinFET or dual-gate designs, the gate dielectric layer contacts only the sidewalls of the active region and not the non-planar device top surface 238,258. In planar transistor embodiments, such as transistor 10 in FIG. 2 , the gate insulating layer is formed only on top surface 218 . The gate insulating layer 212 can be any known dielectric material that is compatible with the semiconductor surface and the gate electrode 213 . In an embodiment of the present invention, the gate dielectric layer is a silicon dioxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ) or silicon nitride (Si ₃ N ₄ ) dielectric layer. In a special embodiment of the present invention, the gate dielectric layer 212 is formed with a thickness of 5-

Silicon oxynitride diaphragm between. In another embodiment of the present invention, the gate dielectric layer 212 is a high-K gate dielectric layer, such as a metal oxide dielectric such as (but not limited to) tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, and aluminum oxide. The gate dielectric layer 212 can be other types of high-K dielectric, such as (but not limited to) lead zirconium titanate (PZT).

[0016] Transistors 10, 20 and 30 have a gate electrode 213, as shown in FIG. In some embodiments, the gate electrode 213 is in contact with the gate dielectric layer 212 formed on the sidewall of each non-planar transistor 20 , 30 . In planar embodiments, such as transistor 10 , gate electrode 213 contacts the gate dielectric layer on top surface 218 . Gate electrode 213 has a pair of laterally opposing sidewalls separated by a distance that defines the gate length (L _g ) of transistors 10 , 20 and 30 . In an embodiment of the invention, the _Lg of the planar transistor 10 and the non-planar transistors 20, 30 is between about 20 nm and about 30 nm. The gate electrode 213 has an effective width equal to the current-carrying width of the semiconductor channel controlled by the gate electrode 213 . In an embodiment of the present invention, the effective current-carrying width of the non-planar device is larger than the effective width of the planar device. In a specific embodiment, as shown in FIG. 2 , the gate-coupling sidewall height of each sidewall 226 , 227 is greater than the width of the top surface 218 . As such, the effective gate electrode width of transistor 20 is greater than the effective gate electrode width of transistor 10 . In another embodiment, the effective width of the gate electrode of transistor 10 is greater than the effective width of the gate electrode of transistor 20 . In yet another embodiment of the present invention, the gate electrode is physically connected between a planar device and a non-planar device, between multiple planar devices or between multiple non-planar devices, that is, is continuous.

[0017] Gate electrode 213 of FIG. 2 may be formed from any suitable gate electrode material having a suitable work function. In an embodiment of the invention, the gate electrode comprises polysilicon. In further embodiments, the gate electrode is composed of a metal such as tungsten, tantalum nitride, titanium nitride or titanium silicide, nickel silicide, cobalt silicide. Suitably, the gate electrode 213 does not have to be a single material, but may be a composite (such as a metal/polysilicon electrode) stack of thin films.

[0018] Transistors 10, 20 and 30, as shown in FIG. 2, each have a source region 216 and a drain region 217. A source region 216 and a drain region 217 are formed on opposite sides of the gate electrode 213 in the active region. Source region 216 and drain region 217 are formed to have the same conductivity type, such as n-type or p-type, depending on whether the transistor is an nMOS device or a pMOS device. In an embodiment of the invention, the source region 216 and the drain region 217 have a doping concentration of 1×10 ¹⁹ -1×10 ²¹ atoms/cm ³ . Source region 216 and drain region 217 may be formed at a single concentration, or they can include subregions of different concentrations or subregions of different impurity distributions, such as tip regions (eg, source or drain extension regions).

[0019] As shown in FIG. The channel regions of transistors 10, 20, and 30 can be independently doped to impurity levels suitable for particular device geometries, gate stacks, and performance requirements. When the channel region is doped, generally the source region 216 and the drain region 217 are doped into opposite conductivity types. For example, nMOS device 205 has source and drain regions of n conductivity type, while the channel region is doped to p conductivity type. In some embodiments of the present invention, the channel regions of the non-planar devices 20, 30 are intrinsic, ie undoped, while the channel regions of the planar devices are doped. In an embodiment of the invention, the channel regions of transistors 10, 20 and 30 are all doped. When the channel region is doped, it can be doped to the extent that the conductivity is 1x10 ¹⁶ -1x10 ¹⁹ atoms/cm ³ .

[0020] A method of fabricating a CMOS device on a bulk substrate according to an embodiment of the present invention (as shown in FIG. 2) is illustrated in FIGS. 3A-3G. In a particular embodiment, fabrication begins with a "bulk" single crystal silicon substrate 201 . In some embodiments of the present invention, the substrate 201 is ^a silicon semiconductor having a doped epitaxial region, and the ^doped epitaxial region has a p conductivity type or ^an n Conductive type. In another embodiment of the present invention, the substrate 201 is a silicon semiconductor having non-doped, ie intrinsic epitaxial, silicon regions. In other embodiments, bulk substrate 201 is any other known semiconductor material, such as gallium arsenide (GaAs), indium antimonide (InSb), gallium antimonide (GaSb), gallium phosphide (GaP), phosphide Indium (InP) or carbon nanotubes (CNT).

[0021] A mask is used to define the active area of the transistor. The mask can be any known material suitable for defining a semiconductor substrate. As shown in FIG. 3A, in an embodiment of the invention, mask 310 is formed from a photolithographically defined and etched dielectric material. In another embodiment, the mask 310 itself is a photo-definable material. In a particular embodiment, as shown in FIG. 3A , masking layer 310 may be a composite stack of materials, such as an oxide/nitride stack. If the mask layer 310 is a dielectric material, known processes such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or uniform spin The masking material is deposited using a coating process, while the mask is defined using well-known photolithography and etching processes. In one embodiment of the present invention, the width of the mask 310 is defined by the minimum lithographic dimension. In another embodiment, the minimum width of the mask 310 is sublithographic, formed by known process methods, such as dry develop process, oxidation/lift-off process or spacer-based craft. In a particular embodiment of the invention, the width of mask 310 is less than 30 nanometers, more specifically, less than 20 nanometers.

至约以容纳介质绝缘区。在又一实施例中，槽320蚀刻成深度为约

至之间。[0022] As shown in FIG. 3B, once the mask layer 310 is defined, a portion of the semiconductor on the bulk substrate 201 is etched using known methods to form a recess or trench 320 in the substrate in alignment with the mask 310. The active region defined by the isolation etching has a depth sufficient to insulate the elements from each other, and forms a gate-coupling sidewall of sufficient height to achieve the maximum ideal channel width of the non-planar transistor. In a specific embodiment of the invention, groove 320 is etched to a depth equal to the maximum ideal channel width of the non-planar transistor plus about

to about to accommodate the dielectric isolation area. In yet another embodiment, groove 320 is etched to a depth of about

to between.

[0023] As shown in FIG. 3C, the trench 320 is then filled with a dielectric to form a shallow trench isolation (STI) region 210 on the substrate 201. In one embodiment of the present invention, an oxide or nitride liner is formed on the bottom and sidewalls of trench 320 by known methods such as thermal oxidation or thermal nitridation. Trenches 320 are then blanket-deposited with oxide on the liner by, for example, a high density plasma (HDP) chemical vapor deposition process. The deposition process will also form a dielectric layer on top of mask 310 . The filled dielectric layer may then be removed from the top of mask 310 by a chemical, mechanical or electrochemical polishing process. Continue grinding until the mask 310 is exposed to form the insulating region 210, as shown in FIG. 3C. In a particular embodiment of the invention, mask 310 is also selectively removed by some well-known means. In another embodiment, as shown in Figure 3C, a portion of mask 310 remains.

如图3C所示。在本发明的实施例中，在选择性的阱区注入和掩模剥离之后，通过公知的净化方法(诸如用HF)从有源区顶面218、238和258去除掩模310或天然氧化物。在本发明的又一实施例中，用公知的工艺在顶面218、238和258生长或沉积牺牲氧化物。[0024] Well regions can then be selectively formed for pMOS and nMOS transistors, if desired. The well region can be formed by doping the active region to a desired impurity concentration by any known process. In an embodiment of the present invention, active regions 204 ^, 224 ^, and 244 ^are selectively doped with p conductivity type or n conductivity type. In a particular embodiment, the well region extends deep into the semiconductor, about

As shown in Figure 3C. In an embodiment of the invention, after selective well implantation and mask stripping, mask 310 or native oxide is removed from active region top surfaces 218, 238, and 258 by well-known cleanup methods, such as with HF. . In yet another embodiment of the invention, a sacrificial oxide is grown or deposited on the top surfaces 218, 238, and 258 using known techniques.

[0025] The insulating regions can then be selectively protected with a masking material to enable selective definition of non-planar devices. In one embodiment, as shown in FIG. 3D, a mask 330 is formed in a manner similar to that described above (see FIG. 3A). Mask 330 is either a photolithographically definable material or a known "hard" mask material that is typically patterned by photolithography and etching processes. In the embodiment shown in FIG. 3D, mask 330 is a photoresist, a photolithographically definable material. As shown in FIG. 3D , mask 330 is used to protect insulating region 210 adjacent to active region 204 and active region 224 of planar device 10 . Additional masking layers may be used, if desired, to selectively protect various other insulating regions.

[0026] Next, the insulating region not protected by the mask is etched and recessed, so that the sidewall of the tube in the active region of the non-planar crystal is exposed. As shown in FIG. 3E , the insulating region 210 not protected by the mask 330 is etched, while the semiconductor active region 224 is not substantially etched such that at least a portion of the semiconductor sidewalls 226 and 227 are exposed. In an embodiment where the semiconductor active region is silicon, the insulating region 210 may be recessed with an etchant including fluorine ions, such as HF. In some embodiments, the insulating region 210 is recessed using a known anisotropic etching process, such as a plasma process or an RIE process using a gaseous etchant such as but not limited to C2F6. In yet another embodiment, an isotropic etch may be followed by an isotropic etch, such as a known dry etch process using a gas such as NF3, or a known wet etch process such as HF , so as to completely remove the insulating medium from at least a part of the sidewall of the semiconductor active region. In some embodiments, only the unprotected portion of the insulating region is removed during the recess etch. In a particular embodiment (not shown), the recess etch acts selectively on the insulating liner material on the insulating fill material such that the insulating recess etch along the liner region directly adjacent to the active region is deeper than the insulating fill. district. In this way, the width of the recess etch can be tightly controlled with the pad width to enable high transistor packing density.

之间。在其它实施例中，最终绝缘厚度显著大于约

在本发明的一实施例中，绝缘区210凹陷大约与半导体有源区224顶面238的宽度相同的量。在其它实施例中，绝缘区210凹陷显著大于顶面238的宽度。[0027] After the non-selective blanket recess etching, the insulating region is selectively recessed by a certain amount, so that the amount of recess reaches the final gate coupling sidewall required by the channel width of the designed non-planar transistor. high. The final gate-coupling sidewall height of the transistor is determined by the cumulative amount, ie, the depth, of recesses in adjacent insulating regions. The isolation recess depth is limited by the isolation requirements and modest aspect ratios of the device. For example, if the insulating recess produces too large an aspect ratio, subsequent processing can inadvertently cause spacer artifacts. In a particular embodiment of the invention, a portion of the insulating region is recessed with a final insulating thickness of about to about

between. In other embodiments, the final insulation thickness is significantly greater than about

In one embodiment of the invention, the isolation region 210 is recessed by approximately the same amount as the width of the top surface 238 of the semiconductor active region 224 . In other embodiments, the isolation region 210 is recessed substantially greater than the width of the top surface 238 .

[0028] In an embodiment of the present invention, as shown in FIG. 3F, mask 330 is removed by known methods, and second mask 340 is formed in a manner similar to that previously discussed with reference to FIG. 3D. Mask 340 protects active region 224, while insulating region 210 surrounding active region 244 is recessed as shown in FIG. 3E. In this embodiment, different sidewall heights can be achieved for 244 compared to 224 , and thus, non-planar transistor 30 is formed with a different channel width than non-planar transistor 20 . It should be understood that the process of selectively masking a portion of the insulating region and a certain amount of recess etching of the insulating region can be repeated many times and in many ways to achieve a range of gate-coupling sidewall heights, corresponding to a series of non-planar transistor channel widths.

[0029] Once the selective isolation recess etch is complete, any isolation mask is removed using known techniques. A final clean, such as an HF clean, may be performed on all active areas to further recess all insulating areas, if desired. In a specific embodiment of the present invention, sacrificial oxidation and blanket oxide etching or cleaning are additionally performed to improve the surface quality of the semiconductor, and then further customize the active surface through corner rounding, feature shrinking, etc. The shape of the area.

[0030] Then, according to the type of non-planar device (double gate, triple gate, etc.), a gate dielectric layer is formed on the active region. In the triple-gate embodiment of the present invention, as shown in FIG. 3G , the gate dielectric layer 212 is formed on the top surface of each source region 204, 224 and 224, and on or adjacent to the exposed sidewall 226, Formed on 227 and 246, 247. In some embodiments, such as dual gate embodiments, the gate dielectric is not formed on top of the non-planar active region. The gate dielectric can be a deposited dielectric or a grown dielectric. In an embodiment of the present invention, the gate dielectric layer 212 is a silicon oxide dielectric film grown by a dry/wet oxidation process. In one embodiment of the present invention, the gate dielectric film 212 is a deposited high-K metal oxide dielectric, such as tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, and aluminum oxide or another high-K dielectric , such as barium strontium titanate (BST). High-K films can be formed using known processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).

之间。在特定实施例中，栅电极材料的厚度由绝缘区凹陷蚀刻的深度限定，因为栅电极材料往往会沿着凹陷蚀刻产生的外形(topography)而形成导电的隔层(spacer)。对于这样的实施例，栅电极材料的过度蚀刻能够防止因绝缘凹部深度小于栅电极材料的厚度而造成这样的隔层后果(spacer artifacts)。在一实施例中，栅电极具有至少三倍于栅耦合侧壁高度(前面定义为有源区侧壁的露出部分)的厚度。在本发明的一实施例中，栅电极包括多晶硅。在本发明的一些实施例中，栅极材料是金属，诸如(但不限于)钨、氧化钽、氮化钛或硅化钛、硅化镍、或硅化钴。在又一些实施例中，电极由多晶硅(poly-silicon)和金属的复合物形成。在本发明的一实施例中，栅电极213用公知的工艺方法形成，诸如在衬底上毯式地沉积栅电极材料，然后将栅电极材料图案化。在本发明的其它实施例中，栅电极使用“取代栅”(″replacement gate″)方法形成。在这些实施例中，栅电极使用类似于通常在波纹金属化(damascene metallization)工艺中使用的填充和研磨方法，通过该法可将凹陷的绝缘区用栅电极材料完全地填充。[0031] A gate electrode is then formed on each active region. In an embodiment of the present invention, as shown in FIG. 3G , the gate electrode 213 is formed above the top surfaces 218, 238, 258, and is formed on the gate dielectric layer 212 along the sidewalls 226, 227 and 246, 247 or with the adjacent. The gate electrode can be formed to a thickness of 200 to

between. In certain embodiments, the thickness of the gate electrode material is defined by the depth of the recess etch of the isolation region, since the gate electrode material tends to form conductive spacers along the topography produced by the recess etch. For such an embodiment, overetching of the gate electrode material can prevent such spacer artifacts caused by the insulating recess depth being less than the thickness of the gate electrode material. In one embodiment, the gate electrode has a thickness at least three times the height of the gate-coupling sidewall (defined above as the exposed portion of the sidewall of the active region). In an embodiment of the invention, the gate electrode includes polysilicon. In some embodiments of the invention, the gate material is a metal such as, but not limited to, tungsten, tantalum oxide, titanium nitride or silicide, nickel silicide, or cobalt silicide. In yet other embodiments, the electrodes are formed from a composite of poly-silicon and metal. In an embodiment of the present invention, the gate electrode 213 is formed by a known process, such as blanket deposition of the gate electrode material on the substrate, and then patterning the gate electrode material. In other embodiments of the present invention, the gate electrode is formed using a "replacement gate" method. In these embodiments, the gate electrode uses a fill and grind method similar to that typically used in damascene metallization processes, by which the recessed insulating regions are completely filled with gate electrode material.

[0032] In an embodiment of the present invention, the source region 216 and the drain region 217 of the transistors 10, 20 and 30 are formed in the active region on both sides of the gate electrode 213, as shown in FIG. 3G. For pMOS transistors, the active region is doped into p conductivity type, and the doping concentration is between 1x10 ¹⁹ -1x10 ²¹ atoms/cm ³ . For nMOS transistors, the active region is doped with ions of n conductivity type at a concentration between 1x10 ¹⁹ -1x10 ²¹ atoms/cm ³ . So far, the CMOS transistor of the present invention is basically completed, and the rest is only the interconnection of devices.

[0033] Although the present invention has been described with respect to structural features and/or methodological actions, it should be understood that the invention defined by the appended claims is not necessarily limited to the specific features or actions described. Rather, the specific features and acts are disclosed as particularly suitable implementations of the claimed invention.

Claims (20)

1. A device comprising: Planar transistors and non-planar transistors formed on bulk semiconductor substrates. 2. The device of claim 1, wherein the planar transistor is in a microprocessor core and the non-planar transistor is in a microprocessor SRAM area. 3. The device of claim 1, wherein the planar transistor has a smaller channel width than the non-planar transistor. 4. A semiconductor device, comprising: a first active region having sidewalls substantially covered by an adjacent insulating region on the bulk semiconductor substrate; a second active region having sidewalls extending on top surfaces of adjacent insulating regions on said bulk semiconductor substrate; a first gate insulating layer on a top surface of the first active region and a second gate insulating layer adjacent to at least a portion of the sidewall of the second active region; a first gate electrode on the first gate insulating layer and a second gate electrode adjacent to the second gate insulating layer; and A first pair of source/drain regions on opposite sides of the first gate electrode and a second pair of source/drain regions on opposite sides of the second gate electrode. 5. The device of claim 4, wherein the second gate insulating layer is on a top surface of the second active region, and the second gate electrode is on the second gate insulating layer. 6. The device of claim 4, wherein the first gate electrode and the second gate electrode are physically connected. 7. A device comprising: a first multi-gate transistor having a first channel width and a second multi-gate transistor having a second channel width formed on a bulk semiconductor substrate, wherein the first The channel width is different from the second channel width. 8. The device of claim 7, wherein the first multi-gate transistor has a first gate-coupling sidewall height and the second multi-gate transistor has a different gate-coupling sidewall height than the first gate-coupling sidewall height. The second gate coupling sidewall height. 9. The device of claim 7, further comprising a single gate transistor formed on the bulk semiconductor substrate. 10. A method of forming planar and non-planar transistors, comprising the steps of: forming a first active region having sidewalls adjacent to a first insulating region on the bulk semiconductor substrate; forming a second active region having sidewalls adjacent to a second insulating region on the bulk semiconductor substrate; exposing at least a portion of the sidewall of the second active region by recessing a top surface of the second insulating region; forming a first gate insulating layer on the top surface of the first active region; forming a second gate insulating layer adjacent to at least a portion of the sidewall of the second active region; forming a first gate electrode on the first gate insulating layer; forming a second gate electrode adjacent to the second gate insulating layer; and In the first active region and the second active region, a first pair of source/drain regions are formed on opposite sides of the first gate electrode, and on opposite sides of the second gate electrode A second pair of source/drain regions is formed on both sides. 11. The method of claim 10, wherein the top surface of the second insulating region is recessed with an etchant containing fluoride ions. 12. The method of claim 10, wherein the top surface of the second insulating region is recessed with anisotropic etching. 13. The method of claim 10, wherein a pad region of the insulating region is recessed by an amount greater than an adjacent filling region of the insulating region. 14. The method of claim 10, further comprising photolithographically defining the second insulating region to be recessed. 15. The method of claim 10, wherein a sacrificial oxide layer is formed on top surfaces of the first and second active regions before recessing the top surfaces of the second insulating region . 16. The method of claim 10, wherein forming the first and the second gate electrodes comprises a replacement gate process. 17. The method of claim 10, wherein the step of defining the first and the second gate electrodes comprises etching the gate electrode material to remove from the sidewalls of the second active region The gate electrode is substantially removed. 18. A method of forming a non-planar transistor, comprising the steps of: forming a first active region having sidewalls adjacent to a first insulating region on the bulk semiconductor substrate; forming a second active region having sidewalls adjacent to a second insulating region on the bulk semiconductor substrate; recessing a top surface of the first insulating region by a first amount to expose at least a portion of the sidewall of the first active region; recessing the top surface of the second insulating region by a second amount to expose at least a portion of the sidewall of the second active region, the second amount of recessing being different from the first amount of recessing ; forming a first gate insulating layer adjacent to at least a portion of the sidewall of the first active region, and forming a second gate insulating layer adjacent to at least a portion of the sidewall of the second active region Insulation; forming a first gate electrode adjacent to the first gate insulating layer, and forming a second gate electrode adjacent to the second gate insulating layer; and A first pair of source/drain regions is formed on opposite sides of the first gate electrode, and a second pair of source/drain regions is formed on opposite sides of the second gate electrode. 19. The method of claim 18, further comprising the steps of: forming a first gate insulating layer and a first gate electrode on the top surface of the first active region; and A second gate insulating layer and a second gate electrode are formed on the top surface of the second active region. 20. The method of claim 18, further comprising the steps of: Before forming the first gate insulating layer and the second gate insulating layer, the sacrificial oxide layer is blanket etched.

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