CN101315887A - Ohmic contact fabrication method for semi-insulating SiC semiconductor device - Google Patents

Abstract

The invention discloses a manufacturing method for an ohmic contact of a semi-insulating SiC semiconductor device, which mainly solves the problem that the specific contact resistance of the ohmic contact is large. The process is: pretreat the SiC substrate, and epitaxial GaN heavily doped layer or SiC:Ge transition layer on the SiC substrate; determine the ohmic contact area on the GaN heavily doped layer or SiC:Ge transition layer, and Perform KOH etching on the GaN heavily doped or SiC:Ge transition layer region between the ohmic contact regions, so that the SiC substrate in the channel region is the Si plane; on the ohmic contact region and the Si plane of the channel region Deposit a layer of SiN material with high dielectric constant; etch away the SiN material on the ohmic contact area, and deposit metal in this area to lead out the electrodes. The invention has the advantages of lower than contact resistance and sheet resistance and long service life, and can be used for making ohmic contact to semi-insulating SiC semiconductor devices.

Description

Ohmic contact fabrication method for semi-insulating SiC semiconductor device

technical field

The invention belongs to the technical field of microelectronics and relates to the manufacture of semiconductor devices, in particular to a method for manufacturing ohmic contacts of semi-insulating SiC devices.

Background technique

As a third-generation semiconductor material, SiC material has considerable advantages over the first-generation semiconductor materials represented by Si and the second-generation semiconductor materials represented by GaAs. Due to its large forbidden band width, it can be used in Working at a higher temperature is conducive to the preparation of high-power devices, and the large carrier saturation drift speed and mobility provide a good foundation for the response speed of the device. At present, the development of SiC devices has become a research hotspot in the field of semiconductor device circuits. Ohmic contact is an important process in the preparation of SiC devices. In high temperature and high power applications, the low specific contact resistance and high stability of ohmic contact are two important factors that determine the performance of the device. In the working state of high current density, small resistance will cause a large voltage drop, and the thermal stability of the ohmic contact ratio contact resistance at high temperature is an inevitable factor to be considered, otherwise the degradation of the ohmic contact will lead to changes in the performance of the entire device Bad or even ineffective. So far, good ohmic contact preparation is still one of the most important and active aspects for the process research of SiC materials.

However, making SiC devices with low ohmic contacts is more difficult than other semiconductor devices. The current specific contact resistance values of n-type and p-type SiC ohmic contacts are usually in the range of 10 ^-5 -10 ^-6 Ωcm ² and 10 ^-4 -10 ^-5 Ωcm ² respectively, and the results of this specific contact resistance are highly dependent on the wafer Surface carrier concentration, metal selection, wafer surface pretreatment and metallization thermal annealing conditions. In order to obtain a good ohmic contact, ion implantation is usually used to increase the carrier concentration on the wafer surface, or high-temperature alloy annealing, or alloys and other compounds are used to make ohmic contacts.

At present, the ohmic contact of n-type SiC is mainly obtained by metallizing annealing of Ni-based metals at 950-1050°C, and its specific contact resistance can basically meet the requirements of device applications. However, for semi-insulating SiC materials, Al-Ti metal and silicide are usually used for metallization annealing at 900-1180°C. Due to the higher contact barrier height, it is more difficult to form a low specific contact resistance, which affects device performance.

In terms of SiC ohmic contact metals, there are a wide range of options, including Cr, Ni, TiN, TiW, NiCr, W, TiW, Ti, TiAl, Mo, Wmo, AuTa, TiAu, Ta, WtiNi and TiC metals or alloy. At present, the choice of ohmic contact metal for SiC materials has developed from a single metal to multi-metal or alloy research, and carbides, silicides, borides, etc. have appeared. The alloying and annealing conditions for the preparation of ohmic contacts are even more diverse, so there is no mature method for the ohmic contact of semi-insulating SiC devices so far.

content of the invention

The purpose of the present invention is to provide a method for making ohmic contacts of semi-insulating SiC semiconductor devices, to solve the problem that semi-insulating SiC is not easy to form low specific contact resistance due to high contact barriers, and to improve the service life and output characteristics of semi-insulating SiC devices .

The technical key to realize the purpose of the present invention is to add a layer of SiC:Ge transition layer or GaN heavily doped layer between the semi-insulating SiC and the metal to play a buffer role and facilitate the manufacture of ohmic contacts.

Technical solution 1, the ohmic contact process for making a semi-insulating SiC semiconductor device is as follows:

(1) Pretreat the SiC substrate, and epitaxially grow a GaN heavily doped layer on the SiC substrate;

(2) Determine the ohmic contact region on the heavily doped layer, and perform KOH etching on the heavily doped channel region between the ohmic contact regions, so that the SiC substrate of the channel region is a Si surface;

(3) Deposit a layer of high dielectric constant SiN material on the ohmic contact region and the Si surface of the channel region;

(4) Etching away the SiN material on the ohmic contact area, and depositing metal in this area to lead out the electrodes.

Technical solution 2, the ohmic contact process of making a semi-insulating SiC semiconductor device is as follows:

1) Pretreat and clean the SiC substrate, and epitaxially grow a transition layer of SiC:Ge on the SiC substrate;

2) Determining the ohmic contact region on the transition layer, and performing KOH etching on the channel region of the transition layer between the contact regions, so that the SiC substrate in the channel region is a Si surface;

3) Depositing a layer of high dielectric constant SiN material on the contact area and the Si surface of the channel region;

4) Etching away the SiN material on the ohmic contact area, and depositing metal in this area to lead out the electrodes.

The deposition metal described in the step (4) of the above-mentioned technical scheme 1 is divided into two cases: for the heavily doped region of n-type GaN material, Ti, Al, Ti and Au are evaporated by electron beam to form Ti/Al /Ti/Au structure, and annealing treatment is carried out under the condition of temperature 900±5℃ and time 60s; for the heavily doped region of p-type GaN material, Ni, Ti and Au are evaporated by electron beam to form Ni/ Ti/Au structure, and annealed at a temperature of 950±5°C and a time of 90s.

The deposition metal described in step 4) of the above-mentioned technical scheme 2 is to form a Ti/Ni structure by electron beam steaming Ti with a thickness of 3nm and Ni with a thickness of 200nm, and to the Ti/Ni structure in a nitrogen atmosphere Annealing, the annealing temperature is 800±5℃, and the duration is 3min.

The present invention has the following advantages:

1. Since a layer of SiC:Ge transition layer is epitaxially formed between the semi-insulating SiC and the metal to form a material with a gradual change in composition, the contact barrier is effectively reduced, and annealing can be performed at a lower temperature of 800±5°C. 150°C lower than the conventional annealing temperature.

2. Since a GaN heavily doped layer is added between the semi-insulating SiC and the metal, the GaN material of the doped layer is close to the forbidden band width of the semi-insulating SiC material, forming a good match between the two materials, which is convenient Fabrication of Ohmic Contacts.

Tests show that the on-state resistance of the semi-insulating 4H-SiC photoconductive switch ohmic contact made by the method of the present invention is in the range of 20-35Ω, the dark-state resistance is in the range of 4.86×10 ¹² -5.08×10 ¹² Ω, and the dark-state resistance The ratio to the on-state resistance is in the range of 1.39×10 ¹¹ -2.54×10 ¹¹ , but domestic semi-insulating SiC ohmic contacts have not been reported yet.

Description of drawings

Fig. 1 is the flowchart of technical scheme 1 of the present invention;

Fig. 2 is a flowchart of technical solution 2 of the present invention.

Detailed ways

The method of the invention can be used to make ohmic contacts of various semi-insulating SiC semiconductor devices, for example, semi-insulating SiC photoconductive switches, semi-insulating SiC transistors and semi-insulating SiC large-scale integrated circuits.

Embodiment 1, taking a semi-insulating 4H-SiC photoconductive switch as an example, describes in detail the specific process of making an ohmic contact of a semi-insulating 4H-SiC semiconductor device according to the present invention.

Referring to Fig. 1, the process of making ohmic contact on the semi-insulating 4H-SiC photoconductive switch of the present invention is as follows:

In step 1, pretreatment is performed on the semi-insulating 4H-SiC material used.

First, passivate the surface of the semi-insulating 4H-SiC substrate with molten KOH. The etching temperature and etching time are 210°C and 15s, respectively; then, the passivated wafer is sequentially treated with acetone, methanol, and deionized water. Clean the sample, and finally, use the RCA standard cleaning process to remove the oxide layer on the surface of the substrate.

Step 2, epitaxially growing a heavily doped layer.

The heavily doped GaN heavily doped layer is epitaxially grown on the pretreated substrate by the OMVPE method, and the p-type GaN heavily doped layer is used for the deeply compensated semi-insulating 4H-SiC, and the doping dose is 4×10 ¹⁹ , the optimal thickness of doping is 100nm; for deep donor-compensated semi-insulating SiC, n-type GaN heavily doped layer is used, the doping dose is 3.8×10 ¹⁹ and the thickness is 100nm, and the optimal thickness of doping is 100nm.

Step 3, determining the electrode contact area, etching the heavily doped layer between the electrode contact areas, and treating the outer surface of the 4H-SiC into a Si surface.

Firstly, using known photolithography technology to determine the electrode contact area; then immersing the substrate in 80% KOH solution at 130±5° C. for 3 minutes by wet etching process to etch away the heavily doped GaN layer; then The etched 4H-SiC material is processed into a Si surface, and the Si surface is chemically cleaned.

In step 4, epitaxially epitaxially layer a layer of high dielectric constant SiN on the heavily doped layer and on the Si surface between the heavily doped regions.

Epitaxial SiN adopts ultra-high vacuum plasma enhanced chemical vapor deposition method, and is carried out on the entire Si surface between the heavily doped layer and the heavily doped region. The process conditions are: the background vacuum is 8×10 ^-9 Torr, the reaction chamber The temperature is maintained at 300±5°C, and the thickness is the same as that of the GaN heavily doped layer for simplicity of the process.

Step 5, etching the SiN on the heavily doped layer.

Soak the epitaxial SiN substrate in a concentrated H ₃ PO ₄ etching solution to etch away the SiN layer on the electrode contact area.

Step 6, depositing metal.

First, the surface of the sample is cleaned by the RCA method for the heavily doped region;

Secondly, metal deposition is performed on the heavily doped GaN material, namely:

Ti 300

Au 750

For the deep main compensation type semi-insulating 4H-SiC, the p-type GaN heavily doped layer is used, and the deposited metal adopts the Ni/Ti/Au structure, in which Ni and Ti are evaporated by electron beams, and Au is steamed by thermal evaporation. The entire Ni/Ti/ The thickness of the Au metal structure are: Ni 500

Ti 300

Au 750

Al 2000

Ti 300

Au300

For the deep donor-compensated semi-insulating 4H-SiC, the n-type GaN heavily doped layer adopts the Ti/Al/Ti/Au structure, in which Ti is steamed by electron beam, Au and Al are steamed by thermal steaming, and the whole Ti/Al/Ti The thickness of the /Au metal structure is respectively: Ti 300

Al 2000

Ti 300

Au300

Then, the metal layer is subjected to rapid annealing in a nitrogen atmosphere, namely:

For deposited metals with Ni/Ti/Au structure, anneal at 950±5°C for 90s;

For deposited metals with Ni/Ti/Au structure, annealing is carried out at a temperature of 900±5°C for 60s. Solder pin leads on Ni/Ti/Au or Ni/Ti/Au metal layers and package with the overall device.

Referring to Fig. 2, the process of making another ohmic contact on the semi-insulating 4H-SiC photoconductive switch according to the present invention is as follows:

In step 1, pretreatment is performed on the semi-insulating 4H-SiC material used.

First, passivate the surface of the semi-insulating SiC substrate with molten KOH, the etching temperature is 210±5°C, and the etching time is 15s; then, the passivated wafer is sequentially treated with acetone, methanol and deionized water. The substrate is cleaned, and finally, the oxide layer on the surface of the substrate is removed by RCA standard cleaning process.

Step 2, epitaxially growing a 4H-SiC:Ge transition layer.

On the pretreated substrate, a 4H-SiC:Ge transition layer is epitaxially grown by HWCVD method, and its thickness is at least 250nm.

Step 3, determine the electrode contact area, etch the 4H-SiC:Ge transition layer between the electrode contact areas, and process the outer surface of the 4H-SiC into a Si surface.

First, use known photolithography technology to determine the electrode contact area; then use conventional ion beam etching process to etch away the 4H-SiC:Ge transition layer between the contact areas; then process the etched 4H-SiC material into Si surface, and the Si surface is chemically cleaned.

Step 4, epitaxial high dielectric constant SiN on the 4H-SiC:Ge transition layer and on the Si surface between the 4H-SiC:Ge transition layers.

Epitaxial SiN adopts ultra-high vacuum plasma enhanced chemical vapor deposition method, and is carried out on the entire Si surface between the transition layer and the transition layer region. The process conditions are: the background vacuum is 8×10 ^-9 Torr, and the temperature of the reaction chamber is maintained at 300±5°C. For simplicity of the process, the thickness of the epitaxial SiN is the same as that of the 4H-SiC:Ge transition layer, which is also taken as 250nm here.

Step 5, etching SiN on the 4H-SiC:Ge transition layer.

Soak the epitaxial SiN substrate in a concentrated H ₃ PO ₄ etching solution to etch away the SiN layer on the electrode contact area.

Step 6, depositing metal.

Firstly, the surface of the sample was cleaned by RCA in the transition layer area; then the Ti/Ni structure was deposited by electron beam evaporation on the 4H-SiC:Ge transition layer, the thicknesses of which were Ti 3nm and Ni 200nm respectively; and then the Ti/Ni The Ni structure is annealed in a nitrogen atmosphere, the annealing temperature is 800±5°C, and the duration is 3min. The pin leads are soldered on the Ti/Ni metal layer and packaged with the overall device.

In Embodiment 2, a semi-insulating 3C-SiC photoconductive switch is taken as an example.

The steps of using the heavily doped layer to make its ohmic contact are the same as the scheme 1 of Example 1, the only difference is that in step 2, a p-type GaN heavily doped layer is used for the deep main compensation type semi-insulating 4H-SiC, and the doping dose The optimum doping thickness is 2.875×10 ¹⁹ , and the optimum doping thickness is 71.88nm; for deep donor compensation type semi-insulating SiC, n-type GaN heavily doped layer is used, the doping dose is 2.73×10 ¹⁹ , and the optimum doping thickness is 71.88nm.

The steps of making the ohmic contact with the intermediate layer are basically the same as the scheme 2 of the embodiment 1, the only difference is that the optimal thickness of the epitaxial 3C-SiC:Ge in the step 2 is 180nm.

In Embodiment 3, a semi-insulating 6H-SiC photoconductive switch is taken as an example.

The steps of using the heavily doped layer to make its ohmic contact are the same as the scheme 1 of Example 1, the only difference is that in step 2, a p-type GaN heavily doped layer is used for the deep main compensation type semi-insulating 4H-SiC, and the doping dose The optimum doping thickness is 3.75×10 ¹⁹ , and the optimal doping thickness is 93.75nm; for deep donor compensation type semi-insulating SiC, an n-type GaN heavily doped layer is used, the doping dose is 3.56×10 ¹⁹ , and the optimum doping thickness is 93.75nm.

The steps of making an ohmic contact with the intermediate layer are basically the same as the scheme 2 of the embodiment 1, the only difference is that the optimal thickness of the epitaxial 3C-SiC:Ge in the step 2 is 234nm.

Effect of the present invention can be further illustrated by measured experimental result:

Actual measurement experiment 1, the semi-insulating 4H-SiC photoconductive switch made by the method 1 of the present invention was tested at room temperature, the on-state resistance of the ohmic contact was in the range of 26-35Ω, and the dark-state resistance was 4.78×10 ¹² -4.97 In the range of ×10 ¹² Ω, the ratio of the dark-state resistance to the on-state resistance is in the range of 1.37×10 ¹¹ -1.91×10 ¹¹ . The results of the IV characteristics of the photoconductive switch show that when the applied bias voltage is 1000V, the output current can reach 46.3A, compared with the GaAs photoconductive switch under the same conditions, it has a stronger output capability.

In actual measurement experiment 2, the photoconductive switch made by method 2 of the present invention was tested at room temperature, and the on-state resistance of the ohmic contact was in the range of 20-30Ω, and the dark-state resistance was in the range of 4.92×10 ¹² -5.10×10 ¹² Ω Inside, the ratio of the dark state resistance to the on state resistance is in the range of 1.94×10 ¹¹ -2.50×10 ¹¹ . The results of the IV characteristics of the photoconductive switch show that when the applied bias voltage is 1000V, the maximum output current can reach 48.9A. Compared with the GaAs photoconductive switch under the same conditions, it has stronger output capability.

The actual test shows that the semi-insulating SiC semiconductor photoconductive switch made by the method of the present invention has good output characteristics, its on-state resistance is in the range of 20-35Ω, and the dark-state resistance is in the range of 4.86×10 ¹² -5.08×10 ¹² Ω , the ratio of the dark-state resistance to the on-state resistance is in the range of 1.39×10 ¹¹ -2.54×10 ¹¹ , and there is no such report in China.

The method of the present invention is not limited to making the photoconductive switch of this example, so the above examples do not constitute any limitation to the present invention. Obviously, other semi-insulating SiC semiconductor devices can be made with the method of the present invention in the technical field, but these methods belong to within the protection scope of the present invention.

Claims (9)

1. the Ohm contact production method of a semi-insulation SiC semiconductor device comprises following process:

(1) the SiC substrate is carried out preliminary treatment, and on the SiC substrate epitaxial growth GaN heavily doped layer;

(2) determine the ohmic contact zone on described heavily doped layer, and the GaN heavily doped region between the ohmic contact zone is carried out the KOH etching, the SiC substrate that makes this channel region is the Si face;

(3) on the ohmic contact zone and on the Si face of described channel region, the SiN material of deposit one deck high-k;

(4) etch away SiN material on the ohmic contact zone, and at this zone depositing metal, extraction electrode.

2. the manufacture method of ohmic contact according to claim 1, wherein step (1) is described at SiC substrate epitaxial growth heavily doped layer, and for p type GaN heavily doped layer, dopant dose is 2.875 * 10 ¹⁹,～4 * 10 ¹⁹, the thickness of doped layer is 71～100nm; For n type GaN heavily doped layer, dopant dose is 2.73 * 10 ¹⁹,～3.8 * 10 ¹⁹, the thickness of doped layer is 71～100nm.

3. Ohm contact production method according to claim 1, wherein the thickness of the described depositing high dielectric constant SiN of step (3) is identical with heavily doped layer.

4. the manufacture method of ohmic contact according to claim 1, the described depositing metal of step (4) wherein, heavily doped region for n type GaN material, be to steam Ti, Al, Ti and Au by electron beam, form the Ti/Al/Ti/Au structure, and be 900 ± 5 ℃ in temperature, the time is to carry out annealing in process under the condition of 60s.

5. the manufacture method of ohmic contact according to claim 1, the described depositing metal of step (4) wherein, heavily doped region for p type GaN material, be to steam Ni, Ti and Au by electron beam, form the Ni/Ti/Au structure, and be 950 ± 5 ℃ in temperature, the time is to carry out annealing in process under the condition of 90s.

6. the manufacture method of a semi-insulation SiC semiconductor device ohmic contact comprises following process:

1) the SiC substrate is carried out preliminary treatment, the transition zone of epitaxial growth SiC:Ge on the SiC substrate;

2) determine the ohmic contact zone on transition zone, and the transition zone channel region between the contact area is carried out the KOH etching, the SiC substrate that makes this channel region is the Si face;

3) on the nurse contact area and on the Si face of described channel region, deposit one deck high-k SiN material;

4) etch away SiN material on the ohmic contact zone, and at this district's depositing metal, extraction electrode.

7. the manufacture method of ohmic contact according to claim 6, wherein step 1) described on the SiC substrate epitaxially grown SiC:Ge transition zone, its thickness is 180-250nm.

8. the manufacture method of ohmic contact according to claim 6, wherein step 3) described on the ohmic contact zone with the Si face of channel region on the thickness of high-k SiN material of deposit identical with the thickness of described SiC:Ge transition zone.

9. Ohm contact production method according to claim 6, the described depositing metal of step 4) wherein, be that to steam thickness by electron beam be that Ti and the thickness of 3nm is the Ni of 200nm, form the Ti/Ni structure, and this Ti/Ni structure annealed in the nitrogen atmosphere, annealing temperature is 800 ± 5 ℃, duration 3min.

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