CN101311944A - Read-out method, responser and inquirer - Google Patents

Abstract

In the prior art, 1 bit is taken as unit and the interrogator sends and receives identification number circularly, so complicated instruction, number of a plurality of action steps, a complicated trigger, control over the switch of sending and receiving, control of memorizer address counter and complicated logic circuits such as data comparison circuit, and the like, are required, and the problem that the size of chip can not be controlled exists. In the application, an interrogator which wirelessly reads an identification number in a responder and the corresponding responder are provided.. When the clock pulse is modulated by the carrier wave with high frequency and sent to the responder through the antenna of the interrogator, a first situation of short interval of the clock pulse and a second situation of long interval of the clock pulse exist. By combining the clock pulse of the first situation and the clock pulse of the second situation and controlling to readout the identification number from the interrogator, the miniaturization of the size of the semiconductor chip of the responder can be realized, thus controlling rise of cost of the semiconductor chip.

Description

Readout methods, transponders and interrogators

This application is a divisional application of the patent application whose application number is 03826707.1, the application date is August 11, 2003, and the invention title is "reading method, transponder and interrogator".

technical field

The present invention relates to an identification method and device for identifying responders by transmitting and receiving signals between an interrogator and a plurality of responders. In particular, it relates to a method and apparatus for controlling the blocking and identification of reply signals from an interrogator, a plurality of transponders.

Background technique

The documents referred to in this specification are as follows. Documents are referenced by this document number.

Document 1: International Publication No. 98/21691

Document 2: International Publication No. 00/36555

When a plurality of transponders exist in the effective radio wave area of the interrogator, it is necessary to identify response signals from the plurality of transponders. There is Document 1 as a technique for preventing signal confusion from a plurality of transponders.

In this document 1, an interrogator receives an interrogation signal, and a transponder transmits a predetermined number of bits. The interrogator receives a predetermined number of bits transmitted from the responder, and sends a reply to the responder. When the reply bit is equal to the bit transmitted by itself, the responder transmits a predetermined number of bits subsequent to the already transmitted bit, and performs the same process in a loop. Unequal transponders do not participate in the identification process until the next interrogation signal is received. By performing this process in a loop, only one transponder finally recognizes its own identification number. By repeating this identification process until there is no more unprocessed transponders, the identification process of a plurality of transponders is completed.

In this document 1, since the transmission and reception with the interrogator is carried out cyclically for a predetermined number of bit units, various commands (inquiry signal, received bit reply signal, identification failure notification signal, identification complete Notification signal), the number of steps (stage) accompanying the command, the flip-flop (flip-flop) indicating the state transition, the switching of sending and receiving of the data comparison circuit, and the logic circuit for controlling the memory address counter.

Document 2 discloses that a transponder having a memory storing an identification number transmits the content of the identification number in synchronization with a clock pulse from an interrogator. Document 2 simplifies the transmission and reception method by excluding commands during communication by transmitting an identification number from a transponder as an RFID in accordance with a clock pulse from an interrogator.

Contents of the invention

The summary of the representative contents among the inventions disclosed in this application will be briefly described as follows.

A transponder, characterized in that it includes: an interrogator that wirelessly reads the identification number in the transponder and a corresponding transponder, and transmits a clock from the antenna of the interrogator to the corresponding transponder through high-frequency carrier modulation When pulse, there is the 1st case that the interval of the clock pulse is short and the 2nd case that the interval of the clock pulse is long, by combining the clock pulse of the 1st case and the clock pulse of the 2nd case, it is controlled to read the clock pulse from the interrogator. identification number.

Description of drawings

FIG. 1 is a diagram showing a clock interval distinguishing circuit.

FIG. 2 is a diagram showing an example of a counter and memory circuit configuration.

Fig. 3 is a diagram showing an example of the interior of the transponder.

Fig. 4 is a diagram showing an example of a memory structure of a transponder.

FIG. 5 is a diagram showing an example of a timer and memory configuration.

Fig. 6 is a diagram showing an example of reading from a transponder.

FIG. 7 is a diagram showing an example of read retry (retry).

FIG. 8 is a diagram showing a situation where congestion control is required.

Fig. 9 is a diagram showing an example of an operation flow of the transponder of the present invention.

Fig. 10 is a diagram showing an example of a protocol.

FIG. 11 is a diagram showing an example of a flip-flop.

FIG. 12 is a diagram showing an example of electron beam writing.

FIG. 13 is a diagram showing an example of a state of a memory.

FIG. 14 is a diagram showing an example of a clock interval detection circuit.

Fig. 15 is a diagram showing the internal structure of an interrogator.

Fig. 16 is a diagram showing an operation flow of the interrogator.

Detailed ways

Due to the increase in recycling costs due to large-scale distribution, there is a problem of reducing the manufacturing unit price of disposable RFID tags (tags).

In order to arrange a plurality of RFIDs in the effective radio wave area from the interrogator, and to expand the effective radio wave area beyond the size of the RFID installation object and the arrangement interval, the RFID must have a blocking control function.

In the present invention, the following problems are solved by simplifying transponders, interrogator transmission and reception methods, and congestion control functions: the function of assembling RFID is increased by increasing the number of chips (RFID) cut out from one wafer (wafer). Tags) to improve mass productivity, enable RFID to have a blocking control function, and at the same time reduce the manufacturing unit price.

For example, the recycling cost of RFID attached to clothing and other products increases, and one-time use is suitable for business and operation. Furthermore, in order to manage a plurality of products in a shipping box or the like without opening the package, it is necessary to perform congestion control.

Therefore, it is necessary to reduce the cost of RFID tags to make them single-use, so that they can be used for congestion control.

FIG. 8 shows an example in which a plurality of transponders 902 to 906 of the present invention exist in an effective radio wave area 901 of an interrogator 907 . In FIG. 8 , an example of a case where there are five transponders 902 to 906 is shown. When there are a plurality of transponders in the effective radio wave area 901, each transponder may be operated according to two kinds of clock pulses (modulation signals) of long and short lengths from the interrogator to read the memory of each transponder. Details will be given later.

In FIG. 10, the communication method of the responder and the interrogator, and the congestion control method are shown specifically. In FIG. 10 , a case where two chips A and B exist in the effective radio wave area is shown. In addition, in this embodiment, for the sake of simplification, the case where the counter in each chip is 2 bits is shown. When the clock pulse from the interrogator starts, chip A and chip B simultaneously set the initial value of the predetermined page number to the counter. In this embodiment, the page number is 01 in chip A and 11 in chip B. The interrogator sends clock pulses at short intervals, hoping to read the memory of the transponder, but because the counters in each chip are not 00, each chip does not send out the memory content. In this way, since there is no incoming data, the interrogator determines that there is no transponder operating, stops the transmission of short-interval clock pulses, and transmits long-interval clock pulses. In this way, each chip counts up the page number by 1 (+1 count up), which becomes 10 in chip A and 00 in chip B. At this time, chip B sets the action switching trigger, and sends the memory data to the interrogator at the next short-interval clock pulse. If this ends normally, the interrogator also sends long interval clock pulses, and the counter of chip A becomes 00 in any case, and chip A sends data. As in this example, chip A and chip B transmit memory data without overlapping, and the interrogator performs operations such as page rounds at high speed based on long-interval clock pulses, thereby shortening the readout time for congestion control.

Fig. 9 is a flowchart showing a communication method with an interrogator and a congestion control method in the transponder of the present invention. The transponders 902 to 906 demodulate the modulated signal from the interrogator 907, and take out two types of clock pulses with long or short intervals.

As the basic operation of the transponder, the page number is counted up (count up) by a clock pulse with a long clock interval, and the memory address is counted up by a clock pulse with a short clock interval (hereinafter, a long clock pulse is referred to as a long clock. pulse, and a short clock pulse is called a short clock pulse). By using two types of clock pulses with different clock intervals, the configurations of the communication method, the congestion control method, the responder, and the interrogator can be simplified.

In addition, in the embodiments of the present application, the clock interval represents the time interval between a certain L level and the next coming L level, that is, the time from the falling edge of the H level to the L level to the falling edge Interval representation.

The clock width is specified by the length of time in the L level state, that is, by the time interval from the falling edge falling from the H level to the L level to the rising edge rising from the L level to the H level. In the flowchart of FIG. 9, these clock intervals and clock widths are separately controlled.

When the action switching flip-flop is in the reset (reset) state, the page number is counted up (count up), and when the action switching flip-flop is in the set (set) state, the memory address is counted up.

In 1001, a transponder receives an initial clock pulse from an interrogator. The initial clock pulse can be either long or short.

In 1002, a counter is set with the page number (random number) uniquely stored for each transponder as an initial value. The page number is a number that specifies the order in which the identification numbers are transmitted when there are multiple transponders in the effective radio wave area of the interrogator.

In 1003, the width of the L level of the next clock pulse is monitored, and the transponder receives the next clock pulse to check whether the interval is long or short. When the clock interval is long (in the case of a long clock), the process proceeds to 1010 , and when the clock interval is short (in the case of a short clock), the process proceeds to 1008 .

In 1010, the operation switching trigger in the transponder is reset, that is, the page number can be counted up, and the process proceeds to 1004, and the page number set in the counter is counted up by +1.

In 1005, if a carry (carry) is issued from the counter, it means that the content of the counter has become 0, that is, in the binary counter, the count is increased one by one, and the action of becoming all 0 after all 1 is performed. When all 0s are reached, a carry is issued. It is checked whether a carry is sent from the counter. At this time, when a carry is sent in 1006, the action switching trigger is set by using the carry of 1005 in the transponder. That is, it is in a state where the count up of the memory address can be performed. Returns to 1003 to wait for the next clock pulse when no carry is issued.

In 1007, wait for the next clock pulse, monitor the width of the L level of the clock pulse, return to 1003 when the clock pulse width is narrow, advance to 1011 when the clock pulse width is wide, and set the counter to be different from 1002 Page number, back to 1003.

On the other hand, in the case of proceeding from 1003 to 1008, in 1008, it is checked whether an action switching trigger located in the responder is set. If it is set, the memory address is incremented by +1 in 1012 of FIG. 9 , the process proceeds to 1009 , and a 1-bit transponder number is issued. Then, go to 1007.

Here, it should be noted that this process is only an embodiment, and the branch condition of 1003 in FIG. 9 can also be reversed, and the branch condition of 1007 in FIG. 9 can also be reversed.

If the transponder receives short-interval clock pulses, it will confirm whether the action switching trigger in this chip is set. If the Action Toggle Trigger is set, the memory data is sent out, if not set, short interval clock pulses are ignored.

Since there is an action switch trigger in the transponder, when the trigger is set, the transponder sends the number corresponding to the clock pulse of the interrogator, and when the action switch trigger is not set, the action of sending the number is not performed , thereby preventing the transponders from simultaneously operating and blocking number transmission.

If probabilistically many wireless IC tag chips (IC tag chips) exist in the effective radio wave area, the possibility of page number collision becomes high. If multiple transponders have the same page number, the action switching trigger is set at the same time and sends the number to the interrogator at the same time. Since the interrogator receives the numbers from multiple transponders through logical OR, the built-in number The error detection code in is not a regular code, and the interrogator received an error number.

Therefore, multiple page numbers are stored in the transponder. If the first page number set in the counter is the same as the page number of other transponders, it is reset to be different from the first page number through the process of 1011 in FIG. 9 The second page number, thereby reducing the possibility of two consecutive page number conflicts. It is possible to set the number of bits of the page number and how many page numbers there are in the transponder according to the application (the number of transponders existing in the effective radio wave area of the interrogator, etc.).

When the modulation method is ASK, when viewed from the interrogator side, the case where the transponder does not exist in the effective radio wave range of the interrogator is the same as the case where the transponder transmits a bit indicating L level. If the first bit of the memory of the transponder that stores the identification number (or the first bit when the identification number is sent to the interrogator) on the electricity becomes an H level bit, the interrogator can immediately confirm the transponder that can send the identification number The existence of is suitable from the viewpoint of shortening the reading time of the identification number. More generally, in the transmission sequence of each bit of the identification number, if the bit indicating the H level is prepared electrically before half of the total number of bits, the interrogator can confirm that the identification number can be transmitted as soon as possible. The presence of a transponder is therefore suitable.

At this time, the noise does not prevent the transponder from being found or that multiple transponders exist and operate. In the presence of this noise, it is uncertain which flow the transponder performs in Figure 9, and the interrogator stops sending modulation signals to the transponder, and retries readout again.

In addition, when a bit at an electrical H level is not transmitted, it is regarded as not receiving data on the interrogator side. That is, in the transmission sequence of each bit of the identification number, if there is no bit electrically indicating the H level before half of the total number of bits, the interrogator regards that there is no responder.

Fig. 16 is a flowchart showing a communication method with an interrogator and a congestion control method in the transponder of the present invention.

In 1601, the interrogator sends an initial clock pulse to the transponder.

In 1602, the interrogator checks whether it is the serial number receiving mode, if it is the serial number receiving mode, then proceed to 1604, if not, proceed to 1603.

At 1604, a short clock pulse is sent from the interrogator to the transponder, and a 1-bit identification number is received from the transponder.

In 1605, it is checked whether 1 bit is received. If it is received, go to 1606, and if not, go back to 1602.

In 1606, it is checked whether all the identification numbers have been received, and if not all of the identification numbers have been received, the process returns to 1602 in FIG. 16 . When all are received, proceed to 1607 to check whether the error check code is normal.

In 1607, the loop returns to 1602 to perform reading when it is not normal, and proceeds to 1608 if it is normal.

In 1608, check whether it is a page switch, if it is a page switch, proceed to 1609, send out a long clock pulse, so that another page number is set to the transponder counter. When it is not page switching, return to 1602 .

Figure 6 shows the clock pulses sent by the interrogator when the identification number is read from the transponder. There is a period 701 in which the count of the page number is increased by a long clock pulse, and a period 702 in which the memory is read out by a clock pulse at a short interval.

In Fig. 7, the clock pulses sent by the interrogator when the identification number is read from the transponder are shown. It is the same as FIG. 6 except that the memory readout period 702 based on short-interval clock pulses has a cyclic portion. The looping portion of the memory read period 702 corresponds to the looping process of (1003)→(1008)→(1012)→(1007)→(1003) in the flow of FIG. 9 .

In the first memory read period 702 in the cycle of the memory read period 702, the interrogator reads the memory of the transponder, and after reading all the memory, confirms that the data is read from the error check code. normal or abnormal.

In an abnormal situation, the interrogator continuously sends short interval clock pulses to retry reading before sending the next long interval clock pulse. A binary counter representing the address of the memory in the transponder is continuously incremented cyclically according to short intervals of clock pulses, thus cyclically sending the data of the memory.

On the other hand, in the case of cyclically sending short-interval clock pulses from the noise source, the interrogator cyclically sends out short-interval clock pulses, data reading is performed normally as the presence of a transponder, but data reading is performed normally without a transponder. In the case of only the noise source, only the data that is the noise source can be read. When a plurality of transponders operate, these transponders operate cyclically, and the interrogator may detect data, which is not regarded as normal data.

FIG. 3 shows the configuration of transponders 902 to 905 in FIG. 8 . The transponders 902 to 905 of the present invention can be produced by various techniques, but in the following embodiments, the case where they are implemented as semiconductor chips will be described as an example.

The antenna 301 receives the modulated signal from the interrogator and is connected to the rectification circuit 302 . The rectification circuit 302 doubles and rectifies the modulated signal, and supplies the power supply voltage VDD. The high-frequency modulated signal is demodulated by the clock pulse extraction circuit 303 , and the low-frequency clock pulse is extracted and input to the counter memory circuit 305 . In the counter of the counter memory circuit, each bit of the identification number in the memory is selected, the impedance between the antennas 301 is changed by the load switch (load switch) 304, and the identification number is sent to the interrogator.

FIG. 15 shows the internal structure of the interrogator in FIG. 8 . The antenna 1501 of the interrogator receives radio waves from the transponder, and is connected to a high-frequency transmitting and receiving circuit 1502 . The modulation circuit 1503 performs modulation for the clock pulse waveform, and the demodulation circuit 1504 detects and demodulates the signal from the transponder. Digital signal processing for transmission and reception is performed by a baseband (BaseBand) processing circuit 1505 . The congestion control circuit 1506 is built in the baseband processing circuit 1505, and is configured with a logic circuit to implement the control flow shown in FIG. 16 .

FIG. 2 shows a circuit diagram of the counter memory circuit 305 in FIG. 3 . The counter memory circuit 305 counts up the page number, counts up the memory address for selecting each bit of the identification number, and selects each bit of the identification number. In the counter memory circuit 305, a blocking control circuit 306 composed of a logic circuit is built in, and controls the flow shown in FIG. 9 .

In order not to increase the chip size, it is effective to share the counter for counting up the page number and the counter for counting up the memory address.

In the present application, an example of the case where the counter is shared is shown, but it is not necessary to share the counter when the chip area is not considered.

In the case of a shared counter, the number of bits of the page number is the number of bits of the memory address identifying the number. The memory address is generally about 10 bits, so the page number is also about 10 bits, which may conflict with the page numbers of other transponders. In this case, as described above, the collision probability can be reduced by storing a plurality of page numbers in the transponder as in 1011 in FIG. 9 and resetting them in the counter. In this application, an example in which two types of page numbers are prepared is shown.

The counter 116 counts up either one of the clock pulses CK1 and CK2 selected by operating the output of the switching flip-flop.

The action switching trigger has the function of switching the page number count increase action and the memory address count increase action. For the action switching flip-flop, when the output of the flip-flop 124 of the highest order in the counter 116 transitions from H level to L level, the output of the action switching flip-flop changes from L level to H level. Here, the set (set) state means when the output of the operation switching flip-flop is H, and the reset (reset) state means when the output of the operation switching flip-flop is L.

When the output of the action switching flip-flop 117 is H, CK1 generated at short clock pulse intervals is input to the flip-flop 115 of the counter 116 through the AND gate (gate) 120 and the OR gate 122, and the counter 116 counts the memory address according to CK1 Increase. In the page number count up operation, the initial value of the page number is set in advance, and the count up is performed based on the signal CK2 based on the long-interval clock pulse.

When the output of the action switching flip-flop 117 is at L level, this signal becomes H level through the inverter gate 123, and CK2 generated at long clock pulse intervals is input to the trigger through the AND gate 120 and the OR gate 122. The device 115 and the counter 116 count up the page number according to CK2. In the count up operation of the memory address, the content of the counter is all 0, that is, counting up is performed according to the signal CK1 based on the short-interval clock pulse from when the output of each flip-flop of the counter is at L level.

The clock pulse interval distinguishing circuit 125 is a circuit for distinguishing CK1, which is a short clock pulse interval, and CK2, which is a long clock pulse interval, from the clock pulses (CLK) from the interrogator. FIG. 1 shows the details. FIG. 1 will be described later.

By connecting the plurality of connection terminals 102 to any one of the electrical H terminal 101 and the electrical L terminal 104 , the page number first setting means 103 holds each bit of the first page number. The page number first setting section 103 electrically sets the connection terminals to HLLH from the left. On the premise of positive logic, it logically represents the number of 1001.

Similarly, by connecting a plurality of connection terminals 109 to the electrical H terminal 105, the second page number setting member 106, and the electrical L terminal 107, each bit of the first page number of the second page number setting member 106 is stored. The page number second setting section 106 sets the connection terminals to LHHL from the left. On the premise of positive logic, it logically represents the number of 0110.

The arrangement of the connection terminals 102, 109 is specifically performed by a pattern (pattern) drawn by an electron beam. In the embodiment of FIG. 2, the counter has 4 bits, but in the present invention, the number of bits may be 4 or more.

According to the selection signals S1 and S2 respectively input to the first selection terminal 110 and the second selection terminal 111 , the selector unit 108 selects either the first page number or the second page number, and inputs it to the counter 116 . More specifically, each bit of the first page number from the connection terminal 102 and a selection signal S1 from the first selection terminal 110 are input to the AND gate 112 . Similarly, each bit of the second page number from the connection terminal 109 and a selection signal S2 from the second selection terminal 111 are input to the AND gate 113 . Outputs of the AND gates 111 and 112 are input to an OR gate 114 . As an initial value of the counter 116 , the output of the OR gate is set to a plurality of flip-flops 115 constituting the counter 116 .

The output of each flip-flop of the counter is input to the memory 118 . The output of the memory is controlled by an AND gate 119 and an action switching flip-flop.

FIG. 5 shows the structure of the counter 116 and the memory 118 of the transponder of FIG. 2 . The memory 118 is composed of a decoder 505 and a memory unit 508 . The memory address output 504 is input to the decoder 505 from each flip-flop constituting the counter 116 in FIG. 2 .

The decoder output 506 (the bit sequence representing X0...X15, Y0...Y7 of FIG. 13) is input from the decoder 505 to the memory unit 508. Each bit of the identification number selected by the decoder output 506 is output from the memory cell to the AND gate 119 as the memory output 507 .

That is, each bit of the identification number corresponding to the count value of the counter 116 during the memory address count up operation is read. The relationship between the memory address and the decoder output may also be such that the memory address and the decoder output correspond one-to-one so that all bits of the identification number are read out.

The counter 502 of FIG. 2 is also used for counting up the memory address and the page number. Therefore, when the counting up of the page number is performed, the address output 504 is also electrically H level or L level. However, by converting the output from the memory 118, The output of the switching flip-flop is input to the AND gate 119, and the AND gate 119 is electrically set to L level, and the output from the memory 118 is ignored, and the contents of the memory are not read from the interrogator, and the transponder is regarded as inactive.

In addition, in the embodiment of FIG. 2 , the counter 502 is also used for counting up the memory address and the page number, so the number of bits of the memory address is equal to the number of bits of the page number.

FIG. 13 shows the data structure of the memory unit 508 of the present invention. In this example, a map format with 16 horizontal columns and 8 vertical rows is shown. In this example, the first transmission data is transmitted to the interrogator in the order of column X0 of row Y0 and column X1 and column X2.

At this time, as described above, assuming that the data of Y0 and X0 of the memory as the first bit of the identification number are always 1, the interrogator immediately reads the head of the memory and can immediately confirm the presence of the transponder. More generally it is appropriate for the interrogator to acknowledge the presence of the transponder as early as possible if the bit which logically indicates the presence of data is set in at least the first half of the transmitted data.

FIG. 11 shows an example of a counter flip-flop used in the present invention. A ground terminal 1103 and a selector terminal 1104 are provided for inputting a signal from the AND gate 1102 and a set (S:set) signal to the NOR gate 1101 , and both are connected to a switching terminal 1105 . In this example, an example in which the ground terminal is connected to the switching terminal is shown. Through the PMOS transistor 1106 and the NMOS transistor, the switching terminal is inverted (inverted) and input to the AND gate. First, when the S signal is electrically at L→H→L level, the output (OUT) of the flip-flop is electrically at L level. Next, as shown in the example in the figure, if the ground terminal is connected to the switching terminal, this state is maintained as it is until the clock pulse (CLK) arrives. When the switch terminal is connected to the selector terminal and the selector terminal becomes L→H→L level, the output (OUT) of the flip-flop changes from L→H. That is, logically set to 1.

In FIG. 12 , a graph 1203 representing a part of the layout pattern in FIG. 11 is lowered to a ground potential graph of 1103 in FIG. 11 . 1204 represents a pattern connected to the selector terminal of 1104 in FIG. 11 . 1205 in FIG. 12 is a graph corresponding to 1105 in FIG. 11 .

The first through hole 1201 is used to connect the metal pattern (metal pattern) 1204 of the upper layer representing the selector terminal and the metal pattern 1205 of the lower layer representing the connection terminal, and the second through hole 1202 is used to connect the metal pattern 1205 of the upper layer representing the ground terminal. The pattern 1203 is connected to the metal pattern 1205 representing the lower layer of the connection terminal, and any one of the first through hole 1201 and the second through hole 1202 is directly drawn with a glass mask pattern or an electron beam to form a pattern. Write the number directly on each wireless tag chip (tag chip) on the wafer by direct drawing with electron beams. This number can also be a random number. Writing is performed on the wafer so that the same page number does not exist, or the number is written so that the number is scattered within the wafer and between wafers. That is, the circuit shown in FIG. 11 can be realized compactly only by wiring and through-holes. Usually, when setting a random number in a flip-flop, a random number generating circuit and a complex circuit for setting are required, but it can be implemented in a small area by forming a pattern.

Fig. 14 shows a circuit for detecting the interval of clock pulses. The output of the first inverting gate 1401 is a signal (CK1) representing the detection result. In FIG. 14 , a constant current can flow through the transistor Q3 through the resistor R1 , the resistor R2 , the transistor Q1 , and the transistor Q2 . Since energy can be supplied from the interrogator to the transponder when there is a carrier wave in the transponder, the clock pulse signal (CLK) in the figure is set shorter when the electrical value is L than when the electrical value is H. That is, there is a negative logic in which there is a clock pulse when CLK is at H level and there is a clock pulse when it is at L level. Therefore, in FIG. 14, when CLK is at the H level, the transistor Q4 is turned off (OFF) because it is a PMOS transistor. At this time, when the first clock pulse is input, CLK becomes L level, and the transistor Q4 is turned on (ON). Then, charge up the capacitor C1. CK1 becomes H→L level. Next, the charge of C1 is discharged through transistor Q3, but according to a short interval of clock pulses, at which point transistor Q4 turns on and charges C1. Conversely, if the interval between clock pulses is long, the voltage of C1 drops when the charge of C1 is discharged, and CK1 becomes L→H level. If the clock pulse arrives, CK1 returns to H→L level. That is, when the clock pulse interval is sufficiently long for the charge discharge of C1, the signal of CK1 generates a signal of L→H→L.

FIG. 1 shows the clock interval distinguishing circuit 116 of FIG. 2 . FIG. 1 is a circuit based on the circuit of FIG. 14 , and transistors Q5, Q6, capacitor C2, and an inverter gate 1402 are added. The first inverting gate 1402 is an inverting output (CK2) that takes part of the capacitor C2 as an input.

Figure 14 adds several components, and by changing C1, C2 and capacitance, clock pulses (CK1, CK2) at different intervals can be detected. In this embodiment, C2 is larger than capacitor C1. Examples of this are transistor Q6 and transistor Q5 and capacitor C2 in FIG. 14 . Set the capacitance value of C2 to be large, or increase the gate length of Q5. According to the situation where the CK1 signal becomes L→H→L level, if there are long interval clock pulses, the CK2 signal becomes L→H→L level. flat.

Fig. 4 shows the format of the memory in the wireless IC tag chip of the present invention. The header portion 401 is located at the head of the memory, the identification number 402 is located at the center of the memory, and the page number portion 403 is located at the end of the memory. The header part 401 is an indication bit indicating the presence of a transponder, and has a function of notifying the interrogator of the presence of the transponder as soon as possible. That is, before sending out the identification number, it is appropriate to prepare a bit that electrically indicates the H level so that the interrogator can confirm the existence of the transponder capable of transmitting the identification number as early as possible. In addition, the header portion 401 may be used as a part of the identification number 402 . The page number portion 403 doubles as an overall error check code. In this way, when the data of the wireless IC tag is sent out in the order controlled by the page number under the congestion control, if the reader is normal, it can be confirmed immediately that the data is sent by the page number while confirming that there is no error according to the page number. Condition.

As described above, according to the present invention, it is possible to simplify the congestion control method in transponders and interrogators, increase the number of chips (RFID tags) that have a congestion control function cut out from the wafer, increase the yield, and reduce the manufacturing unit price. . By increasing the yield and reducing the manufacturing unit price, it can become a one-time use RFID.

Furthermore, a plurality of RFIDs can be arranged in the effective radio wave area of the interrogator, and the effective radio wave area of the interrogator can be increased beyond the size of the RFID installation object and the arrangement interval.

As mentioned above, the invention proposed by this inventor was concretely demonstrated based on an Example, However, this invention is not limited to the said Example, Of course, various changes are possible in the range which does not deviate from the summary. For example, there may be two types of clock pulses, and the functions of the long and short clock pulses may be reversed. In addition, the content stored in the transponder may not be an identification number, but various data.

It can be utilized in RFID which is the technical field which is the background of this application. In addition, the present invention is not limited thereto, and can be applied to, for example, general wireless LANs, congestion control in mobile phones, and the like.

Claims (1)

1. transponder is characterized in that comprising:

The first memory (118) of storage identiflication number;

Configuration is used to receive modulation signal, extraction is included in first and second time clock in the described modulation signal, the concurrent transmission receiving-member (302 of stating identiflication number of serving, 303,304), the clock pulse interval length of described first time clock is different from the clock pulse interval length of second clock pulse;

First counter, configuration is used to count first time clock;

Second counter, configuration is used to count the second clock pulse; And

Storage is as the initial value of above-mentioned first counter and the second memory (103,106) of the page number that is provided with, wherein

Carried out from above-mentioned initial value to setting at above-mentioned first counter under the situation of counting increase, above-mentioned second counter is arranged to counting increases the second clock pulse, and above-mentioned transmission receiving-member is arranged to transmission each bit corresponding to the identiflication number of the count value of above-mentioned second counter.

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