CN101330088A - Integrated circuit package and manufacturing method thereof - Google Patents

Abstract

The invention provides an integrated circuit package and a manufacturing method thereof. The integrated circuit package includes: a transparent substrate having a first surface and a second surface; a semiconductor layer formed on the second surface of the transparent substrate; a photosensitive element formed on the semiconductor layer; a metal plug formed on the second surface of the transparent substrate and electrically connected to the photosensitive element; and the solder ball is formed on the second surface of the transparent substrate and is electrically connected with the metal plug. In the integrated circuit package, the photosensitive element can be directly arranged on the semiconductor layer on the transparent substrate without additional processes such as bonding, notching and the like, so that the manufacturing process can be shortened, and the manufacturing cost can be reduced.

Description

Integrated circuit package and manufacturing method thereof

technical field

The invention relates to an integrated circuit package, in particular to a thinned integrated circuit package and a manufacturing method thereof.

Background technique

In the manufacturing process of the integrated circuit device, the integrated circuit needs to be packaged and used in various application fields, such as computers, mobile phones or digital cameras. Therefore, the structure of the integrated circuit package and its manufacturing method also directly affect the performance and volume of the integrated circuit device.

FIG. 1 shows a cross-sectional view of a conventional integrated circuit package. In FIG. 1 , a photosensitive element 4 and a bonding pad 6 are formed on the silicon substrate 2 , and the bonding pad 6 is electrically connected to the photosensitive element 4 . Next, after the transparent cover plate 10 is bonded to the silicon base 2 , the carrier plate 8 is pasted under the silicon base 2 . After that, the conductive layer 12 extends from the carrier board 8 and the sidewall of the silicon substrate 2 to the bonding pad 6 and electrically connects the solder ball 14 . Since the silicon substrate 2 and the carrier plate 8 both have predetermined thicknesses, the integrated circuit package has a relatively large thickness. Moreover, since the metal plug (not shown in the figure) is formed on the light incident surface, the difficulty of the manufacturing process is increased. Furthermore, in the existing IC package, since the conductive layer 12 is disposed on the periphery of the IC package, the conductive layer 12 is easily damaged during the manufacturing process, resulting in failure of the IC package.

Therefore, there is an urgent need for a new integrated circuit package and its manufacturing method to solve the above problems.

Contents of the invention

In view of this, the object of the present invention is to provide an integrated circuit package. The integrated circuit package includes: a transparent substrate having a first surface and a second surface; a semiconductor layer formed on the second surface of the transparent substrate; a photosensitive element formed on the semiconductor layer; a metal plug formed on the The second surface of the transparent substrate is electrically connected to the photosensitive element; and the solder ball is formed on the second surface of the transparent substrate and electrically connected to the metal plug.

The integrated circuit package as described above, wherein the semiconductor layer comprises silicon, gallium arsenide or silicon germanium.

The above integrated circuit package, wherein the thickness of the semiconductor layer is between 0.1-10 microns.

The integrated circuit package as described above further includes an interlayer dielectric layer formed on the semiconductor layer and surrounding the metal plug.

The above integrated circuit package further includes: a metal pad formed on the second surface of the transparent substrate and electrically connected to the metal plug; and a solder mask covering the metal pad.

The integrated circuit package as described above, wherein the solder ball is formed on the metal pad.

The integrated circuit package as described above, wherein the light incident surface of the integrated circuit package is opposite to the metal plug provided.

Another object of the present invention is to provide a method for manufacturing an integrated circuit package. The manufacturing method of the above-mentioned integrated circuit package includes: providing a transparent substrate having a first surface and a second surface; forming a semiconductor layer on the second surface of the transparent glass substrate; forming a photosensitive element on the semiconductor layer; forming a metal plug plugging on the second surface of the transparent substrate and electrically connecting the photosensitive element; and forming solder balls on the second surface of the transparent substrate and electrically connecting the metal plug.

The manufacturing method of the integrated circuit package as described above, wherein the semiconductor layer is formed by a low temperature chemical vapor deposition method.

In the manufacturing method of the integrated circuit package as described above, the temperature range for forming the semiconductor layer is between 500°C and 800°C.

Another object of the present invention is to provide a method for operating an integrated circuit package, which includes: a transparent substrate having a first surface and a second surface; a semiconductor layer formed on the second surface of the transparent substrate; and a photosensitive element , formed on the semiconductor layer; and metal plugs, formed on the second surface of the transparent substrate, and electrically connected to the photosensitive element; wherein the photosensitive element senses through the first surface of the transparent substrate, the semiconductor layer light, and transmits a signal through the metal plug to the solder ball.

In the above-mentioned integrated circuit package, since the photosensitive element can be directly arranged on the semiconductor layer on the transparent substrate, no additional processes such as bonding and scoring steps are required, so the production process can be shortened, thereby reducing the production cost . In addition, since the metal plug for transmitting information is fabricated in the integrated circuit package, the problem of damage caused by the cutting step can be avoided.

Description of drawings

Figure 1 shows a cross-sectional view of a conventional integrated circuit package;

Fig. 2A-Fig. 2E show the sectional view of making the integrated circuit package of the embodiment of the present invention; And

FIG. 3 shows a flow chart of manufacturing an integrated circuit package according to an embodiment of the present invention.

Wherein, the reference signs are explained as follows:

Related Technical Component Symbols

2～silicon substrate; 4～photosensitive element; 6～bonding pad;

8～loading board; 10～transparent cover plate; 12～conductive layer; 14～solder ball.

The symbol of the embodiment of the present invention

102～transparent substrate; 1021～first surface; 1022～second surface;

104～semiconductor layer; 106～photosensitive element; 108～interlayer dielectric layer;

110～metal plug; 112～interlayer dielectric layer; 114～metal plug;

116～metal pad; 118～solder mask; 120～solder sphere;

130～integrated circuit package body.

Detailed ways

Next, the present invention will be described in detail with embodiments and accompanying drawings. In the drawings or descriptions, similar or identical parts use the same symbols. In the drawings, the shape or thickness of the embodiments may be exaggerated to simplify or facilitate labeling. Component parts in the drawings will be explained with description. It is to be understood that elements not shown or described may have various forms well known to those skilled in the art. In addition, when it is described that a layer is on a substrate or another layer, the layer may be directly on the substrate or another layer, or there may be an intervening layer therebetween.

2A-2E show cross-sectional views of manufacturing an integrated circuit package according to an embodiment of the present invention. As shown in FIG. 2A , a transparent substrate 102 having a first surface 1021 and a second surface 1022 is provided, which can also be called a cover plate. The above-mentioned transparent substrate 102 may preferably be glass or a polymer material such as polyester. The above-mentioned first surface 1021 can be used as a light-incident surface of a subsequently formed integrated circuit package.

In FIG. 2A , next, the semiconductor layer 104 is deposited on the second surface 1022 of the transparent substrate 102 . In an embodiment, the method of forming the semiconductor layer 104 may be a low temperature chemical vapor deposition (CVD) method, such as a temperature between 500° C.˜800° C. The aforementioned semiconductor layer 104 may preferably be a deposited layer of polysilicon. Certainly, the above-mentioned semiconductor layer 104 may also be a deposition layer of silicon germanium (SiGe), gallium arsenide (GaAs) or other suitable semiconductor materials.

In an embodiment, the thickness of the semiconductor layer 104 may be between 0.1-10 micrometers (μm), preferably 3 μm. It is worth noting that the above-mentioned semiconductor layer 104 also serves as the base of the subsequently formed photosensitive element and the path of light incident into the integrated circuit package. Therefore, the thickness of the semiconductor layer 104 should not be too thick or too thin, so as to meet the above two purposes at the same time. Accordingly, the thickness of the semiconductor layer mainly satisfies the above purpose, and the thickness of the above semiconductor layer 104 is only used to illustrate a practical example, and is not intended to limit the present invention.

As shown in FIG. 2B , next, a photosensitive device 106 is formed on the semiconductor layer 104 . In an embodiment, the above-mentioned photosensitive element 106 may be formed by an existing complementary metal oxide semiconductor (CMOS) manufacturing process. To simplify the description, details are not described here.

After forming the above-mentioned photosensitive element 106, then, using, for example, chemical vapor deposition, an interlayer dielectric layer (inter-layer dielectric ILD) 108, such as an oxide layer, is formed on the transparent substrate 102, and covers the above-mentioned photosensitive element 106, as Figure 2B.

In FIG. 2C , a metal plug 110 is formed in the interlayer dielectric layer 108 to electrically connect the photosensitive element 106 . In an embodiment, the metal plug 110 may be formed by patterning the interlayer dielectric layer 108 by photolithography and etching to form an opening and expose the photosensitive element 106 . Then, by such as electrochemical deposition (electrical chemical deposition; ECD), sputtering (sputtering), evaporation (evaporation) or other suitable means, deposition such as copper (copper), aluminum (aluminum) or tungsten (tungsten) The metal layer is on the surface of the transparent substrate 102 and covers the interlayer dielectric layer 108 . Then, a chemical mechanical polishing (CMP) step is performed to remove excess metal layers to form metal plugs 110 in the interlayer dielectric layer 108 .

It is worth noting that the light incident surface of the integrated circuit package and the metal plug are arranged in the opposite direction, that is, the metal plug is formed on the non-light incident surface (backlight surface), thereby increasing the design of the metal plug. elasticity.

As shown in FIG. 2C , after the interlayer dielectric layer 112 is covered on the transparent substrate 102 , then, a metal plug 114 is formed in the interlayer dielectric layer 112 and electrically connected to the metal plug 110 . The method of forming the metal plug 114 may be similar to the method of the metal plug 110 described above, therefore, details are not repeated here.

In another embodiment, after depositing the interlayer dielectric layers 108, 112 on the transparent substrate 102, the metal plugs 110, 114 are respectively formed on the interlayer dielectric layer by using a dual damascene process. Among the layers 108,112.

As shown in FIG. 2C , a metal pad 116 such as copper is formed on the interlayer dielectric layer 112 to electrically connect the metal plug 114 . Then, a solder resist film 118 is coated on the interlayer dielectric layer 112 and covers the metal pad 116 .

In FIG. 2D , solder balls 120 are formed on the metal pads 116 to electrically connect the photosensitive element 106 . In an embodiment, firstly, the solder mask 118 is patterned by photolithography to expose the surface of the metal pad 116 . Afterwards, solder is coated on the exposed metal pad 116 , and a reflow step is performed to form solder balls 120 on the metal pad 116 . The aforementioned solder may preferably be a solder material.

Finally, the individual dies are diced along the pre-cut lines of the individual dies by using a dicing blade to complete the integrated circuit package 130 , as shown in FIG. 2E .

In FIG. 2E , an integrated circuit package 130 according to an embodiment of the present invention is shown. As shown in FIG. 2E , light (arrows in FIG. 2E ) enters the integrated circuit package 130 through the first surface 1021 of the transparent substrate 102 , and passes through the transparent substrate 102 and the semiconductor layer 104 to the photosensitive element 106 . Then, the photosensitive element 106 generates a signal, and transmits the signal to the solder ball 120 through the metal plugs 110 , 114 , and then to the external circuit.

It can be seen that, in the above-mentioned integrated circuit package, the solder balls can be directly connected to the photosensitive element to transmit signals through the metal plugs, without the need of additionally formed metal pads, thus saving manufacturing cost. Furthermore, since the integrated circuit package does not use the carrier substrate and the silicon base, the volume of the integrated circuit package can also be reduced.

FIG. 3 shows a flowchart of fabricating an integrated circuit package according to an embodiment of the invention. First, a transparent substrate is provided, as in step S5. Next, a semiconductor layer is formed on the transparent substrate, such as step S10. Then, a photosensitive element is formed on the semiconductor layer, such as step 15 . Afterwards, metal plugs are formed on the transparent substrate and electrically connected to the photosensitive element, such as step S20. Next, solder balls are formed, and the photosensitive elements are electrically connected through metal plugs, as in step S25. Finally, the dicing blade is used to cut the individual dies along the pre-cut lines of the individual dies, so as to complete the integrated circuit package.

It is worth noting that since the photosensitive part of the photosensitive element is in contact with the semiconductor layer on the light incident surface, that is to say, the metal plug is formed on the non-light incident surface, so that the metal plug formed later does not need to avoid the photosensitive part. Therefore, The manufacturing process tolerance of the metal plug can be increased. In addition, the photosensitive part of the photosensitive element and the metal plug are arranged on the opposite side (the metal plug is arranged on the non-light incident surface), and after the metal plug is formed, the position of the solder sphere can be rearranged, so the solder sphere can also be increased. Make space.

Furthermore, since the photosensitive element can be directly disposed on the semiconductor layer on the transparent substrate without additional processes such as bonding and scoring steps, the manufacturing process can be shortened, thereby reducing the manufacturing cost. In addition, since the metal plug for transmitting information is fabricated in the integrated circuit package, the problem of damage to the conductive layer caused by the cutting step can be avoided, thereby improving the yield of production.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be The scope defined by the appended claims shall prevail.

Claims (10)

1. An integrated circuit package, comprising: a transparent substrate having a first surface and a second surface; a semiconductor layer formed on the second surface of the transparent substrate; a photosensitive element formed on the semiconductor layer; a metal plug formed on the second surface of the transparent substrate and electrically connected to the photosensitive element; and A solder ball is formed on the second surface of the transparent substrate and electrically connected to the metal plug. 2. The integrated circuit package as claimed in claim 1, wherein the semiconductor layer comprises silicon, gallium arsenide or silicon germanium. 3. The integrated circuit package as claimed in claim 1, wherein the thickness of the semiconductor layer is between 0.1-10 microns. 4. The integrated circuit package as claimed in claim 1, further comprising an interlayer dielectric layer formed on the semiconductor layer and surrounding the metal plug. 5. The integrated circuit package of claim 1, further comprising: a metal pad formed on the second surface of the transparent substrate and electrically connected to the metal plug; and The solder resist film is covered on the metal pad. 6. The integrated circuit package as claimed in claim 5, wherein the solder ball is formed on the metal pad. 7. The integrated circuit package as claimed in claim 1, wherein the light-incident surface of the integrated circuit package is in a direction opposite to the disposed metal plug. 8. A method for manufacturing an integrated circuit package, comprising: providing a transparent substrate having a first surface and a second surface; forming a semiconductor layer on the second surface of the transparent glass substrate; forming a photosensitive element on the semiconductor layer; forming a metal plug on the second surface of the transparent substrate, and electrically connecting the photosensitive element; and Solder balls are formed on the second surface of the transparent substrate and electrically connected to the metal plugs. 9. The method of manufacturing an integrated circuit package as claimed in claim 8, wherein the semiconductor layer is formed by a low temperature chemical vapor deposition method. 10. The method for manufacturing an integrated circuit package as claimed in claim 9, wherein the temperature range for forming the semiconductor layer is between 500°C and 800°C.

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