CN101331395A - Ultrasonic flaw detection system - Google Patents

Abstract

A method and apparatus for effecting ultrasonic inspection of an object processes echo signals received from the object being inspected in at least three signal channels, wherein the echo signals are scaled to different degrees along each channel, increasing and extending the dynamic range of the associated A/D converter system in a manner that eliminates the need to use a large number of analog high-pass and low-pass filters and variable gain amplifiers. This reduces complexity and avoids performance limitations. The digital-to-analog converters sample the input signals of different scales and the selection circuit selects the output of the digital output obtained by the analog-to-digital converter with the highest gain but without overflow. The digital outputs are seamlessly merged to produce an output that can be displayed as a scanned display showing the location of the defect.

Description

Ultrasonic flaw detection system

Cross References to Related Applications

This application claims the benefit of U.S. Provisional Patent Application Serial No. 60/726,798, entitled ULTRASONICFAULT DETECTION SYSTEM USING A HIGH DYNAMIC RANGE ANALOG TODIGITAL CONVERSION SYSTEM, filed October 14, 2005, and filed October 14, 2005 U.S. Provisional Patent Application Serial No. 60/726,776, entitled ULTRASONIC DETECTION MEASUREMENT SYSTEM USING A TUNABLE DIGITAL FILTER WITH 4XINTERPOLATOR, and DIGITAL TIME VARIABLE AMPLIFIERFOR NON-DETRUCTIVER INTERPOLATOR, filed October 14, 2005 Benefit and priority of US Provisional Patent Application Serial No. 60/726,575, the entire disclosure of which is incorporated herein by reference.

Background technique

The present invention relates generally to ultrasonic inspection systems for detecting internal structural defects such as cracks, discontinuities, corrosion or thickness variations in objects or materials, for example in such critical structures as airliner wings. This is accomplished by sending ultrasonic pulses at a target object and analyzing the detected echo signals from that target object. More particularly, the present invention relates to systems and methods for high dynamic range analog-to-digital conversion that may be used in such ultrasonic inspection systems, particularly whereby objects are scanned with ultrasonic probes or transducers. The invention also relates to an eddy current inspection system for detecting internal structural defects.

Ultrasonic flaw detectors in the prior art are exemplified by products such as the instant assignee's Epoch 4Plus product. Competing products available from General Electric are called USM 35X, USN 58L and USN 60 flaw detection systems. In general, prior art ultrasonic flaw detectors utilize a highly complex analog front end comprising many parts that are critical in calibration, reliability, lead time, consistency of results, and optimization for specific applications and settings, etc. There are particularly difficult problems to solve.

A typical prior art ultrasonic flaw detector includes a transducer positioned relative to the object to be inspected and cooperating with a large number of analog circuits such as gain calibrators, preamplifiers and attenuators, variable gain amplifiers, and high-pass and low-pass analog filters that operate over many different frequency bands and require careful calibration and maintenance.

As a result, current flaw detectors present a host of problems for designers and users of such equipment which, due to their complexity, affect their troubleshooting and repair. These issues include issues such as matching the input impedance seen by a varying transducer with different gain amplifiers being switched into and out of the signal path. This has undesired effects on the frequency response and induces various gain nonlinearities. This creates calibration problems when analog circuitry is switched in and out of the signal path.

Another problem with existing flaw detectors can be attributed to their back wall attenuation performance, which affects the ability to detect defects that are very close to the back wall of the object being inspected. This problem poses a particular problem for time-varying gain functions, which in prior art devices have limited gain range and gain rate of change.

Another prior art disadvantage is caused by the way the analog circuits are coupled, which results in each operational amplifier in the signal path having a different DC in order to be able to use the maximum full amplitude scale of this converter Offset error, where in order to maintain the input signal at the midpoint of the ADC, the DC offset error must be zeroed. Also, DC offset errors can cause the waveform presented on the display to not be vertically centered in the waveform portion of the screen, thereby causing undesired anomalies in the waveforms that operators use to analyze and determine the results of their inspections. The error nulling process in the prior art is therefore unreliable, especially at high gains, due to inaccurate DC baseline measurements due to noise.

A further problem arises from the intensive analog implementation of existing flaw detector front-ends due to the need to utilize the entire dynamic range of the instrument used, which creates problems with various gain linearity calibrations.

Prior art ultrasonic inspection equipment is described in US Patent No. 5,671,154, which provides background information for the apparatus and method of the present invention.

Contents of the invention

In general, the object of the present invention is to provide a device and method for ultrasonic object inspection, which avoid or improve the aforementioned disadvantages of the prior art.

It is a further object of the present invention to provide an ultrasonic inspection apparatus and method implemented with simpler circuitry.

It is a further object of the present invention to provide an ultrasonic inspection apparatus and method which requires a shorter and simpler calibration and adjustment procedure before use.

It is a still further object of the present invention to provide an ultrasonic inspection apparatus and method that provides an electronic inspection apparatus and method that delivers more accurate, readable and consistent inspection results.

The foregoing and other objects of the present invention are accomplished by methods and apparatus that extend the dynamic range of A/D converter circuits and eliminate the need for variable gain amplifier (VGA) circuits and their associated complexity and performance limitations.

According to one aspect of the present invention, the apparatus and methods of the present invention are embodied as a plurality of A/D circuits comprising a plurality of channels coupled to receive a single analog input signal, each channel having an analog input signal A device that converts digital signals.

Another aspect of the invention includes means for adjusting the individual sampling times to compensate for all sources of timing skew, including the propagation delay of each preamplifier and those revealed by examining the A/D converter output data. any other sources of skew; means for preventing saturation of the input stage of each channel's preamplifier to prevent signal distortion from affecting inputs to other channels; means for adjusting the frequency response of each channel to substantially match, and means for adjusting the overall frequency response of the device; means for detecting channel overflow in one or more channels of higher gain; and means for combining the plurality of channels into a continuous output stream.

According to another aspect of the invention, the multi-channel converter circuit of the invention comprises means for nulling out offset errors by injecting DC signals from the D/A converter at various points in the analog signal path, whereby A device that removes signal skew errors in each channel.

According to another aspect of the invention, the means for merging a plurality of channels is operable as a function of the result generated by the channel overflow condition detecting means. Also, the means for combining a plurality of channels is operable to output the result of the channel having the lower gain when a channel overflow condition is detected on any channel having the higher gain.

According to another aspect of the invention, means for substantially matching the frequency response of each analog channel is provided for minimizing amplitude matching errors between the channels, particularly at high frequencies.

According to another aspect of the invention, each A/D converter circuit includes means for varying the reference voltage to adjust the full scale range by using a D/A converter. This is used to optimize signal amplitude matching.

According to another aspect of the invention, the plurality of A/D converter circuits of the invention includes means for matching the result of each channel to a different gain.

According to another aspect of the present invention, the plurality of A/D circuits of the present invention also includes a position for timely adjusting the sampling clock of one channel relative to the rising edge of other channel clock circuit parts so that the sampling times of each channel are adjusted , the means to compensate for the propagation delay of each preamplifier channel and any other sources of skew revealed by examining the A/D converter output data.

According to another aspect of the present invention, the channel overflow condition detection means further comprises a means for ensuring that all amplifiers in the signal path from the first amplifier to the amplifiers inside the A/D converter have sufficient time to return to the linear region of their operation, A device that extends the duration of the overflow signal from the A/D converter.

According to yet another aspect of the invention, the means for combining a plurality of channels further comprises means for adjusting, for example scaling, the data bit position of the result of one or more channels with lower gain to match one or more channels with higher gain Means for multiple channel results. This can be done eg by shifting using shift registers, multiplexers etc. or by any means.

According to a further aspect of the present invention, there is provided a method for converting an analog signal to a digital signal comprising, for example, splitting an input analog signal into larger and smaller signal paths; scaling the input signal on the larger and smaller signal paths , so that the smaller signal channel has a higher resolution than the larger signal channel; utilize separate A/D converters to sample the larger and smaller signal channels; and output the result of one of the larger and smaller signal channels, As a function of determining whether the larger signal channel is valid.

The method of the present invention also includes merging the result of the larger signal channel and the result of the smaller signal channel to obtain a combined result; and outputting the combined result.

Other features and advantages of the present invention will become apparent from the following description of the invention with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a block diagram of a basic configuration of an ultrasonic inspection apparatus.

FIG. 2 is a basic waveform diagram for the device shown in FIG. 1. FIG.

Fig. 3 is a waveform diagram showing the characteristics of the falling edge of an ultrasonic pulse.

Fig. 4 is a block diagram providing a side-by-side comparison of a waveform display and the location of a defect in a target object.

FIG. 5 is a continuation of FIG. 4 .

Fig. 6 shows a circuit block diagram of an ultrasonic inspection device in the prior art.

Fig. 7 is a circuit diagram of a digitally dense implementation of an ultrasonic inspection apparatus according to the present invention.

8a and 8b are another block diagram of another implementation of the present invention.

Figure 8c corresponds to Figure 8b, but includes purely digital DC offset compensation.

Figures 8d and 8e correspond to Figure 8b, but with amplitude comparators instead of overflow indicators, Figure 8e adds digital baseline correction.

Figures 8f and 8g correspond to Figure 8b, but with baseline correction added in each channel.

Fig. 8h corresponds to Fig. 8b, but includes a delay circuit for handling fast slewing input signals.

FIG. 9 shows a block circuit diagram for an alternative embodiment of the front end portion depicted in FIG. 7 .

Figure 10 is a signal diagram used to explain certain concepts applicable to the operation of the circuits in Figures 8d, 8e and 8h.

Figure 11 is a block diagram of the hybrid circuit associated with Figure 8d.

Detailed ways

Referring initially to Figures 1 and 2, background information on the general environment and the various problems addressed by the present invention is provided.

In FIG. 1, an ultrasonic transmitter-receiver unit 10 transmits an ultrasonic wave to a probe or transducer 12 coupled to a target object 14 such as steel material, directly or through a delay material such as water or quartz, during a predetermined period. Electrical pulse signal 10a. As shown in FIG. 2 , the probe 12 converts the trigger pulse signal 12a into an ultrasonic pulse 10a that is transmitted through the target object 14 . Ultrasonic pulses 10 a applied to the target object 14 are then reflected by the bottom surface 14 a of the target object 14 and received by the probe 12 . The probe 12 converts the reflected wave into an electrical signal, which is supplied to the ultrasonic transmitting-receiving unit 10 as an electrical echo signal 10b. The ultrasonic transmitting-receiving unit 10 amplifies the electrical signal 10 b and transmits the amplified signal 11 as an echo signal 11 to the signal processing device 16 . As used herein, the term probe or transducer includes implementations in which the transducer is implemented using different transmitters and receivers.

The echo signal 11 includes a bottom surface echo 11 a corresponding to a wave reflected by the bottom surface 14 a, and a defect echo 11 b caused by a defect 14 b in the object 14 . Additionally, the frequency of the ultrasound echo pulses 11 is primarily determined by the thickness or other characteristics of the ultrasound oscillator incorporated in the probe 12 . The frequency of the ultrasonic pulse 10a used for inspection is set to several tens of KHz to several tens of MHz. Therefore, the signal waveform frequency range of the bottom surface echo 11a and the defect echo 11b included in the echo signal 11 covers a wide range from about 50 KHz to several tens of MHz.

The signal processing device 16 performs various signal processing on the echo signal 11 received from the ultrasonic transmitting-receiving unit 10, and the signal processing device 16 displays on the display unit 18 the 14 Thickness output results. In order to signal-process the echo signal 11 and display the echo signal, a trigger signal S synchronized with the pulse signal 10 a is supplied from the ultrasound transmitter-receiver unit 10 to the signal processing device 16 .

In the defect inspection apparatus arranged as described above, the echo signal 11 output from the ultrasonic transmitting-receiving unit 10 includes a certain amount of noise in addition to the bottom surface echo 11a and the defect echo 11b. When the amount of noise included in the ultrasound pulse 11 is large, the reliability of the inspection result is greatly reduced. Noise is roughly divided into electrical noise and material noise.

The electrical noise includes external noise caused by mixing electromagnetic or static waves into the probe 12, the ultrasonic wave transmitting-receiving unit 10, a connecting cable such as the cable 13, etc., and generated by an amplifier incorporated in the ultrasonic wave transmitting-receiving unit 10, etc. internal noise.

Reducing noise included in the echo signal 11 is very important for performing ultrasonography with high accuracy. Typically, an analog filter is used to reduce noise components included in the echo signal 11 . For example, a BPF (Band Pass Filter) is used to pass a frequency component of an ultrasonic echo with respect to electrical noise having a wide frequency component. Also, LPF (Low Pass Filter) or BPF is used for material noise, recognizing that the frequency distribution of the defect echo 11b (Fig. 2) is lower than that of the echo produced by signal scattering. In this way, when the analog filter is used, the noise component included in the echo signal 11b can be reduced to a level equal to or lower than a predetermined level.

It is generally known that the frequency distribution of the defect echo signal varies based on the ultrasonic attenuation characteristics of the target object 14 . Therefore, when the BPF is to be used for material noise represented by scattered echoes or the like, a filter having optimal characteristics is desirably used according to the target object 14 . However, since the frequency pass characteristics of analog filters cannot be easily changed, a greater number of filters having different frequency pass characteristics corresponding to the various materials associated with the target object 14 must be prepared. Different ultrasonic attenuation characteristics. In this way, when different filters are used depending on the material characteristics of the target object 14, practical difficulties arise when considering the operability or economic advantages relative to the cost and complexity of the overall system.

In some cases, the defect echo 11b may be very close to the front surface 14c of the target object 14, which would place it immediately on the falling edge of the transmit pulse 10a. For this reason, it is desirable that the end of the falling edge of the transmit pulse 10a (exaggerated as falling edge 10at in FIG. 3 ) sink as quickly as possible to the zero baseline 10ab in order not to interfere with the returning defect echo 11b. The settling time 7a to zero baseline is the decisive factor for the near-surface resolution of the flaw detector.

Considering that the gain of the ultrasonic transmitting-receiving unit 10 can be adjusted up to 110dB (as required by the European standard EN 12668-1), if the gain level is set too high, the gain amplification stage before the ultrasonic transmitting-receiving unit 10 A small amount of baseline error will result in a large error at the output of the gain stage.

The resulting baseline error at the input to the signal processing means 16 will be:

or

(b) If high enough in amplitude, it causes one or more of the gain amplification stages to saturate, thereby preventing the echo signal from being detected at all.

Typically, the baseline error problem described above is addressed in one of two ways. According to a first method, an HPF is used in the signal path at the input of the ultrasound transmitter-receiver unit 10 in order to filter out the low-frequency content of the falling edge 10at of the transmission pulse 10a. The falling edge 10at of the transmit pulse 10a can be improved by the HPT as shown adjacent to the dashed line 7c.

However, the effectiveness of HPF solutions is limited in several ways. First, the HPF cutoff frequency (fHPF-3dB) must be as high as possible in order to minimize the low frequency content of the falling edge 10at of the transmit pulse 10a. For example, if the excitation frequency of the probe 12 is 10 MHz and fHPF-3dB is 5 MHz, the undesired effect on the receiver baseline will be greatly reduced.

Unfortunately, it is not unusual to use excitation frequencies as low as 500kHz for probe 12, which would require fHPF-3dB to be below 500kHz. The HPF solution loses much of its effectiveness in this frequency range because the undesirably large amount of transmit pulse 10a falling edge 10at low frequency content is allowed to pass through the HPF and introduce baseline errors.

Second, in order to prevent damage to the amplifier circuit, the maximum amplitude of the transmit pulse applied to the first amplifier stage (not shown) of the ultrasonic transmit-receive unit 10 is limited (clamped) to a few volts. It is common to operate the gain of the ultrasound transmit-receive unit 10 at a level which would cause the amplifier to saturate each time the pulser is fired. If the filter is not critically damped, the filter response after coming out of saturation will make the falling edge of the transmit pulse 10a worse than if no filtering was used. It is possible to have a large number of tuned filters for each instrument manufactured to ensure critical damping; however, practical difficulties arise when manufacturability and temperature drift of the filter components are considered.

It should also be noted that once an amplifier goes into saturation, it will take a significant amount of time for the amplifier to return to the region of linear operation. This results in it taking more time to return the falling edge of transmit pulse 10a to the zero baseline than it would if the amplifier input signal were held below the saturation level (ie within the linear operating range).

An alternative method for solving the baseline error problem is to couple the clamped transmit pulse 10 a directly to the input of the ultrasound transmit-receive unit 10 . This approach avoids one of the above-mentioned problems because no HPF or BPF filters are used.

The effectiveness of direct-coupled solutions is limited in two ways. Firstly, it is not useful for reducing the low frequency content of the falling edge 10at of the transmit pulse 10a. Secondly, the DC component of the baseline error and the amplifier offset error of the ultrasound transmitter-receiver unit 10 pass through the signal path and are amplified. This leads to various dynamic range and saturation issues described further on.

Typically, flaw detectors are provided that allow the user to operate the instrument with filters or by direct coupling in order to select the optimal settings for the flaw measurement situation.

The detection of defects near the back surface of the object 14 will now be described with reference to FIG. 4 . In some cases, the defect 14d may be very close to the far surface 14a of the target object 14, which will cause the defect echo 11b to be in close proximity to the back wall echo 11a. For a proper inspection (according to many formal inspection procedures), the peak of the back wall echo 11a must remain visible on the waveform display 18 at all times. The reasons for this are: 1) A small defect 2d in the target object 14 caused by porosity or material contamination will produce a defect echo which is not large enough to be seen on the waveform display 18, but will be reduced the amplitude of the echo reaching the rear wall 14a, thereby reducing the amplitude of the defect echo 11b and the rear wall echo 11a, and 2) the probe 12 will be intermittently coupled incorrectly to the surface 14c of the target object 14, This reduces the amplitude of the rear wall echo 11a. Both of these conditions will render the echo from defect 14d not visible on waveform display 18 . However, a reduction in the back wall echo 11a will indicate a problem with the target object 14 material or probe 12 coupling. If the peak of the back wall echo 11a were allowed to exceed the top visible portion of the waveform display 18, the reduction in peak amplitude would not be visible on the waveform display 18. The person performing the examination establishes the detection parameters of the posterior wall echo 11a by adjusting the posterior wall echo gate 6d (see FIG. 4 ) to set the area on the horizontal time axis in which the posterior wall echo 11a is allowed. The threshold on the vertical amplitude axis is also set for the minimum acceptable echo amplitude. Typically, an alarm will occur when the back wall echo 11a falls outside these parameters.

This method of measurement poses some problems.

The echo amplitude difference between the flaw echo 11b and the back wall echo 11a can be huge (up to several orders of magnitude). However several methods (a, b, c and d) described below can be used to ensure that the peaks of both the defect echo 11b and the back wall echo 11a remain visible on the waveform display 18:

(a) Connect probe 12 to two parallel receiver and A/D converter channels (A and B). The gain of channel A is adjusted by the person performing the inspection to optimize the amplitude of the echo from defect 14d so that it can be clearly seen on waveform display 18 . The gain of channel B is adjusted to ensure that the peak of the rear wall 11a echo remains visible on the waveform display 18 for reasons previously described.

The digital outputs of channel A and the BA/D converter are combined in such a way that the full horizontal time scale of the waveform display 18 shows the full output of channel A except for the area of the rear wall echo gate 6d. The far left of the rear wall echo gate 6d indicates the point in time at which switching from channel A to channel B occurs.

Unfortunately, this two-pass approach has drawbacks. Typically, inspection is accomplished by moving probe 12 in a scanning motion along the surface of target object 14, since the presence or location of defects within the object is not known until they are detected. If the target object does not have a constant thickness between the front surface 14c and the rear surface 14a in the scanning area, then in order not to miss the detection of the rear wall echo 11a, the rear wall echo gate 6d will need to be adjusted wide enough so that Variations in this thickness are included.

Therefore, if the near rear wall defect echo 11b is very close to the rear surface 14a, it will not be detected because the rear wall defect echo 11b will occur in the region of the rear wall echo gate 6d. This causes the far surface 14a to have an undesired effect on the near surface resolution. Also, the amount of receiver hardware is nearly double that required for a single channel solution.

(b) The two consecutive pulse receiver measurement cycles approach is similar in concept to the two parallel receiver and A/D converter channel approach, except that only one channel is required. The description in part (a) above applies to the method of two consecutive pulse reception measurement cycles. Also, instead of processing the defect echo 11b and the back wall echo 11a in two parallel channels set to different gains, the echoes are processed in the same channel, one pulse reception cycle followed by another pulse reception cycle, but Each loop has a different gain.

A particular disadvantage of the continuous pulse acquisition measurement cycle method is that the defect echo 11b is separated in time from the rear wall echo 11a by an additional pulse interval To (see FIG. 2 ). Therefore, measurement errors are more likely to occur when the probe 12 is moved, since its position may change between the time the flaw echo 11b and the back wall echo 11a are measured.

(c) Time-Varying Gain (TVG) is a single-channel scheme in which the amplifier gain of the ultrasonic transmit-receive unit 10 is dynamically changed to optimize the amplitudes of the defect echo 11b and the back wall echo 11a (for reasons already described) .

As with the two parallel receiver and A/D converter channel approach, the TVG approach has the same disadvantages for near surface resolution caused by the far surface 14a.

But there are other disadvantages associated with the TVG method. Figure 5 thus shows an ideal TVG curve 6e that changes instantaneously from gain 6f to gain 6h, thereby not introducing additional near-surface resolution errors from the analog TVG amplifier. Errors associated with measuring defects close to the rear wall of a target object having a non-constant thickness will still remain, as described in the above method.

Unfortunately, it is impossible to achieve the ideal curve 6e (especially the instantaneous slope 6g) with an analog TVG amplifier. The analog TVG amplifiers and the external signals that control them have response times that limit the rate of gain change 6g, thereby causing undesired effects on the near surface resolution brought by the far surface 14a. Since the defect 14d has to be far away from the backside 14c of the target object 14 in order to provide a time interval of 6m for the gain change, the near surface resolution is reduced. In terms of echoes, the defect echo 11b must occur before the start of the time interval 6m, whereas the rear wall echo 11a must not occur before the end of the time interval 6m.

Other problems associated with the TVG method are caused by various sources of DC offset error in the receiver portion of the ultrasound transmit-receive unit 10 . These sources include the amplifier IC's input DC offset error and the DC component of the baseline error.

The DC offset error present in certain prior flaw detectors of the present assignee is compensated at each gain setting each time the gain is adjusted from one level to the next. The DC offset error is compensated in this way to account for effects of temperature, long-term stability, drift on the DC offset error, and the like. The compensation method utilizes several D/A converters along the receiver signal path to inject a DC null signal that will ensure that the baseline remains centered on the full scale range of the A/D converters , and in the optimal position on the waveform display 18. Every time the instrument is turned on, or the gain setting is changed, an algorithm runs in the microprocessor that performs a baseline error reading, calculates the required DC error correction value, and sets the DAC to that value.

At the speed the TVG needs to run, it is impractical to perform the above DC offset compensation method for every gain setting. Conversely, the DC offset correction is set for the midpoint gain, thereby dividing the error between the endpoints. For example, if the TVG range is set to operate between 20 and 60dB, the DC offset correction is set to compensate for errors at 40dB. The problem with this technique is that it introduces errors into the echo amplitudes, which is undesirable for accurate flaw detection and dimensional measurement.

(d) A logarithmic amplifier is used to cover the huge dynamic range required and the echoes are displayed on the waveform display 18 on a logarithmic scale. The logarithmic scale provides a very high dynamic range, thus making the peaks of both low amplitude defect echoes and much higher amplitude rear wall echoes visible on the waveform display.

Unfortunately, certain undesired consequences occur when using logarithmic methods. Thus, for a given back wall echo amplitude and amplitude variation, the vertical variation of the echo waveform peak is less noticeable on the waveform display than for a receiver using a linear amplifier. This makes it more difficult to detect defects by observing the peak amplitude variation of the back wall echo as described above.

Also, the output of the log amp can only provide the corrected waveform. Therefore, the position of the negative echo lobe cannot be identified because it is either removed by half-wave correction or converted to a positive lobe by full-wave correction. The precise location of the positive and negative echo lobes is very important to accurately measure the thickness of the target object 14, since one lobe may be more visible than the other. The polarity of the echo lobes is also needed to determine when echo phase reversal occurs. Phase inversion of ultrasonic echoes occurs when sound waves pass from a low acoustic impedance material to a high acoustic impedance material.

Also, all filters must be positioned before the log amp section, since the filters require a linear signal to operate correctly (log amps are non-linear devices). If the filter circuit is positioned before the high-gain log amp section, the receiver will be much more sensitive to noise because the PCB traces needed to connect the filter components together are sensitive to electromagnetic Noise sensitive, and the internal noise generated by the filter amplifier will be the most amplified. These problems with logarithmic amplifiers are ameliorated in the present invention because the full dynamic range of the sampled data is provided on each sample clock cycle, thereby allowing it to be presented as a linear or logarithmic scale. Thus, the present invention enables an operator to command a system, such as the FPGA described above, to select and develop linear or logarithmic system outputs for display on display 18, or to store these outputs for later analysis.

The present invention aims to improve or avoid the disadvantages of the prior art, in fact, it is basically equivalent to a 100MHz 24-bit A/D converter, which operates with a large input voltage, without DC offset, baseline errors and other disadvantages of the prior art. It is important to note the fact that although the present invention is implemented with the performance of an A/D converter substantially equivalent to 100MHz 24-bit, it can also be used with sampling frequencies other than 100MHz and 24-bit, respectively, as described above and resolution to achieve. It utilizes three (or more) A/D converters operating in a corresponding number of channels. The present inventors realized that the eventual development of multi-function operating A/D converters would allow the use of a smaller number of A/D converters.

The block diagram in Figure 6 shows a more detailed form of prior art circuitry that has been used to implement an ultrasonic inspection system. This dense analog circuit takes the signal from the transducer 12 and feeds it through a switch 24 as an optional input to a series of amplifier/attenuators 28, 30, 32, 34 and 36 provided in parallel, which The attenuators have respective gains of 14dB, 0dB, -8dB, -14dB, and -20dB. Switch 24 also receives the input of gain calibrator 20 and provides its signal directly to attenuators 32 , 34 and 36 and via switch 26 to amplifiers 28 and 30 .

Variable gain amplifiers (VGAs) 40, 42 and 44 receive their inputs respectively from amplifiers 28, 30 and switch 29 which provides an output 31 which constitutes a selected one of the outputs of attenuators 32, 34 and 36. The output of the VGA is provided to a switch 46 which also receives the signals from the gain calibrator 22 as one of its inputs and selectively provides these signals via a bus 48 to a series of high pass filters 50, 52, 54, 56 , 58 , 60 , 62 and 64 , whose outputs are switched to low pass filters 70 , 72 , 74 , 76 , 78 , 80 , 82 and 84 through switch network 66 . Thus, by controlling the selection of the desired signal through the switches 66 and 67, the signal from the VGA 40, 42 and 44 or from the gain calibrator 22 can be fed to provide it to the further downstream VGA 86, the VGA 86's The output is further provided to amplifier 90 via switch 92 .

The output of the amplifier 90 or the output of the gain calibrator 94 is then finally fed to a 100 MHz 10-bit analog-to-digital (A/D) converter 100 .

Field Programmable Gate Array (FPGA) 106 will combine real-time sampled data control and storage circuitry 102 with measured gain detection and compression circuitry 104 to provide an output to digital signal processor and control 110, which also controls the settings of FPGA 106 to obtain Properly processing the output of the analog-to-digital converter 100 provides time-varying gain control and produces a signal that can be displayed on the display 18 .

Given the introductory discussion, it is evident that various analog circuits are calibrated to prevent inconsistencies and variations in the different spectral responses due to a large number of high-pass and low-pass filters, and to avoid DC offsets and drifts and analog device temperature effects The task of posing a number of challenges to designers and users of circuits in the prior art.

A cursory comparison of the block diagram of the present invention shown in FIG. 7 shows that very little use of problematic analog circuitry is used in the present invention, which utilizes triplets of A/D channels, thus avoiding many of the disadvantages and complications of the prior art. Spend.

In the block diagram of FIG. 7 , when switch 114 a is closed, transducer 12 has its output 13 a provided directly to only two preamplifiers 110 and 112 , which feed third amplifier 122 . The signals of these amplifiers are processed in frequency response trimming and filter blocks 116, 118 and 120 respectively and then provided to differential amplifier drivers 126, 128 and 130 along three channels A, B, C. The analog signals along these three paths are then provided directly to A/D converters 132, 134 and 136, respectively, whose digital outputs are then provided in turn to field programmable gate array 140, which incorporates Control and storage module 142 , time-varying gain 146 and measurement gate detection and synthesis A-scan compression circuit 152 . The FPGA 140 works in conjunction with a DSP 160 which provides its signals to the display 18.

The implementation in Figure 7 (whose function and features are discussed in detail below in the description of Figures 8a and 8b) eliminates most of the analog circuitry and overcomes the shortcomings of the prior art, including the intensive use of Filters, additional amplifiers and calibrators and various VGA circuits, all appear unnecessary according to the circuits of Figures 7, 8a and 8b.

Thus, as further shown in Figures 8a and 8b, the present invention is an apparatus and method for extending the dynamic range of A/D converter circuits used in flaw detectors, thickness or corrosion measuring instruments, which eliminates the need for variable gain amplifiers (VGA) and its associated complexity and performance constraints. The apparatus and method of the present invention utilize three A/D converters that sample three differently scaled versions of the same input signal on different channels. The number of samples per channel is adjusted to compensate for the propagation delay of each preamplifier channel, minimizing the signal skew error between the output of each A/D converter sampled data. The scale is such that the maximum gain channel (C) has 32 times higher resolution than the medium gain channel (B) and 1024 times higher resolution than the minimum gain channel (A). The higher resolution channels are monitored for data overflow, and the channel with the highest resolution data without overflow is selected as output. Selected outputs are merged to produce a seamless output data stream. The resulting output is a data stream whose quantization step size is larger for large signals and 32 or 1024 times smaller for small signals. The level of dynamic range provided by the present invention thus eliminates the traditional VGA implementation of controlling the analog input signal level to maintain the peak voltage level of the analog input signal at or near the full scale value input to the A/D converter.

When sampling with the circuit shown in Figures 8a and 8b, the input signal from the transducer 12 is split into two channels 19a and 19b, with respective buffers dedicated to each respective channel. Thus, each buffer amplifier 110 and 112 amplifies the input signal 13a on its respective channel with a gain of 0.1 (-20 dB) and a gain of 3.2 (10.1 dB), respectively. The output of buffer amplifier 112 is connected to the input of buffer amplifier 122 to produce a third channel with a gain of 102.4 (40.2 dB). Each channel is sampled by one of three substantially identical A/D converters 132 , 134 and 136 . The three channels A, B, C are sampled with a time delay between them to compensate for input signal skew errors caused by propagation delays of all amplifiers in the analog signal path. The time delays are controlled by the rising edges of the clocks CLKA, CLKB, CLKC driving the A/D converters, which are adjusted with a calibration algorithm.

In an embodiment that has been reduced to implementation, the sample timing adjustment is broken into two parts.

A) Coarse tuning: Data is delayed by a selectable integer number of clock cycles using a FIFO and control circuitry for each A/D channel.

B) Fine Tuning: There are four Phase Locked Loops (PLLs) running at 0, 90, 180, 270 phase angles relative to the clock. The clock timing of each A/D can be adjusted in steps of 1/4 clock cycle by independently selecting the PLL output for each A/D.

If the conversion data for the maximum gain channel (C) is valid, its result is passed unmodified as output 132OUT of the three-channel A/D converter circuit (Fig. 8b). If the converted data result of the maximum gain channel (C) overflows, its result is discarded, and if the converted data result of the medium gain channel (B) does not overflow, it is passed, scaled to correct for buffer amplifier 112 gain and is Used as output 134OUT. If the converted data for the middle gain channel (B) overflows, its result is also discarded, while the converted data result for the smallest gain channel is scaled to correct for signal path gain. The scaling gain is calculated as:

Gain of buffer amplifier 112 + gain of buffer amplifier 122 - gain of buffer amplifier 110, which is then used as output 136OUT.

In the embodiment shown in Figures 8a and 8b, the three-channel A/D converter circuit of the present invention is capable of: canceling signal offset errors in all three separate channels; by using three separate channels each set to a different gain buffer amplifier channel to scale the input signal; converts the analog signal input for each of the three discrete channels to digital at a respective sampling number adjustable to compensate for input signal skew errors; at least with higher gain Detect channel overflow conditions in the channel; and combine the A/D converter output of the three channels in real time.

As mentioned above, the analog input signal 13a from the transducer 12 is directed to two signal clamping amplifier channels, wherein the gain of the second amplifier 112 of the two amplifier channels is predetermined greater than the gain of the first channel 110 factor. The output of channel B amplifier 112 is connected to downstream filter 118 and amplifier 122 with a gain of 32 to generate channel C. For example, channel A has a gain of 0.1, channel B has a gain of 3.2, and channel C has a gain of 102.4. Thus, channels A and B differ by a gain factor of 32, channels C and B differ by a gain factor of 32, and channels A and C differ by a gain factor of 1024 compared to each other.

The clamp voltage thresholds for amplifiers 110 and 112 are set to levels such that the resulting output is slightly outside the effective input range of A/D converters 132, 134 and 136 for each channel A, B and C. Clamp circuits 111a, 111b and 113 also limit the input voltage to the gain channel amplifiers to prevent them from going into saturation.

It is important to prevent the amplifier from saturating, because once in saturation, the amplifier takes a lot of time to return to its linear region of operation. By preventing the amplifiers in the gain channel from becoming saturated, the length of time the higher gain A/D converter is in an overflow condition is minimized, thereby allowing higher resolution output data to be used sooner. The clamp circuit in the preamplifier 112 is also used to maintain a constant input impedance for the input signal 19a regardless of the input signal level being higher than the signal level at the maximum input to the channel A preamplifier 110 . If a constant input impedance is not maintained, the input signal will become distorted.

The inventors have realized that amplifier 122 does not require clamp 113 to maintain a constant input impedance to transducer 12 above its signal amplitude operating range because amplifier 122 is isolated from transducer 12 by amplifier 112 . For this reason, other amplifier circuit configurations may be used for amplifier 122 if desired to provide other advantages such as lower power or lower circuit complexity.

In an embodiment that has been scaled down, Channel C amplifier 122 is allowed to saturate and fast recovery OpAmps are used. Preferably, clamping can be added to generate less noise.

The output of each gain channel amplifier 110, 112, 122 is connected to frequency response trimming and filter circuits 116, 118, and 120, respectively. Frequency response adjustment control signals 116a, 118a, 120a are used to match the frequency responses of channels A, B, and C, respectively, as closely as possible. This entails ensuring that all signal frequencies of interest are kept as close as possible to the same gain. A calibration algorithm is used to adjust the frequency response, as described above. This frequency trimming method can be used for two or more ADC channels.

The anti-aliasing filter functions for channels A, B, and C are distributed in frequency response trim & filters 116, 118, and 120 and differential amplifiers 126, 128, and 130, respectively.

The DC offset inherent in each channel's amplifier is compensated by injecting DC signals 112a, 122a, 126a, and 128a to balance DC offset errors present throughout the analog signal path. A calibration algorithm is used to achieve this compensation. It should be noted that this DC offset compensation method has the following two limitations:

1) At very fast pulser/receiver repetition rates ("to" of Figure 2), there is not enough time available between "to" cycles to achieve the required compensation for DC offset drift over time The DC offset correction process. This limits the DC offset calibration to only occur when the instrument is not making measurements.

2) At very high gain settings, small DC offset errors remaining after balance will produce significant shifts in the stored sample data and thus in the waveform displayed on the display.

To further ameliorate the effects of DC offset errors present throughout the analog signal path, including those described in items 1 and 2 above, this embodiment includes a purely digital DC offset compensation method, shown in Figure 8c its block diagram.

With further reference to FIG. 8c, the output of A/D converter 136 is provided to baseline capture module 146 during interval 10c shown in FIG. Sample points from interval 10c are used to monitor the baseline because they are in a relatively "quiet" region of time, ie, the region that occurs before the pulser fires and after the ultrasonic response signal of substantial magnitude will occur. In this embodiment, the baseline capture module 146 utilizes 256 signed integer sampling points and calculates the average; however, a different number of sampling points may be used. When multiplexer 147 is enabled via control signal 149 to allow the integer output of signed baseline capture module 146 to pass baseline corrector module 148, signal 147a is subtracted from signed integer signal 145a to remove baseline errors. Register 150 is intended to allow selectable baseline compensation values to be used, which may have been generated by software algorithms or by hardware means not shown.

The three-channel A/D converters 132, 134, and 136 are 14-bit high-speed converters, and sampling clocks are provided to them with sampling clocks CLKA, CLKB, and CLKC using respective Delay control element, derived from 100MHz oscillator module 131. The delay control element enables timely adjustment of the position of the rising edge of one channel's sampling clock relative to the other channel's clock circuit section so that the number of samples per channel is adjusted to compensate for the propagation delay of each preamplifier channel and by checking the A/ Any other sources of skew revealed by the output data from the D-converter. A calibration algorithm is used to achieve this compensation.

As mentioned earlier, in the embodiment that has been reduced to implementation, the sample timing adjustment is split into two parts.

1) Coarse tuning: Data is delayed by a selectable integer number of clock cycles using a FIFO and control circuitry for each A/D channel.

2) Fine Tuning: There are four Phase Locked Loops (PLLs) running at 0, 90, 180, 270 phase angles relative to the clock. The clock timing of each A/D can be adjusted in steps of 1/4 clock cycle by independently selecting the PLL output for each A/D.

The inventors consider an alternative method of adjusting sample data timing by using fine analog adjustments as described above in combination with coarse digital adjustments. An adjustable signal delay element would be used to adjust the timing of the analog signal instead of the digital clock timing adjustment method described above. This analog signal delay can be accomplished using any of the following methods.

1) A delay line with taps selected by switches for adjusting the delay.

2) Delay filter elements, switched in or out of the signal path as required.

3) An adjustable delay built using variable elements such as an all-pass delay filter using voltage controlled components. Delay can be controlled by the DAC to provide very fine control. The inventors realized that this method provides the best adjustment resolution.

A method of calibrating the system gain by adjusting the full scale range of A/D converters 132, 134 and 136 is also provided. This is done by adjusting the reference voltage (not shown) of each A/D converter with a D/A converter (not shown). Calibration algorithms are used to achieve this functionality.

The digital outputs of A/D converters 132 , 134 and 136 are connected to digital multiplexing circuit 135 . The overflow signals for the two higher gain A/D converters 134 and 136 are connected to channel select logic 137 . Channel select logic circuit 137 also extends the duration of the overflow signal from A/D converters 134 and 136 in order to provide time for all amplifier circuits before A/D converters 134 and 136 inputs come out of saturation. This circuit 137 selects the output data bus from the highest gain channel A/D converter that has not yet overflowed. If all three A/D converter channels overflow, the output data bus of the lowest gain channel A/D converter is selected because it will be the first channel to come out of the overflow condition.

The channel selection logic circuit 137 and the overflow signal from the A/D converter 132 are connected to the index generator circuit 139 . The circuit 139 calculates an index that accompanies the selected A/D converter data in RAM 141. The floating point conversion circuit 143 effectively adds precise bits to the A/D conversion for small signals, while maintaining range capacity for large signals. Floating point converter 143 also reduces the number of bits required for sample data RAM. The sample data RAM has 18 bits, of which 14 bits are used for the mantissa and 4 bits are used for the exponent. When sampled values are stored, the selected A/D converter value is stored in the mantissa, and an exponent value of 0, 5, or 10 is stored in the exponent to indicate the numerical range of the data. The exponent can also be set to 15 to indicate that all channels are in an overflow condition. Also, when data is read from the sample RAM 141, the exponent is used to position the data in the mantissa to construct the 24-bit integer output of the floating point to integer converter 143. This is the final output 145 of the present invention. This output can be represented by the following formula:

Output 145 = 2 ^exponent × mantissa = 24-bit integer

Although the invention has been described with respect to an embodiment utilizing three signal processing channels, each channel in conjunction with its own analog-to-digital converter, the direct inventors have also attempted to use a smaller number of analog-to-digital converters or even a single analog-to-digital converter. number converter. Thus, for example, if an analog-to-digital converter operating at 200 MHz is available, two of the channels can be handled by a single analog-to-digital converter which produces two consecutive fast samples of the same signal point. To this end, a first sample of a signal can be taken, while an amplified version of the same signal is delayed (by an analog delay time) by a time delay approximately equal to the period of the 200MHz analog-to-digital converter clock. The delayed amplified signal is then sampled by the same A/D converter. Also, an analog comparator may be used to compare the signal amplitudes at the output of the preamplifier to determine their amplitude range and control directing the signal to one of the analog-to-digital converters which responds to the signal amplitude difference will overflow.

Also, when three channels are already utilized, for the purpose of increasing the overall dynamic range of the detection system and/or for the use of a given ADC as a temporary replacement for any one that temporarily overflows due to saturation For purposes, the use of four or more channels is also within the concept of the present invention.

With regard to the detailed description of the foregoing extensions to the present invention, one implementation may be in the form of a two-channel system utilizing a pair of 16-bit ultra-fast analog-to-digital converters, the clock speed of which is sufficient for the application of the present invention. Note further that full dynamic range is not always required in every application, eg a particular user may require less than full dynamic range and thus be able to utilize only one of the multiple ADC channels. In a two-channel system where one channel is switched between low gain and high gain, it is possible to provide some of the advantages of a three-channel system utilizing only two channels.

With respect to the aforementioned problem of flaw detection echoes very close to the back wall of the target object, the inventors have realized that this problem can be solved if both channels are stored and a channel change is performed in post-processing. This would be the "tracking rear wall attenuator" solution. It is also possible to use dual or split screen display windows, one for the defect and the other for the rear wall. This will eliminate the need to track the rear wall and adjust the monitor. A small portion of the received signal will be displayed twice - once with high gain in the defect section, and again with low gain in the back wall section. This method can only support defect alarm doors that detect defects very close to the rear wall if the door position is calculated in post-processing.

With respect to the foregoing notion of adjusting channel frequency responses individually to fit the aggregated data stream together without the concept of steps or jumps, it should be noted that this can be achieved by using factory trims or run-time trims. Note further that in a three-channel system, it is sufficient to provide frequency response trimming for only two of the channels.

The invention can also be implemented by extending the duration of the over range indication signal to prevent the output data of the analog-to-digital converter from being selected until its signal path has fully recovered from the saturation condition. This can take one or more of the following forms.

1. In the current embodiment, the time is added from the ADC to the end of the out-of-range indicator bits. This feature is implemented in channel selection logic 137, as shown in Figure 8b. It may include an AND gate receiving the overflow signal as one input and its shifted version as the other.

2. A digital comparator is used on the channel with the next lower gain to detect when the ADC is coming out of severe saturation even though the ADC is still indicating overrange. Adding a delay to this "heavily saturated" detector can be compared to providing a delay on an overrange indicator.

3. The data output from the ADC is compared to the value of the next lower gain channel to verify the data. The value must be within the specified range of values from the next channel.

4. The analog to digital converter is used and its slowness indicates that it has gone out of range.

It should further be noted that the ADC may saturate at input voltages higher than the overrange voltage. This is why it is beneficial to provide a delay out of saturation, whereas a delay out of overrange is not. In the voltage range between overrange and saturation, the ADC can operate without recovery time. In embodiments that have been scaled down, the analog-to-digital converter overrange indicator has been used as a saturation indicator and will sometimes introduce unwanted delays. This unwanted delay is so little that it doesn't make any technical sense.

The inventors also tried to use the ADC to fine-tune the reference voltage of the ADC for the effect of fine-tuning the gain. This method is used to extend the range of user gain control, and this is different from channel matching.

The inventors have also attempted to use preamplifiers for medium and high gain channels that do not distort the source signal. The method preferably builds or utilizes an amplifier with an extremely low noise performance of at least a 20 volt peak output range. The method is also preferred for hybrid designs where the input uses attenuator steps, but this method does not have a large dynamic range. However, for low-cost market segments, a hybrid design would be preferred.

In the foregoing description, reference was made to various technical considerations regarding circuit arrangements becoming saturated or analog-to-digital converters indicating overrange. Following an initial discussion of the problem below, several alternative solutions representing further embodiments of the invention are provided.

Under normal operating conditions, the channel gains for the circuits indicated in parentheses below are applicable.

Channel A gain*32≈Channel B gain [Figure 7]

Channel B gain*32≈Channel C gain [Figure 7]

When a channel is driven into saturation, this will be indicated by the overflow output signal of the channel's analog-to-digital converter, thereby enabling the channel selection logic 137 to select the best channel to receive the signal. As previously described, the best channel is the one with the highest gain and not in an overflow state. The lowest to highest gains are Channel A, Channel B, and Channel C. See Figures 8b, 8c, 8d and 8e.

Any or all of the above is not true for very fast slew rate signals, such as the leading edge of a pulse generator pulse, because the edge is so fast that the amplifiers of all three channels are driven to saturation almost simultaneously.

Due to the slew rate limitations of the amplifiers and filters, the ADC does not saturate immediately, and all three channels move towards saturation at essentially the same rate. If sampling from A/Ds while their outputs are transitioning to their final values, erroneous readings will be noticed. For example, when all three channels are approximately 1/2 full scale (corresponding to the A/D output value (in hexadecimal) 2FFFC), they will not correspond to the correct input amplitude. None of the channel readings indicating overflow will look like this:

Channel A = 2FFF, indicating -5V at the input

Channel B = 2FFF, indicating -0.15V at the input

Channel C = 2FFF, indicating -0.005V at the input

Therefore, the embodiment of Figures 8b and 8c will select channel C since it is the channel with the highest gain and not yet in an overflow state. The above channel reading indicates that channel A is -5V or lower; therefore, a signal of -0.005V (assumed to be at the input of channel C) will be displayed on the display, which will not be correct.

Alternative embodiments need not use overflow output signals from any of the analog-to-digital converters 132, 134 and 136, as shown in Figures 8d and 8e. Instead, magnitude comparators 801, 802 and 803 are used to indicate when the digital output data of each analog-to-digital converter matches a predetermined number, respectively. Amplitude comparators 801 , 802 , and 803 provide output signals to channel selection logic 137 when a predetermined number matches the digital output data of each analog-to-digital converter. The magnitude comparator 801 also supplies its output signal to the exponent generator 139 . It should be noted that the performance of this embodiment can also be achieved by using only amplitude comparators 801 and 802 for channels A and B, respectively.

Due to the fact that the digital output signal of a channel ADC can be correlated to the signal level at any point along the input signal path, the main advantage of the "amplitude comparator" method is that it can be used to Any signal level of interest within the scale, and within its measurement resolution capability. Saturation of an amplifier in the input signal path is an example of a signal level of interest.

Referring to Figure 10, the following logic is true when dealing with very fast signal edges (ie fast slew rates). It should be understood that the values shown below are 14-bit signed integers.

a) If [Channel A >= 100] or [Channel A <= 3EFF], the Channel B and Channel C amplifiers may be over driven.

b) If [Channel B >= 100] or [Channel B <= 3EFF], the Channel C amplifier may be overdriven.

Using logic a) and b) above, the wrong channel selection problem can be prevented by incorporating the following rules into the channel selection logic 137 in the order of precedence shown below:

a) If [Channel A >= 100] or [Channel A <= 3EFF], use data from Channel A, i.e. Channel A has priority over Channel B

b) If [channel B >= 100] or [channel B <= 3EFF], then use data from channel B, i.e. channel B has priority over channel A

c) If [channel A < 100 and > 3EFF] and [channel B < 100 and > 3EFF], use data from channel C, i.e. channel C has priority over channels A and B

It should be noted that the hexadecimal values used above and in Figure 10 were chosen as examples, and this value does not necessarily have to be used in an actual embodiment.

Figure 8d further shows in dashed lines the channel mixer 135' being used as an alternative to the MUX 135. In order to minimize the effect of mismatched signals between channels, a channel mixer 135' is used to mix the outputs of the two A/D converters of the three A/D converters that have the highest gain but are not saturated.

Figure 11 is approximately equivalent to the circuitry and signals contained in channel mixer 135'; however, it only shows part of channels A and B, more output circuitry would need to be added to accommodate the inputs required for RAM 141.

As used herein, "combined" means combined or associated such that separate components or boundaries are not readily distinguishable. Thus, the channel mixer 135' is a device that takes output values from two adjacent A/D converter channels and calculates a compromise value as its output. A ratio control is required to control the ratio of the two inputs used.

Figure 11 shows the details of the ratio control circuit.

In this example, the ratio control value is limited to a range of 0 to 1.

(input A)*ratio+(input B)*(1-ratio)=output

For circuit simplification purposes, ratio control may be further limited to a small set of discrete values that may not include zeros and/or ones. Digital 0s and 1s produce the same output as one or the other input; some other circuitry can handle this case.

A very simple mixer consisting of two adders and three multiplexers can support the following ratio values: 0, 0.25, 0.5, 0.75, and 1. This divides the channel selection irregularly into four separate anomalies; each one is a quarter of the magnitude.

Thus, based on the magnitude of the input signal 19a of FIG. 7, the channel selection logic 137 of FIG. 8d selects the active channel. When the system is used in applications that generate input signal amplitudes that are very close to the threshold that causes the system to switch channels, it can be observed that small jumps or glitches may appear in the output when the system changes channels because the two channels gain, frequency response, and/or phase are not precisely matched. This may manifest itself as an undesired rise or fall in the amplitude of the output signal.

Referring to Figure 8d, the low gain channel is channel A and the high gain channel is channel B. Mixer 1111 (Figure 11 ) measures how close channel B is saturated, depending on the outputs of amplitude comparators 1102 and 1108 (Figure 11 ) included in channel mixer 135&apos; (Figure 8d). As the input signal 19a (FIG. 7) increases, Channel B approaches the saturation and magnitude comparator 1108 preset values. When the latter is reached, the mix function is invoked in the channel mixer 135&apos; which mixes the data from the A/D converter 134 with the data from the A/D converter 132. The mixing function is variable, or has the step of weighting the two data sources from respective A/D converters. When channel B reaches saturation, the mix weight ratio is changed such that a larger weight is applied to channel A and a smaller weight is applied to channel B. As an example: starting with a low input signal 19a (Fig. 7) amplitude, the mix ratio will be 100% for channel B and 0% for channel A; as channel B approaches saturation, the mix will change to 50% for channel B and 50% of channel A; when channel B is saturated, the mix is 100% of channel A and 0% of channel B. The mixing ratio can be extracted by channel A or B or a combination of them. The mixing ratio can be varied in several steps, or adjusted smoothly in proportion to the channel signal amplitude.

The use of the channel mixer 135&apos; makes the input signal 19a (FIG. 7) voltage threshold comparison that separates channel A operation from channel B operation less likely to be observed by the operator. This mix function can be used for all channel transition points. This method can be used in combination with any other method of controlling channel selection.

Figure 8h provides another solution in order to provide an additional clock cycle to the overflow signal to respond to before the output sample data is provided to the MUX 135, which feeds the output sample data and the overflow (OF ) signal with a delay element added. Although not shown, more than one additional clock cycle may be used. The delay prevents the channel selection logic 137 from selecting a channel until the overflow signal has had sufficient time to respond, thereby preventing the problems previously described caused by fast slew rate input signals.

In each channel, overflow and delayed overflow signals are provided to AND gates in order for the overflow signal to:

a) turn on without delay such that it occurs before the time when the analog-to-digital converter output samples are provided to MUX 135, and

b) Closed with a delay in order to synchronize with the delayed sample data provided to the MUX 135 input upon return from the overflow state.

It should be noted that delays other than one clock cycle could also be used with this alternative embodiment.

This method is implemented by inserting a data delay of one sampling clock cycle between each digital signal output of the analog-to-digital converters 132, 134, and 136 and the input of MUX 135. A data delay of 1 sample clock is also inserted between the overflow signal of each ADC and the input of the AND gate. The output of AND gate 809 of channel A is provided to the input of exponent generator 139 . The outputs of AND gates 812 and 815 for channels B and C are provided to channel selection logic 137, respectively.

It should be noted that the performance of this alternative embodiment can also be achieved by utilizing the delays in channels B and C only.

The present inventors also considered a method of making the gain of each channel substantially satisfy a predetermined level by using only a variable gain mechanism in the analog signal path of each channel, such as a variable gain amplifier. The gain level can be set to a predetermined level through a calibration process. The predetermined levels considered for this embodiment are those which ensure that the gain scaling between channels A, B and C is as accurate as possible. There is no drawing associated with this alternative embodiment.

In the foregoing description, reference was made to the baseline corrector 148 shown in Figure 8c. As described below, digital DC offset adjustments can be made on either ADC output, rather than just the mixed output, as shown in Figure 8c. Therefore, referring now to Figures 8e, 8f and 8g, note the following:

a) The Baseline Correction System (BLCS) 804 shown in Figure 8f is the same as items 146 to 150 shown in Figure 8e.

b) Baseline Correction Systems (BLCS) 805, 806 and 807 for channels A, B and C respectively have the same content as BLCS 804. BLCS 805, 806 and 807 are redrawn versions of BLCS 804 and are intended to improve the appearance of Figure 8g.

c) BLCS 805, 806, and 807 are inserted between the digital signal outputs of analog-to-digital converters 132, 134, and 136 and the input of MUX 135, as shown in Figure 8g.

With further reference to FIG. 8g, during interval 10c shown in FIG. Sample points from interval 10c are used to monitor the baseline because they are in a relatively "quiet" region of time - that is, the region that occurs before the pulser fires and after the ultrasonic response signal of substantial magnitude will appear. In this embodiment, BLCS 805, 806, and 807 each utilize 256 sampling points and calculate the average; however, a different number of sampling points may be used. The multiplexers within the BLCS 805, 806 or 807 can be enabled by their respective control signal (ME) to allow the output of each BLCS to be provided to the baseline corrector module input B, as shown in Figure 8f. Input B is then subtracted from the outputs of A/D converters 132, 134 and 136 to remove baseline errors. The registers contained in the BLCS 805, 806 and 807 are intended to allow alternative baseline compensation values to be used, which have been generated by software algorithms or by hardware means not shown.

The inventors have also contemplated an alternative embodiment shown in FIG. 9 and described below which would utilize a gain-reading A/D converter consistent with one or more gain-reading A/D converters and automatic gain control (AGC) circuits. The signal path A/D converter determines and controls the system gain to achieve the advantages of the present invention, especially high dynamic range. Although not shown in FIG. 9 , input signal 10 b of FIG. 1 is connected to input 200 of FIG. 9 .

According to an aspect of an alternative embodiment, the data reconstruction means in the capture logic module 210 is used to calculate the system gain and present the appropriate signal magnitude on a display or provide it as an input to other means. The capture logic module 210 will be positioned within the FPGA 140 of FIG. 7, and the circuits to the left thereof will be substantially replaced with those of FIG. 9. Certain circuitry in FPGA 140 will be modified or removed as appropriate for each alternative embodiment.

According to another aspect of the alternative embodiment, the system gain is calculated for each sample point by using the output value of the signal A/D converter 209 combined with the output values of the gain reading A/D converters 225 and 226 . The sampling rates are substantially the same and synchronized for A/D converters 209 , 225 and 226 . The accuracy of the system gain calculation is basically determined by the accuracy of the gain calibration system, the transfer characteristics of the multiplexer and the accuracy of the aforementioned three A/D converters. The inventors consider that calibration for zero multiplication (explained later) and DC offset nulling may be required for each channel.

As can be further seen in FIG. 9, the circuit of the alternative embodiment includes four parallel input gain channels 201, 205, 207, and 211, the output of each of which is provided to four gain control multipliers 202, 206, respectively. , 208 and 212, the output of which is provided to adder 203 followed by amplifier 204, A/D converter 209, and finally capture logic 210. AGC circuit 227 receives inputs from monitor signals 213, 214, 215 and 216 and provides output gain control signals 217, 218, 219 and 220 to multiplexers 202, 206, 208 and 212, respectively. The inventors have realized that the number of channels may be more or less than four, depending on the dynamic range required for the application to which this alternative embodiment is applied.

Preventing the undesired effects of signal saturation that may occur at different locations in the signal path is a very important aspect of this alternative embodiment. The signal path starts at input 200 and ends at the input of A/D converter 209 . A saturated signal in this embodiment is considered to be any signal in the signal path from the output of the preamplifiers 201, 205, 207 and 211 whose absolute value of amplitude is greater than 1 volt. The following three situations can cause saturated signals to appear in the signal path.

1. The absolute value of the amplitude of the input signal 200 is greater than 10V peak.

2. The amplitude of the input signal 200 is less than or equal to 10 volts peak in absolute value and has sufficient peak value such that the output of the preamplifier 205, 207 or 211 is greater than 1 volt.

3. The absolute value of the amplitude of the input signal 200 is less than or equal to 10V peak, and the sum of the outputs of the multipliers 202, 206, 208 and 212 at the output of the adder 203 is high enough to cause the signal at the input of the A/D converter 209 saturation.

For case 1, the goal of this alternative embodiment is not to prevent signal saturation on the signal path, because many flaw detector inspection procedures require that the pulse generator signal with a peak amplitude much greater than 10V in absolute value always appear on the display; therefore, the pulse The generator signal must be allowed to saturate on the signal path.

For Case 2, this alternative embodiment provides that the saturated output signals of the preamplifiers 205, 207 and 211 are substantially prevented by using the AGC circuit 227 by setting the gain control signals 218, 219 and 220 to substantially zero. by means of gain multipliers 206 , 208 and 212 . The inventors have recognized that commercially available multiplier components do not possess desirable performance characteristics. Thus, multipliers 206, 208, and 212 are not required to provide the infinite attenuation associated with theoretical zero multiplication. Multipliers 206 , 208 and 212 need only provide sufficient attenuation to keep the maximum peak amplitude of the saturated signal below a level that would have an undesired effect on the input signal to A/D converter 209 . The maximum allowed saturation signal level may be established according to recognized industry standards for flaw detection instruments, such as EN12668-1:2000, for example. Note that the outputs of multipliers 206, 208 and 212 are summed; therefore the calculation of the maximum allowable saturated signal level must be considered.

For Case 3, this alternative embodiment provides the use of AGC circuit 227 to ensure that the outputs of multipliers 202, 206, 208, and 212 have sufficiently low amplitudes to prevent signals greater than 1V from being summed by adder 203 at the output. and appear at the input of the A/D converter 209 after being amplified by the +15dB amplifier 204.

According to another aspect of the alternative embodiment, channels A, B, C and D must have substantially equal propagation delays, and a frequency response equal to and including the input of summer 203, in order to prevent distortion at the summing output.

According to another aspect of the alternative embodiment, the gain of each channel is controlled by the multiplier signals Gain A, Gain B, Gain C and Gain D, which are represented in FIG. 9 by items 217, 218, 219 and 220 said. Automatic gain control circuit 227 monitors the output of each gain amplifier using monitor signals 216, 215, 214, and 213, and adjusts the gain accordingly. The gains of the multipliers 202, 206, 208 and 212 are controlled in a manner that provides a smooth transition from one multiplier to the other, thereby preventing sudden gain changes that could cause signal distortion or glitches.

According to another aspect of the alternative embodiment, the preamplifiers 205, 207 or 211, if saturated, are prevented from distorting the input signal 200 by using the clamping circuit described above with respect to the invention of FIG. Each clamp circuit prevents distortion of the input signal 200 by maintaining a constant input impedance for the preamplifiers 205 , 207 and 211 .

According to another aspect of the alternative embodiment, A/D converters 225 and 226 sample the summation gain signals provided thereto by adders 223 and 224, respectively. In order to scale them to match the sensitivity of gain signals 218 and 220, each of gain signals 217 and 219 is divided by 10.

According to another aspect of the alternative embodiment, when the amplitude of the signal at input 200 approaches zero, the amplitudes of gain monitor signals 213, 214, 215, and 216 will also approach zero, thereby causing automatic gain control circuit 227 to set the gain Signals 217, 218, 219 and 220 increase to their maximum gain value of 1 volt. As the signal amplitude at input 200 increases, the multiplier with a non-zero gain multiplier is gradually changed in order to provide a smooth gain transition between channels before reaching a saturation condition. When the amplitude of the input 200 is such that the D_Monitor signal 213 reaches a predetermined amplitude just below saturation, the automatic gain control circuit 227 reduces the gain D 220 to zero to prevent the saturated signal from passing through the channel D multiplier 212 when this occurs and result in a substantially saturated signal. When gain D is set to zero, input 200 will pass through channels A, B, and C until C_Monitor signal 213 reaches a predetermined magnitude just below saturation, thereby causing the automatic gain control process described above for channel D to begin for channel C. As the signal amplitude at input 200 continues to increase, this process is performed for channel B, then channel A, eventually preventing a substantially saturated signal from passing through channels B, C and D.

The response time of the AGC circuit 227 establishes the maximum acceptable time rate of change of the input signal 200 because the gain adjustment must occur before the moment when the input signal 200 reaches a magnitude that would cause an unacceptable signal to occur. If the alternative embodiment must operate with signals whose rate of change in time is faster than the response time of AGC circuit 227, between the outputs of preamplifiers 201, 205, 207, and 211 and the inputs of multipliers 202, 206, 208, and 212 Introduce a delay circuit. Monitor signals 216, 215, 214 and 213 are respectively connected to the input of each delay circuit. The delay circuit provides a time delay that is greater than the AGC circuit 227 response time. In order not to distort the signal to unacceptable levels, the relative propagation delay and frequency response errors between the delay circuits of each channel must be minimal.

The inventors have realized that the objects of the alternative embodiments may be achieved by the control parameters and sequences for the automatic gain control circuit 227 in other ways than those described in the above embodiments. And, the inventors have realized that these other embodiments can accomplish substantially the same end result with respect to gain control.

Throughout the specification and claims, reference is made to "echo" signals. As will be appreciated by those skilled in the art, in certain circumstances or applications, the transmitter and receiver components of transducer 12 are physically separated and the receiver is positioned opposite the object being detected. Accordingly, the term "echo" as used herein also relates to and includes embodiments in which the so-called echo signal passes through the object being detected.

In the foregoing description, the invention has been specifically described with respect to embodiments in which flaw detection is performed using a single transducer of a transmitter/receiver pair operating exclusively on the echo principle and/or with reference to ultrasonic waves passing through the material. device components operate. It should be noted, however, that the invention is equally applicable to flaw detection instruments utilizing arrays of transducer elements, such as ultrasonic phased array probes. In the case of single-element ultrasound transducers, the response signal for each transducer element of the phased array ultrasound probe for reception is provided to the input of the receiver channel for use by an analog-to-digital converter Conditioning and subsequent digitization. In other words, references (in the singular) to "transducer" in the claims are considered to also belong to the ultrasonic phased array type of probe. Such transducer arrays are considered identical, or at least equivalent, to single element transducers. The structure of such ultrasonic phased array devices is described or referenced in US Patent Nos. 4,497,210 and 6,789,427, the contents of which are incorporated herein by reference.

While the invention has been described with respect to specific embodiments thereof, it is evident that many other variations and modifications, as well as other uses, will be apparent to those skilled in the art. Accordingly, it is preferred that the invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims (65)

1. An object inspection system comprising: The transmitting and receiving part is used to generate the detection signal and receive the corresponding echo signal; The transducer is used to convert the detection signal into an ultrasonic signal, apply the ultrasonic signal to the target object to be detected, receive the ultrasonic echo signal, and generate the echo signal for the transmitting and receiving parts; A signal processing circuit coupled with the transmitting and receiving part, for receiving and processing the echo signal, the signal processing circuit includes at least three signal processing channels, each channel scales the echo signal to a different degree, and each channel has its own an analog-to-digital converter; and A selection circuit selects the output of the analog-to-digital converter that provides the maximum increase in echo signal without overflow. 2. The system of claim 1, comprising a display for displaying the scan signal generated by the signal processing circuit and representing the echo signal. 3. The system of claim 1, further comprising respective frequency filters in at least one of the signal paths. 4. The system of claim 1, further comprising respective frequency trimming circuits for at least one of said signal processing channels, the respective frequency trimming circuits matching the frequency responses of the filters to each other. 5. The system of claim 1 , comprising at least first, second and third signal paths, said paths respectively comprising first, second and third preamplifiers, said preamplifiers respectively providing echo 1st, 2nd and 3rd scaled output of the signal. 6. The system of claim 5, wherein the output of the second preamplifier is provided as the input of the third preamplifier. 7. The system of claim 5, wherein a respective DC offset adjustment circuit is in at least one of the signal processing channels. 8. The system of claim 5, wherein each channel includes a respective differential amplifier driver. 9. A system according to claim 8, wherein at least one of the amplifier drivers is provided with a DC offset adjustment circuit. 10. The system of claim 5, wherein the outputs of the first, second and third preamplifiers are such that the second output is greater than the first output, and the third output is greater than the second output. 11. The system of claim 5, comprising first, second and third analog-to-digital converters, each analog-to-digital converter having a respective clock input utilizing a phase adjustment between its clock edges activated Instead, they are synchronized with each other to compensate for signal path delays in each channel. 12. The system of claim 5 including a clamping circuit for the preamplifier. 13. The system of claim 5, wherein each analog-to-digital converter has a respective overflow output, and the selection circuit includes channel selection logic that receives the respective overflow output and selects whether to provide Overflow is the output of the ADC for maximum gain. 14. The system of claim 13, further comprising an exponential generator for scaling the output of the selected analog-to-digital converter output and storing the same output in the random access memory. 15. The system of claim 5, comprising a display. 16. The system of claim 3, wherein the filter is an anti-aliasing filter. 17. The system of claim 5, comprising a DC offset circuit that applies a digital DC offset correction at a signal location after the selection circuit. 18. The system of claim 17, wherein the DC offset circuit comprises a baseline capture circuit coupled to at least one of the first, second and third analog-to-digital converters to generate a correction signal, the baseline capture circuit A baseline corrector capable of subtracting a correction signal from an output signal derived by one of the first, second and third analog-to-digital converters is included. 19. The system of claim 11, comprising a FIFO circuit that enables delaying one clock input relative to other clock inputs by a selectable integer number of clock cycles. 20. The system of claim 5 , comprising an analog signal delay module effective to delay output from the first, second, and third preamplifiers in a manner that enables synchronization of outputs from the first One or more derived outputs of the first, second and third preamplifiers. 21. The system of claim 20, wherein the analog signal delay module comprises a delay line having taps, wherein desired taps are selected by switches to obtain a desired delay. 22. The system of claim 20, wherein the analog signal delay module includes a delay filter element that can be switched in or out of the signal path as desired. 23. The system of claim 20, wherein the analog signal delay module includes an adjustable variable element controlled by the voltage control assembly in response to the digital-to-analog converter. 24. The system of claim 1, wherein selection circuitry is coupled to respective overflow signals provided by respective plurality of said analog-to-digital converters. 25. The system of claim 1 , wherein the selection circuit is coupled to a plurality of magnitude comparators each coupled to a respective plurality of the analog-to-digital converters, wherein each of the The magnitude comparators are configured to compare the output of their respective analog-to-digital converters with respective predetermined references, the selection circuit being responsive to the magnitude comparators to determine in advance one or more of the analog-to-digital converters Is it trending towards false readings. 26. The system of claim 1 , comprising respective baseline correction systems associated with respective one or more of said analog-to-digital converters, said baseline correction systems being respectively coupled to multiplexers, said The multiplexer directs the selected one for processing. 27. A method for ultrasonic object detection comprising the steps of: providing a detection signal to the transducer to generate an ultrasonic signal capable of being propagated and reflected in the target object to be detected; receiving ultrasonic echo signals and generating echo signals to be processed; Echo signals are processed in at least three signal processing channels, the echo signals are scaled to a different degree in each processing channel, and then converted to digital output using a respective analog-to-digital converter in each processing channel ;and An output from the analog-to-digital converter is selected that provides the greatest increase in the echo signal without overflow. 28. The method of claim 27 including adjusting the respective sampling times of each analog-to-digital converter to compensate for skew sources including signal propagation delays in each signal path. 29. The method of claim 27 including preventing saturation of a preamplifier input stage associated with a channel to prevent signal distortion from affecting inputs to other channels. 30. The method of claim 27, comprising fine-tuning the respective frequency responses in at least one of the channels such that the three channels have substantially matching frequency responses. 31. The method of claim 27, comprising detecting a channel overflow condition in one or more channels having a higher gain. 32. The method of claim 27, comprising combining the output of the analog-to-digital converter into a continuous output stream. 33. The method of claim 27, comprising canceling signal offset errors in each signal path by injecting a DC signal from a digital-to-analog converter at various points in the analog signal path. 34. The method of claim 27, further comprising varying the reference voltage applied to the ADC in each signal channel to adjust its full scale span by using the DAC. 35. The method of claim 27, including adjusting the active edge position of the clock input to the analog-to-digital converters to ensure that each analog-to-digital converter samples the echo signal at the same point. 36. The method of claim 27, comprising scaling the magnitude of the digital output data obtained by the analog-to-digital converters of the different channels commensurate with the respective gain levels of the analog-to-digital converters. 37. An object inspection system comprising: The transmitting and receiving part is used to generate the detection signal and receive the corresponding echo signal; The transducer is used to convert the detection signal into an ultrasonic signal, apply the ultrasonic signal to the target object to be detected, receive the ultrasonic echo signal, and generate the echo signal for the transmitting and receiving parts; a signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, the signal processing circuit comprising at least one signal processing channel, each channel comprising a respective preamplifier which converts the echo The signal is scaled to different degrees; An analog-to-digital converter coupled to the preamplifiers via an amplifying circuit in such a way that only the non-saturated output of at least one of the preamplifiers is passed to the analog-to-digital converter; and an automatic gain control circuit coupled to the output of the preamplifier and capable of detecting the output amplitude of the preamplifier to provide a gain setting to a multiplier circuit selected to ensure that a non-saturated output is provided to analog-to-digital converter. 38. The system of claim 37, including capture logic coupled to and receiving the output from the analog-to-digital converter and an additional output derived from the automatic gain control circuit. 39. The system of claim 38, wherein the additional output is produced by at least one analog-to-digital converter provided between the capture logic circuit and the automatic gain control circuit. 40. An object inspection system comprising: The transmitting and receiving part is used to generate the detection signal and receive the corresponding echo signal; The transducer is used to convert the detection signal into an ultrasonic signal, apply the ultrasonic signal to the target object to be detected, receive the ultrasonic echo signal, and generate the echo signal for the transmitting and receiving parts; A signal processing circuit coupled with the transmitting and receiving part for receiving and processing the echo signal, the signal processing circuit includes at least two signal processing channels, each channel scales the echo signal to a different degree, and each channel has its own the analog-to-digital converter; a selection circuit that selects the output of the analog-to-digital converter that provides the maximum increase in echo signal without overflow; and A channel mixer is responsive to the selection circuit and is operable to mix the outputs of the analog-to-digital converters to produce a mixed analog-to-digital output. 41. The system of claim 40, wherein the selection circuit is coupled to a plurality of magnitude comparators each coupled to a respective plurality of said analog-to-digital converters, wherein each of said The magnitude comparators are configured to compare the output of their respective analog-to-digital converters with respective predetermined references, the selection circuit responsive to the magnitude comparators to determine in advance one or more of the analog-to-digital converters Is it trending towards false readings. 42. The system of claim 40, wherein each of the analog-to-digital converters has a respective overflow output, and the selection circuitry includes channel selection logic that receives the respective overflow outputs and selectively provides output of the ADC for maximum gain without overflow. 43. The system of claim 40, further comprising respective frequency trimming circuits for at least one of said signal processing channels, the respective frequency trimming circuits matching the frequency responses of the filters to each other. 44. The system of claim 40, comprising first and second analog-to-digital converters each having a respective clock input synchronized to each other by activating a phase adjustment between their clock edges to compensate for Signal path delay in each channel. 45. The system of claim 40, further comprising an exponential generator for scaling the output of the selected analog-to-digital converter output and storing the same output in the random access memory. 46. The system of claim 40 , comprising a DC offset circuit that applies a digital DC offset correction to signal locations located after the selection circuit, wherein the DC offset circuit includes a baseline capture A circuit, the baseline capture circuit is coupled to at least one of the first or second analog-to-digital converter to generate a correction signal, and includes a circuit capable of subtracting from an output signal derived by one of the first or second analog-to-digital converter. Baseline corrector to correct the signal. 47. The system of claim 40, comprising at least first and second signal paths comprising first and second preamplifiers, respectively, said preamplifiers providing first and second scaling of the echo signal, respectively output, wherein the analog signal delay block includes a delay line having taps, wherein the desired tap is selected by a switch to obtain the desired delay. 48. A method for ultrasonic object detection comprising the steps of: providing a detection signal to the transducer to generate an ultrasonic signal capable of being propagated and reflected in the target object to be detected; receiving ultrasonic echo signals and generating echo signals to be processed; echo signals are processed in at least two signal processing channels, the echo signals are scaled to a different extent in each processing channel, and then converted to digital output using a respective analog-to-digital converter in each processing channel ;and selecting an output from the analog-to-digital converter that provides the maximum increase in the echo signal without overflow; and In response to the selecting step, the outputs of the analog-to-digital converters are mixed to produce a mixed analog-to-digital output. 49. The system of claim 48, including adjusting the respective sampling times of each analog-to-digital converter to compensate for skew sources including signal propagation delays in each signal path. 50. The system of claim 48, including preventing saturation of a preamplifier input stage associated with a channel to prevent signal distortion from affecting inputs to other channels. 51. The system of claim 48, including trimming respective frequency responses in at least one of the channels such that the channels have substantially matched frequency responses. 52. The system of claim 48, including detecting a channel overflow condition in one or more channels having a higher gain. 53. The system of claim 48, including canceling signal offset errors in each signal path by injecting DC signals from the digital-to-analog converter at various points in the analog signal path. 54. The system of claim 48, further comprising varying the reference voltage applied to the ADC in each signal channel to adjust its full scale span by using the DAC. 55. The system of claim 48, including adjusting the active edge position of the clock input to the analog-to-digital converters to ensure that each analog-to-digital converter samples the echo signal at the same point. 56. The system of claim 48, comprising scaling the magnitude of the digital output data obtained by the analog-to-digital converters of the different channels commensurate with the respective gain levels of the analog-to-digital converters. 57. An object inspection system comprising: The transmitting and receiving part is used to generate the detection signal and receive the corresponding echo signal; The transducer is used to convert the detection signal into an ultrasonic signal, apply the ultrasonic signal to the target object to be detected, receive the ultrasonic echo signal, and generate the echo signal for the transmitting and receiving parts; A signal processing circuit coupled with the transmitting and receiving part for receiving and processing the echo signal, the signal processing circuit includes at least two signal processing channels, each channel scales the echo signal to a different degree, and each channel has its own the analog-to-digital converter; a selection circuit that selects the output of the analog-to-digital converter that provides the maximum increase in echo signal without overflow; and A delay circuit for delaying the output of at least one of the analog-to-digital converters to allow the analog-to-digital converter to respond to a rising edge of the fast switching input signal before the output is processed by the selection circuit. 58. The system of claim 57, wherein the delay circuit provides a delay that is a multiple of a clock period associated with the system. 59. The system of claim 58, wherein the delay circuit is further effective to delay respective overflow outputs of the analog-to-digital converters. 60. An object inspection system comprising: The transmitting and receiving part is used to generate the detection signal and receive the corresponding echo signal; The transducer is used to convert the detection signal into an ultrasonic signal, apply the ultrasonic signal to the target object to be detected, receive the ultrasonic echo signal, and generate the echo signal for the transmitting and receiving parts; A signal processing circuit coupled with the transmitting and receiving part for receiving and processing the echo signal, the signal processing circuit includes at least two signal processing channels, each channel scales the echo signal to a different degree, and each channel has its own the analog-to-digital converter; a selection circuit that selects the output of the analog-to-digital converter that provides the maximum increase in echo signal without overflow; and A delay circuit effectively causes the selection circuit to refrain from selecting an output of an analog-to-digital converter that has overflowed until after the overflowed analog-to-digital converter has recovered from a saturation condition. 61. An object inspection system comprising: The transmitting and receiving part is used to generate the detection signal and receive the corresponding echo signal; The transducer is used to convert the detection signal into an ultrasonic signal, apply the ultrasonic signal to the target object to be detected, receive the ultrasonic echo signal, and generate the echo signal for the transmitting and receiving parts; A signal processing circuit coupled with the transmitting and receiving part for receiving and processing the echo signal, the signal processing circuit includes at least two signal processing channels, each channel scales the echo signal to a different degree, and each channel has its own the analog-to-digital converter; a selection circuit that selects the output of the analog-to-digital converter that provides the maximum increase in echo signal without overflow; and Respective frequency trimming circuits are used for at least one of the signal processing channels, and the respective frequency trimming circuits make the frequency responses of the channels match each other. 62. An object inspection system comprising: The transmitting and receiving part is used to generate the detection signal and receive the corresponding echo signal; The transducer is used to convert the detection signal into an ultrasonic signal, apply the ultrasonic signal to the target object to be detected, receive the ultrasonic echo signal, and generate the echo signal for the transmitting and receiving parts; A signal processing circuit coupled with the transmitting and receiving part for receiving and processing the echo signal, the signal processing circuit includes at least two signal processing channels, each channel scales the echo signal to a different degree, and each channel has its own the analog-to-digital converter; a selection circuit that selects the output of the analog-to-digital converter that provides the maximum amplitude of the echo signal without overflow; a preamplifier associated with each channel; and Anti-saturation circuitry associated with each preamplifier effective to prevent saturation of the respective input stages of each preamplifier in order to prevent signal distortion from affecting inputs to other channels. 63. An object inspection system comprising: The transmitting and receiving part is used to generate the detection signal and receive the corresponding echo signal; The transducer is used to convert the detection signal into an ultrasonic signal, apply the ultrasonic signal to the target object to be detected, receive the ultrasonic echo signal, and generate the echo signal for the transmitting and receiving parts; A signal processing circuit coupled with the transmitting and receiving part for receiving and processing the echo signal, the signal processing circuit includes at least two signal processing channels, each channel scales the echo signal to a different degree, and each channel has its own the analog-to-digital converter; a selection circuit that selects the output of the analog-to-digital converter that provides the maximum increase in echo signal without overflow; and A reference voltage circuit is applied to each of said analog-to-digital converters in each signal channel, respectively, to adjust its full-scale range. 64. The system of claim 63, wherein the reference voltage circuit includes a respective digital-to-analog converter associated with each respective analog-to-digital converter. 65. A method for ultrasonic object detection comprising the steps of: providing a detection signal to the transducer to generate an ultrasonic signal capable of being propagated and reflected in the target object to be detected; receiving ultrasonic echo signals and generating echo signals to be processed; echo signals are processed in at least two signal processing channels, the echo signals are scaled to a different extent in each processing channel, and then converted to digital output using a respective analog-to-digital converter in each processing channel ;and selecting an output from the analog-to-digital converter that provides the maximum increase in the echo signal without overflow; and The sample data of the echo signal of full dynamic range can be processed in each sample clock cycle in such a way that the sample data can be represented on a linear scale as well as on a logarithmic scale.

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