CN101390065A - Cooperative writing via an address channel of a bus - Google Patents

Abstract

The present invention discloses a processing system and method for communicating over a bus in a processing system. The processing system includes a receiving device, a bus having first, second, and third channels, and a sending device, the sending device being configured to address the receiving device on the first channel and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of the payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.

Description

Coordinated write via the address channel of the bus

Related Application Cross-References

This patent application claims priority based on Provisional Application No. 60/776,529, filed February 24, 2006, entitled "Cooperative Writes Over Address Channel," and is assigned to the assignee of the present invention and is hereby expressly incorporated herein by reference.

This patent application is related to the following co-pending U.S. Patent Application No. 060485, filed concurrently herewith and entitled "Auxiliary Writes Over Address Channel," assigned to To the assignee of the present invention and expressly incorporated herein by reference.

technical field

The present disclosure relates generally to processing systems, and more particularly to systems and techniques for performing cooperative writes over address channels with a bus context.

Background technique

At the heart of most modern processing systems is an interconnect known as a bus. The bus moves information between the various processing entities in the system. Today, most bus architectures are pretty standard. These standard bus architectures usually have independent and separate read, write and address channels.

In processing systems, this type of bus architecture is often found to have one or more general uses supported by memory. In these systems, the memory provides the storage medium that holds the programs and data that the processor needs to perform its functions. The processor can read from or write to the memory by setting the address on the address channel and sending the appropriate read/write control signals. Depending on the state of the read/write control, the processor writes to the memory via the write channel or reads from the memory via the read channel. In these types of processing systems, as well as many others, it may be desirable to reduce write latency and increase write bandwidth.

Contents of the invention

One aspect of a processing system is disclosed below. The processing system includes: a receiving device; a bus having first, second and third channels; and a transmitting device configured to address the receiving device on the first channel and to address the receiving device on the second channel. reading a payload from the receiving device on a channel, the sending device further configured to write the first portion of the payload to the receiving device on a first channel and write the payload to the receiving device on a third channel the second part of .

Another aspect of a processing system is disclosed below. The processing system comprises: receiving means; a bus having first, second and third channels; addressing means for addressing the receiving means on the first channel; reading means, which for reading a payload from a receiving device on said second channel; and writing means for writing a first portion of a payload to a receiving device on said first channel and on said third channel A second portion of the payload is written to a receiving device.

An aspect of a method of communicating between a sending device and a receiving device via a bus is disclosed below. The bus includes first, second and third channels. The method includes: addressing a receiving device on a first channel; reading a payload from the receiving device on a second channel; and writing a first portion of the payload to the receiving device on the first channel and A second portion of the payload is written to the receiving device on the third channel.

One aspect of a bus master is disclosed below. The bus mastering device includes: a processor; and a bus interface configured to interface the processor to a bus having first, second and third channels, the bus interface further configured to operate at the addressing the slave device on the first channel, receiving a payload from the slave device on the second channel and writing the first part of the payload to the slave device on the first channel and writing to the slave device on the third channel Write the second part of the payload.

The invention also discloses another aspect of the bus master control device. The bus master device includes: a processor; and interfacing means for interfacing the processor to a bus with first, second and third channels; interfacing means for interfacing the processor Interfaced to said bus, which includes means for addressing a slave device on a first channel; receiving means for receiving a payload from a slave device on a second channel; and writing means for receiving a payload on a second channel A first portion of the payload is written to the slave device on the first channel and a second portion of the payload is written to the slave device on the third channel.

An aspect of a slave device is disclosed below. The slave device includes: a memory; and a bus interface configured to interface the memory to a bus having first, second and third channels, the bus interface configured to slave a bus master on the first channel The device receives the address and a first portion of the payload, sends the payload to the bus master on a second channel, and receives a second portion of the payload from the bus master on a third channel.

Another aspect of a slave device is disclosed below. The slave device includes: a memory; and interfacing means for interfacing the memory to a bus having first, second and third channels; interfacing means for interfacing the memory to the A bus comprising means for receiving an address and a first portion of a payload from a bus master on a first channel; sending means for sending a payload to the bus master on a second channel; and receiving means , for receiving the second portion of the payload from the bus master on a third channel.

It is understood that other embodiments of the invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various other respects, all without departing from the invention. Accordingly, the drawings and description herein should be regarded as illustrative in nature and not limiting.

Description of drawings

Various aspects of the invention are illustrated herein, by way of example and not limitation, in the accompanying drawings, in which:

1 is a simplified block diagram illustrating an example of two devices communicating via a bus in a processing system;

2 is a diagram showing the flow of information on the address and write channels of the bus in the processing system of FIG. 1, wherein the address channels provide a generic medium for address and data;

3 is a timing diagram showing two write operations via the bus in the processing system of FIG. 1;

4 is a simplified block diagram illustrating a cache coherency processing system having two processing devices communicating with shared resources via a bus interconnect;

5 is a diagrammatic illustration showing the flow of information on address and write channels between a processing device and a bus interconnect in the cache coherent processing system of FIG. 4. FIG.

6 is a simplified block diagram illustrating an example of two devices communicating via a 4-channel bus in a processing system.

7 is a diagram showing the flow of information on the address and write channels of the 4-channel bus in the processing system of FIG. 6, wherein the read and write address channels provide generic media for addresses and data.

Detailed ways

The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various embodiments of the invention, and is not intended to represent that the invention can be practiced only in these embodiments. In order to provide the reader with a thorough understanding of the invention, several specific details are included in the detailed description. It will be readily apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention.

1 is a simplified block diagram illustrating an example of two devices communicating via a bus in a processing system. Processing system 100 may be a collection of hardware devices that cooperate to perform one or more processing functions. Typical applications for the processing system 100 include, but are not limited to: desktop computers, laptop computers, servers, cellular phones, personal digital assistants (PDAs), game consoles, pagers, modems, audio equipment, medical devices, automotive , video equipment, industrial equipment or any other machine or device capable of processing, retrieving and storing information.

Processing system 100 is shown having sending device 102 in communication with receiving device 104 via bus 106 . The bus 106 includes three channels: an address channel 106a, a write channel 106b, and a read channel 106c. A "channel" is defined as a set of electrical conductors that can be used to carry information between two devices and that have a common set of control signals. In this example, each channel is 32 bits wide. Typically, a bus interconnect (not shown) will be used to establish a point-to-point communication path between sending device 102 and receiving device 104 via bus 106 . Alternatively, bus 106 may be a dedicated bus, a shared bus, or any other type of suitable bus architecture.

The transmitting device 102 may be any type of bus mastering device. In this example, sending device 102 includes processor 108 and bus interface 110 . Processor 108 may be a general purpose processor such as a microprocessor, a special purpose processor such as a digital processor (DSP), an application specific integrated circuit (ASIC), a direct memory access (DMA) controller, a bridge, a programmable Logic components or any other entities that require access to the bus 106 . The bus interface 110 is used to drive the address and write channels 106a, 106b and to provide appropriate control signals. The bus interface 110 also acts as a receiver for the read channel 106c.

The receiving device 104 may be any type of slave device. Receiving device 104 may be a temporary memory (e.g., SDRAM, DRAM, or RAM) or a longer term storage device (e.g., flash memory, ROM memory, EPROM memory, EEPROM memory, CD-ROM, DVD, magnetic disk, rewritable optical disk, etc. ). Alternatively, receiving device 104 may be a bridge or any other device capable of retrieving and storing information. In this example, receiving device 104 includes interface bus 112 and memory 114 . Interface bus 112 is used to drive read channel 106c and appropriate control signals. The bus interface 112 also acts as a receiver for the address and write channels 106a, 106b. Memory 114 may be any device whose contents can be arbitrarily accessed (ie, read and written).

In this bus architecture, the sending device 102 can read from or write to the receiving device 104 . When the sending device 102 performs a write operation, an address is sent on the address channel 106a to the receiving device 104 with appropriate control signals. The payload may be sent on the address channel 106a, the write channel 106b, or both. The "payload" refers to the data associated with a particular read or write operation, and in this case a write operation. When the sending device performs a read operation, it sends an address to the receiving device 104 on the address channel 106a with appropriate control signals. In response, the receiving device 104 transmits a payload to the sending device 102 on the read channel 106c.

Two examples of write operations will now be described with reference to FIG. 2 . Figure 2 is a diagram showing addresses and information flow on a write channel. In this example, the sending device initiates two 16-byte write operations.

Referring to FIG. 2, on a first clock cycle 202, the sending device initiates a first 16-byte write operation by sending a 4-byte address A1 to the receiving device on address channel 106a with appropriate control signals. During the same clock cycle 202, the sending device may also send the first 4 bytes W1(1) of the first payload to the receiving device on the write channel 106b.

On a second clock cycle 204, the sending device sends data using both address channel 106a and write channel 106b. The sending device sends the second 4 bytes W1(2) of the first payload on write channel 106b and the third 4 bytes W1(3) of the first payload on address channel 106a.

The sending device initiates the next 16-byte write operation during the third clock cycle 206 by sending the 4-byte address A2 on the address channel 106a to the receiving device with appropriate control signals. The sending device completes the transmission of the first payload during the same clock cycle of the next write operation by sending the last 4 bytes W1(4) to the receiving device on the write channel 106b.

The sending device then uses the next two clock cycles to send the second payload to the receiving device. On the fourth clock cycle 208, the sending device sends the first 4 bytes W2(1) of the second payload to the receiving device on the write channel 106b and the second 4 bytes of the payload on the address channel 106a to the receiving device. The second 4 bytes of the payload W2(3). On the next clock cycle 210, the sending device sends the third 4 bytes W2(3) of the second payload to the receiving device on the write channel 106b, and sends the second valid payload to the receiving device on the address channel 106a. The last 4 bytes of the payload W2(4).

Two types of control signals can be used to support the medium for address and data transfer. A first control signal, referred to as an "address/data" signal, is used on the address channel 106a to indicate whether the information being transmitted is an address or data. In this example, an address is transmitted on address channel 106a when the address/data signal is asserted. Conversely, when the address/data signal is de-asserted, data is transferred on address channel 106a.

A second control signal called "tick ID" is used on both address and write channels 106a, 106b to indicate the tick of the current payload being transmitted. It should be noted that the "Tick ID" is a zero-based indicator such that a value of "0" indicates the first tick of the payload being transmitted. In this example, each payload is transmitted in its entirety before the next payload is transmitted, and thus no signaling is required to identify each payload. In an alternative embodiment of the processing system, wherein the payloads are transmitted out of order, or the ticks of different payloads are interleaved, the signaling may include a payload sequence number.

An example illustrating how two control signals may be used will now be described with reference to FIG. 3 . The address and bus protocol for writing to the channels 106a, 106b are shown in Table 1 below. This bus protocol is used to illustrate aspects of the inventive processing system, and it should be understood that these aspects of the invention may be used with other bus protocols. Those skilled in the art will readily be able to change and/or add signals to this protocol in an actual implementation of the bus architecture described herein.

Table 1

Table 2

FIG. 3 is a timing diagram showing control signals for the same two 16-byte write operations described above in connection with FIG. 2 . A system clock 306 may be used to synchronize communications between sending and receiving devices. The system clock 306 is shown to have five clock cycles, where each clock cycle is numbered sequentially.

A write operation may be initiated on address channel 106a during a first clock cycle 301 by a sending device. This write operation can be implemented by transmitting the address A1 of the first write operation on the 32-bit address medium 308 . The sending device asserts the A Valid 312 signal to indicate that valid information is being transmitted on address channel 106a. The sending device 102 also asserts the address/data signal 313 to be addressed by indicating the information 106a being transmitted on the address channel. The sending device 102 asserts the read/write signal 316 to request a write operation. Payload size 318 may be used to indicate the size of the payload, which in this case is 16 bytes. The state of the address tick ID 314 is negligible during the address lifetime on the address channel 106a.

During the same first clock cycle 301, the sending device uses the write medium 320 to transmit the first 4 bytes W1(1) of the first payload and sets the write tick ID 326 to "0". The sending device also asserts the W valid signal 324 to indicate that valid information is being transmitted on the write channel 106b.

At the end of the first clock cycle 301, the sending device checks the asserted Address Transfer Ack signal 310 to acknowledge the successful delivery of address A1 to the receiving device via address channel 106a. The sending device also checks the asserted Write Transfer Ack signal 322 to confirm the successful delivery of the first 4 bytes W1(1) of the first payload to the receiving device via the write channel 106b.

On the second clock cycle 302, the sending device uses the write medium 320 to send the second 4 bytes W1(2) of the first payload and sets the write tick ID 326 to "01". The sending device also asserts the W valid signal 324 to indicate that valid information is being transmitted on the write channel 106b.

During the same second clock cycle 302, the sending device transmits the third 4 bytes W1(3) of the first payload on the address medium 308 to the receiving device and sets the address tick ID 314 to "10". The sending device also asserts the A Valid 312 signal to indicate that valid information is being transmitted on the address channel 106a, and deasserts the Address/Data signal 313 to indicate that the information being transmitted on the address channel 106a is data. During the data lifetime on address channel 106a, the state of read/write signal 316 and payload size 318 are negligible. In FIG. 3, read/write signal 316 and payload size 318 remain unchanged, but can be set to any state.

At the end of the second clock cycle 302, the sending device checks the asserted Write Transfer Ack signal 322 to confirm successful delivery of the second 4 bytes W1(2) of the first payload to the receiving device via the write channel 106b. The sending device also checks the Asserted Address Transfer Ack signal 310 to confirm the successful delivery of the third 4 bytes W1(3) of the first payload to the receiving device via the address channel 106a.

On the third clock cycle 303, the sending device uses the write medium 320 to send the last 4 bytes W1(4) of the first payload and sets the write tick ID 326 to "11". The sending device also asserts the W valid signal 324 to indicate that valid information is being transmitted on the write channel 106b.

During the same third clock cycle 303 in which the first write operation is completed, the sending device transmits on the address medium 308 the address A2 for the second 16-byte write operation. The sending device asserts the A Valid 312 signal to indicate that valid information is being transmitted on address channel 106a. Sending device 102 also asserts address/data signal 313 to indicate that the information being transmitted on address channel 106a is address A2. The sending device 102 asserts the read/write signal 316 to request a write operation. Payload size 318 may be used to indicate the payload size, which in this case is 16 bytes. During the address lifetime on the address channel 106a, the state of the address tick ID 314 is negligible.

At the end of the third clock cycle 303, the sending device checks the asserted address transfer Ack signal 310 to confirm the successful delivery of address A2 to the receiving device via the address channel 106a. The sending device also checks the asserted Write Transfer Ack signal 322 to confirm the successful delivery of the last 4 bytes W1(4) of the first payload to the receiving device via the write channel 106b.

The sending device uses the next two clock cycles to send the second payload to the receiving device. On the fourth clock cycle 304, the sending device sends the first 4 bytes W2(1) of the second payload to the receiving device using the write medium 320 and sets the write tick ID 326 to "00". The sending device continues to assert the W valid signal 324 to indicate that valid information is being transmitted on the write channel 106b.

During the same fourth clock cycle 304, the sending device transmits the second 4 bytes W2(2) of the second payload on the address medium 308 and sets the address tick ID 314 to "0". The sending device also asserts the A Valid 312 signal to indicate that valid information is being transmitted on the address channel 106a, and deasserts the Address/Data signal 313 to indicate that the information being transmitted on the address channel 106a is data. During the data lifetime on address channel 106a, the state of read/write signal 316 and payload size 318 are negligible.

At the end of the fourth clock cycle 304, the sending device checks the asserted Write Transfer Ack signal 322 to confirm successful delivery of the first 4 bytes W2(2) of the second payload to the receiving device via the write channel 106b. The sending device also checks the Asserted Address Transfer Ack signal 310 to acknowledge the successful delivery of the second 4 bytes W2(2) of the second payload to the receiving device via the address channel 106a.

On the fifth clock cycle 305, the sending device sends the third 4 bytes W2(3) of the second payload to the receiving device using the write medium 320 and sets the write tick ID 326 to "10". The sending device asserts the W valid signal 324 to indicate that valid information is being transmitted on the write channel 106b.

During the same fifth clock cycle 305, the sending device transmits the last 4 bytes W2(4) of the second payload on the address medium 308 and sets the address tick ID 314 to "11". The sending device also asserts the A Valid 312 signal to indicate that valid information is being transmitted on the address channel 106a, and deasserts the Address/Data signal 313 to indicate that the information being transmitted on the address channel 106a is data. During data lifetime on address channel 106a, the state of read/write signal 316 and payload size 318 are negligible.

At the end of the fifth clock cycle 305, the sending device checks the asserted Write Transfer Ack signal 322 to confirm successful delivery of the third 4 bytes W2(3) of the second payload to the receiving device via the write channel 106b. The sending device also checks the Asserted Address Transfer Ack signal 310 to acknowledge the successful delivery of the last 4 bytes W2(4) of the second payload to the receiving device via the address channel 106a.

Signaling reduction can be achieved by replacing the tick ID with an implicit addressing scheme. An example of this implicit addressing scheme is shown in Figure 2. In this example, the implicit addressing scheme requires that the next 4-byte sequence of the current payload be transmitted on the earliest clock cycle available, preferably requiring write channel 106b rather than address channel 106a.

Referring to FIG. 2 , the earliest clock cycle available to send the first 4 bytes W1 ( 1 ) of the first payload is the first clock cycle 202 , and the write channel 106 b is available during clock cycle 202 . The earliest clock cycle available to send the second 4 bytes W1(2) of the first payload is the second clock cycle 204, and the write channel 106b is also available. The second clock cycle 204 is also available to transmit the third 4-byte W1(3) of the first payload, but the write channel 106b is not available. Accordingly, the third 4 bytes W1(3) of the first payload are transmitted on address channel 106a. The earliest clock cycle available to send the last 4 bytes W1(4) of the first payload is the third clock cycle 206, and write channel 106b is also available.

During the third clock cycle 206, the address A2 for the second write operation is transmitted to the receiving device. However, the write channel 106a cannot be used to send the first 4 bytes W2(1) of the second payload because the last 4 bytes W1(4) of the first payload need to be sent during the third clock cycle 206 . The earliest clock cycle available to send the first 4 bytes W2(1) of the second payload is the fourth clock cycle 208, and the write channel 106b is available during clock cycle 208. The fourth clock cycle 208 can be used to transfer the second 4 bytes W2(2) of the second payload, but the write channel 106b is not available. Thus, the second 4 bytes W2(2) of the second payload are transmitted on the address channel 106a. The earliest clock cycle available to send the last 8 bytes W2(3), W2(4) of the second payload is the fifth clock cycle 210. The third 4 bytes W2(3) of the second payload are transmitted on the write channel 306b (i.e., the preferred channel), and the last 4 bytes W2(4) of the second payload are transmitted on the address channel 106a .

The use of address channels as the medium for transmitting addresses and data can be used in a variety of processing environments. For example, this technique can be used to reduce the amount of time it takes a processor to obtain a cache line from another processor in a hardware-enforced cache coherency system. This example will be further described with reference to FIG. 4 . A cache coherency processing system 400 is shown in FIG. 4 having two processing devices 402 a , 402 b communicating with a shared resource (eg, memory device 404 ) via a bus interconnect 406 . In this example, the first processing device 402a reads from the memory device 404 by setting an address on its address channel 406a ₁ with appropriate control signals. The address is forwarded by the bus interconnect 406 to the memory device 404 on the memory's address channel _406a3 . In response, bus interface 408 retrieves a block of data from memory 410 and sets it on read channel _406c3 of the memory. The bus interconnect 406 forwards data from the memory device 404a to the first processing device 402a via the read channel _406c1 of the first processor device. Once the data is received by the first processing device 402a, the data may be placed in the cache memory 412, modified by the processor 414, and written back to the memory device 404 by the bus interface 416. The write operation may be performed in the same manner as described above in connection with FIGS. 2 and 3 .

Cache coherency handles the situation where the second processing device 402b subsequently attempts to read from the same address. Since there is no mechanism to ensure cache coherency, if the data in the cache 412 in the first processing device 402a has been modified but not written back to the memory device 404, the second processing device 402b can retrieve the data from the memory device 404. 404 Received expired data.

Coherency between cache and memory is typically maintained using a process called "snooping". Snooping is the process by which a processing device (such as the second processing device 402b in this example) issues a read request to a cacheable address in the memory device 404 that is not present in its own cache 418, causing a bus transaction. Link 406 broadcasts the snoop address to other processing devices in the system before forwarding the read request to memory device 404 for data. If another processing device (eg, first processing device 402 a ) stores the requested data in its cache memory 412 in a modified state, it writes the modified data back to memory device 404 . At the same time, the bus interconnect 406 will send the modified data to the second processing device 402b via the intermediate read channel _406c2 . The second processing means 402 places the modified data in the cache memory 418 for use by the processor 422 .

FIG. 5 is a diagram showing the address and information flow on the write channels 406a ₁ , 406b ₁ between the first processing device 402a and the bus interconnect 406 . Referring to FIGS. 4 and 5 , the first processing device 402 a writes a 32-byte payload from its cache 412 to the memory device 404 in response to the snoop address broadcast by the bus interconnect 406 . The write operation is performed by sending a 32-byte payload to the bus interconnect 406 using both address and write channels 406a ₁ , 406b ₁ . On a first clock cycle 502, the first processing device 402a sends the snooped address A to the bus interconnect 406 on its address channel _406a1 with appropriate control signals. During the same clock cycle 502, the first 4 bytes W(1) of the payload are sent by the first processing device 402a to the bus interconnect 406 on the write channel _406b1 .

The remainder of the payload is sent from the first processing device 402a to the bus interconnect 406 via the next four clock cycles. On the second clock cycle 504, the first processing device 402a sends the second 4 bytes W( ₂ ) of the payload on the write channel 406b1 and the third 4 words of the payload on the address channel _406a1 Section W(3). The fourth 4 bytes W(4) of the payload, the sixth 4 bytes W(6) of the payload and the last 4 bytes W(8) of the payload are passed by the first processing means 402a via the next three Clock cycles 506, 508, 510 are sent to bus interconnect 406 on write channel _406b1 . The fifth 4 bytes W(5) of the payload and the seventh 4 bytes W(7) of the payload are sent by the first processing device 402a via the next two clock cycles 506, 508 on the address channel _{406a1 to} Bus interconnection 406 .

The bus interconnect 406 can similarly send the 32-byte payload to the memory device 404 using both address and write channels _406a3 , _406b3 to send the payload in 5 clock cycles. The bus interconnect 406 also sends the 32-byte payload on the read channel _406c2 to the second processing device 402b in 8 clock cycles in response to the original read request by the processing device 402b. The transmission of the 32-byte payload to the memory device 404 and the second processing device 402 may overlap or follow the transmission of the payload between the first processing device 402a and the bus interconnect 406 .

The explanation of the control signaling has been described in detail in conjunction with FIG. 3, and will not be repeated here, only one point is pointed out: the address and the beat ID written in both channels 406a ₁ and 406b ₁ need to be expanded to 3-bit codes to handle 8 Beat payload.

FIG. 6 is a simplified block diagram illustrating an example of two devices communicating via a 4-channel bus in a processing system 600 . A separate and independent address channel is provided for each read and write channel. In this example, each channel is 32 bits wide, but in practice could be any width, depending on the particular application and overall design constraints. Writing over a 4-lane bus can be performed by sending an address to receiving device 604 on write address channel 606a and data to receiving device 604 on write address channel 606a, write channel 606b, and/or read address channel 606d Enter operation. A read operation via the 4-channel bus is performed by sending an address to the receiving device 604 on the read address channel 606d. In response, the receiving means 604 transmits a payload to the sending means 602 on the read channel 606c.

7 is a diagram showing information flow on a write address channel, a read address channel, and a write channel between a sending device and a receiving device via a 4-channel bus. On the first clock cycle 702, the sending device initiates a write operation of the first 16 bytes by sending 4 bytes of address A1 to the receiving device on write address channel 606a with appropriate control signals. During the same clock cycle 702, the sending device also transmits the first 4 bytes W1(1) of the first payload on the write channel 606b and the second 4 bytes of the same payload on the read address channel 606d. Byte W1(2).

On a second clock cycle 704, the remainder of the first payload is transmitted by the transmitting device to the receiving device. More specifically, on the second clock cycle 704 that completes the first write operation, the sending device transmits the third 4 bytes W1(3) of the first payload on the write channel 606b and on the read address channel The last 4 bytes W1(4) of the first payload are transmitted at 606d. During the same clock cycle 704, the sending device sends address A2 for the second 16-byte write operation to the receiving device on write address channel 606a.

The sending device then uses the next two clock cycles to send the second payload to the receiving device. On the third clock cycle 706, the sending device sends the first 4 bytes W2(1) of the second payload to the receiving device on the write channel 606b and the second valid payload to the receiving device on the read address channel 606d. The second 4 bytes W2(2) of the payload and the third 4 bytes W2(3) of the second payload are sent to the receiving device on the write address channel 606a. On the next clock cycle 708, the sending device sends the last 4 bytes of the second payload W2(4) to the receiving device on write channel 606b.

The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable Gate arrays (FPGAs) or other programmable logic components, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, e.g., a DSP in combination with a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The methods or algorithms described in connection with the embodiments disclosed herein may be directly embodied in hardware, software modules executable by a processor, or a combination of both. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC may reside in the transmit and/or receive components or elsewhere. Alternatively, the processor and storage medium may reside as discrete components in the transmitting and/or receiving components or elsewhere.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the intention is not to limit the present invention to the embodiments shown herein but to give it the widest scope consistent with the principles and novel features disclosed herein.

Claims (42)

1. A processing system comprising: receiving device; a bus having first, second and third channels; and a transmitting device configured to address the receiving device on the first channel and to read a payload from the receiving device on the second channel, the transmitting device further configured to address the receiving device on the second channel A first portion of the payload is written to the receiving device on a first channel and a second portion of the payload is written to the receiving device on the third channel. 2. The processing system of claim 1, wherein the sending device is further configured to simultaneously write the first and second portions of the payload to the receiving device. 3. The processing system of claim 1, wherein the sending device is further configured to simultaneously address and write the second portion of the payload to the receiving device. 4. The processing system of claim 1, wherein the sending device is further configured to write the first and second portions of the payload to a first address of the receiving device, the sending device Further configured to send a second address to the receiving device on the first channel concurrently with the writing the second portion of the payload to the receiving device. 5. The processing system of claim 1, wherein the sending means comprises a first processing means and the receiving means comprises a bus interconnect, the processing system further comprising a second processing means, the bus interconnect configured to connect the first and second processing devices to a shared resource, and wherein the first processing device is further configured to write a payload to the bus interconnect in response to a snoop address from the second processing device The first and second parts of . 6. The processing system of claim 1, wherein the bus further comprises a fourth channel, the transmitting device is further configured to address the receiving device on the first channel for a write operation, and addressing the receiving device on a fourth channel for a read operation, and wherein the sending device is further configured to write a third of the payload to the receiving device on the fourth channel part. 7. The processing system of claim 6, wherein the sending device is further configured to simultaneously write the first, second and third portions of the payload to the receiving device. 8. The processing system of claim 6, wherein the sending device is further configured to write the first, second and third portions of the payload to a first address of the receiving device, the The sending device is further configured to send a second address to the receiving device on the first channel at the same time as the writing the second or third portion of the payload to the receiving device. 9. The processing system of claim 1, wherein the sending device is further configured to provide a control signal to the receiving device, the control signal indicating that the first channel is currently being used to address the receiving device Also writing the first portion of the payload to the receiving device. 10. The processing system of claim 1, wherein the sending device is further configured to provide a control signal to the receiving device on each of the first and third channels, in the control signal Each of identifies the portion of the payload being sent on its corresponding channel. 11. A processing system comprising: receiving device; a bus having first, second and third channels; addressing means for addressing said receiving means on said first channel; reading means for reading a payload from said receiving means on said second channel; and writing means for writing a first portion of the payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel. 12. A method of communicating between a transmitting device and a receiving device via a bus, the bus comprising first, second and third channels, the method comprising: addressing a receiving device on said first channel; read a payload from the receiving device on the second channel; and A first portion of a payload is written to the receiving device on the first channel and a second portion of the payload is written to the receiving device on the third channel. 13. The method of claim 12, wherein the first and second portions of the payload are written to the receiving device simultaneously. 14. The method of claim 12, wherein the receiving device is addressed at the same time as the writing the second portion of the payload to the receiving device. 15. The method of claim 12, wherein said first and second portions of said payload are written to a first address of said receiving device, said addressing of said receiving device further comprising at The writing of the second portion of the payload to the receiving device is concurrent with sending a second address to the receiving device on the first channel. 16. The method of claim 12, wherein the transmitting device comprises a first processing device and the receiving device comprises a bus interconnect, the processing system further comprising a second processing device, the bus interconnect configured to The first and second processing devices are connected to a shared resource, and wherein the first and second portions of a payload are written to the bus interconnect in response to a snoop address from the second processing device. 17. The method of claim 12, wherein said bus further comprises a fourth channel, said addressing of said receiving device on said first channel is for a write operation, said method further comprising The receiving device is addressed for a read operation on the fourth channel and a third portion of the payload is written to the receiving device on the fourth channel. 18. The method of claim 17, wherein the sending device is further configured to simultaneously write the first, second and third portions of the payload to the receiving device. 19. The method of claim 18, wherein writing said first, second and third portions of said payload to a first address of said receiving device, said method further comprising Sending a second address to the receiving device on the first channel at the same time the receiving device writes the second or third portion of the payload. 20. The method of claim 12, further comprising providing a control signal to the receiving device, the control signal indicating whether the first channel is currently being used to address the receiving device or to the receiving device Writing the first portion of the payload. 21. The method of claim 12, further comprising providing a control signal to the receiving device on each of the first and third channels, each of the control signals identifying the The portion of the payload being sent on its corresponding channel. 22. A bus master device, comprising: processor; and a bus interface configured to interface the processor to a bus having first, second and third channels, the bus interface further configured to address slave devices on the first channel, on the receiving a payload from the slave device on the second channel, and writing the first portion of the payload to the slave device on the first channel and writing the payload to the slave device on the third channel The second part of the payload described above. 23. The bus master device of claim 22, wherein the bus interface is further configured to simultaneously write the first and second portions of the payload to the slave device. 24. The bus master device of claim 22, wherein the bus interface is further configured to simultaneously address and write the second portion of the payload to the slave device. 25. The bus master device of claim 22, wherein the bus interface is further configured to write the first and second portions of the payload to a first address of the slave device, the The bus interface is further configured to send a second address to the slave device on the first channel concurrently with the writing the second portion of the payload to the slave device. 26. The bus master device of claim 22, wherein the slave device includes a bus interconnect configured to connect the bus master device and a second bus master device to a shared resource , and wherein the bus master is further configured to write the first and second portions of a payload to the bus interconnect in response to a snoop address from the second bus master. 27. The bus master device of claim 22, wherein said bus further comprises a fourth channel, said bus interface being further configured to address said slave device on said first channel for writing and addressing the slave device on the fourth channel for a read operation, and wherein the bus interface is further configured to write the valid The third part of the load. 28. The bus master device of claim 27, wherein the bus interface is further configured to simultaneously write the first, second and third portions of the payload to the slave device. 29. The bus master device of claim 27, wherein the bus interface is further configured to write the first, second and third portions of the payload to a first address of the slave device , the bus interface is further configured to send a second address to the slave device on the first channel at the same time as the writing the second or third portion of the payload to the slave device . 30. The bus master device of claim 22, wherein the bus interface is further configured to provide a control signal to the slave device, the control signal indicating that the first channel is currently being used to address the A slave also writes the first portion of the payload to the slave. 31. The bus master device of claim 22, wherein the bus interface is further configured to provide a control signal to the slave device on each of the first and third channels, the control Each of the signals identifies the portion of the payload being sent on its corresponding channel. 32. A bus master device, comprising: processor; and interfacing means for interfacing the processor to a bus having first, second and third channels; the means for interfacing the processor to the bus comprises: for interfacing the processor at the means for addressing a slave device on said first channel; means for receiving a payload from said slave device on said second channel; and means for writing a valid payload to said slave device on said first channel means for loading a first portion of the payload and writing a second portion of the payload to the slave device on the third channel. 33. A slave device comprising: memory; and a bus interface configured to interface the memory to a bus having first, second and third channels, the bus interface further configured to receive an address and A first portion of a payload, sending a payload to the bus master on the second channel, and receiving a second portion of the payload from the bus master on the third channel. 34. The slave device of claim 33, wherein the bus interface is further configured to receive the first and second portions of the payload concurrently. 35. The slave device of claim 33, wherein the bus interface is further configured to simultaneously receive the address and the second portion of the payload. 36. The slave device of claim 33, wherein the bus interface is further configured to write the first and second portions of the payload to a first address in the memory, the bus interface Further configured to receive a second address on the first channel concurrently with the second portion of the payload. 37. The slave device of claim 33, wherein the bus further comprises a fourth channel, the bus interface is further configured to receive the address on the first channel for a write operation, and in An address is received on the fourth channel for a read operation, and wherein the bus interface is further configured to receive a third portion of the payload from the bus master on the fourth channel. 38. The slave device of claim 37, wherein the bus interface is further configured to receive the first, second and third portions of the payload simultaneously. 39. The slave device of claim 37, wherein the bus interface is further configured to write the first, second and third portions of the payload to a first address in the memory, the The bus interface is further configured to receive a second address from the bus master on the first channel concurrently with the receiving the second or third portion of the payload. 40. The slave device of claim 33, wherein the bus interface is further configured to receive a control signal from the bus master device, the control signal indicating that the first channel is currently being used to transmit the address Also said first portion of said payload. 41. The slave device of claim 33, wherein the bus interface is further configured to receive control signals from the bus master device on each of the first and third channels, the control Each of the signals identifies the portion of the payload being sent on its corresponding channel. 42. A slave device comprising: memory; and interfacing means for interfacing said memory to a bus having first, second and third channels; said means for interfacing said memory to said bus comprising: for interfacing said memory with said bus means for receiving an address and a first portion of a payload from a bus master device on a first channel; means for sending a payload to said bus master device on said second channel; and means for transmitting a payload to said bus master device on said third channel; means on a channel that receives the second portion of the payload from the bus mastering means.

Images