CN101425523A - CMOS sensor package assembly and method of manufacturing the same - Google Patents

Abstract

The invention provides a packaging structure of a complementary metal oxide semiconductor sensing chip, which comprises: a carrier plate having an upper surface and a lower surface, the upper surface of the carrier plate being provided with a patterned metal layer; a CMOS sensing chip, wherein the active surface of the CMOS sensing chip is provided with a plurality of CMOS sensing components and a plurality of bonding pads arranged near the periphery of the active surface, and each bonding pad is electrically connected with part of the patterned metal layer; a plurality of electrical connection components arranged on part of the patterned metal layer and forming electrical connection; the sealing colloid covers the upper surface of the carrier plate, the electrical connection assembly and the complementary metal oxide semiconductor sensing device; and a plurality of conductive elements formed on the connecting elements. The novel CMOS sensor packaging process and the structure thereof can effectively reduce the packaging time and effectively improve the reliability of the CMOS sensor.

Description

Complementary metal oxide semiconductor sensor package assembly and manufacturing method thereof

technical field

The present invention mainly relates to a semiconductor packaging component, in particular to a complementary metal oxide semiconductor sensor packaging component and a manufacturing method thereof.

Background technique

The development of semiconductor technology is very fast, especially the trend of miniaturization of semiconductor chips. However, the functional requirements of semiconductor chips tend to be relatively diversified. In other words, semiconductor chips require more I/O pads in a smaller area, so the density of pins also increases rapidly. This makes packaging of semiconductor chips more difficult and reduces yield. The main purpose of the packaging structure is to protect the chip from external damage. However, most of the packaging technologies first cut the chips on a wafer into multiple single chips, and then package and test each single chip. In addition, a packaging technology called "wafer level package" (wafer level package; WLP) can package chips on a wafer before dividing the chip into a single chip. Wafer-level packaging technology has some advantages, such as shorter production cycle, lower cost and no need for under-fill.

A digital imaging technology has been widely applied to imaging devices, such as digital cameras, image scanning devices, etc. Most current imaging devices use complementary metal oxide semiconductor sensors (CMOS sensors) as image reading devices. The CMOS sensor has a chip fixed therein, and the image signal is transmitted to a digital processor through a plurality of array sensing elements in the sensing area of the chip for converting the analog signal into a digital signal. Since the sensing region of the CMOS sensor is quite sensitive to dust particles, the quality of the sensing component will be degraded. In order to achieve the above purpose, a transparent material, especially a glass, is formed on the multiple sensing elements in the sensing area of the chip to protect the sensing elements and increase the focusing function.

Next, please refer to FIG. 1 , which is a packaging structure of a CMOS sensor disclosed in the prior art with wafer-level packaging. The packaging structure is that a CMOS sensor is fixed on an insulating substrate 100, and the An array of microlenses 140 is formed on the sensing area, and then another protection layer 150 is formed on the array of microlenses 140 .

Obviously, in the prior art, the packaging process of the CMOS sensor is relatively complicated and must be completed layer by layer. In addition to increasing the process time, the sensing area of the CMOS sensor may be polluted during the manufacturing process. Therefore, the present invention proposes a new CMOS sensor packaging process and its structure, which can effectively reduce the packaging time and effectively improve the reliability of the CMOS sensor.

Contents of the invention

In view of the above problems, the main purpose of the present invention is to provide a CMOS sensor package assembly, so as to reduce the manufacturing time and save the manufacturing cost.

Another main objective of the present invention is to provide a CMOS sensor package assembly, thereby increasing the reliability of the assembly.

According to the above purpose, the present invention provides a package structure of a complementary metal oxide semiconductor sensing chip, comprising: a carrier plate having an upper surface and a lower surface, the upper surface of the carrier plate is provided with a patterned metal layer; a Complementary metal oxide semiconductor sensing chip, its active surface is equipped with a plurality of complementary metal oxide semiconductor sensing components and has a plurality of pads arranged near the periphery of the active surface, and each pad is connected to a part The patterned metal layer is electrically connected; a plurality of electrical connection components are arranged on part of the patterned metal layer and form an electrical connection; the encapsulant covers the upper surface of the carrier board, the electrical connection components and the complementary a metal oxide semiconductor sensing device; and a plurality of conductive elements formed on the connection elements.

The present invention also discloses a packaging method for a complementary metal oxide semiconductor sensor chip, including: providing a carrier board with an upper surface and a lower surface; forming a plurality of identically patterned metal layers on the upper surface of the carrier board ; then electrically connect a plurality of complementary metal oxide semiconductor sensing chips to a plurality of patterned metal layers, wherein the active surface of the complementary metal oxide semiconductor sensing chip has a plurality of complementary metal oxide semiconductor sensing elements and A plurality of pads are arranged near the periphery of the active surface, and are electrically connected to the part of the patterned metal layer through the pads; electrically connected to a plurality of electrical connection components on the part of the patterned metal layer; Then perform an injection molding step to cover the upper surface of the carrier board, the electrical connection components and the CMOS sensing chips; then expose an end of the electrical connection components; form a plurality of conductive components in each an exposed terminal of the electrical connection element; and performing a cutting step to form a plurality of packaged CMOS sensing devices.

Relevant features of the present invention are described in detail below as the best embodiment in conjunction with the drawings. (In order to have a further understanding of the object, structure, feature, and function of the present invention, now cooperate with embodiment to describe in detail as follows.)

Description of drawings

FIG. 1 is a schematic cross-sectional view of an existing package assembly;

2 is a schematic diagram of forming a plurality of patterned metal layers on a carrier according to the present invention;

3 is a schematic cross-sectional view of a plurality of CMOS sensor chips attached to a plurality of patterned metal layers according to the present invention;

4 is a schematic cross-sectional view of forming a plurality of electrical connection components on the structure of FIG. 3 according to the present invention;

5 is a schematic cross-sectional view of performing an injection molding process according to the present invention to cover the structure of FIG. 4 with an encapsulant;

6 is a schematic cross-sectional view of a plurality of conductive components formed on a plurality of electrical connection components in the structure of FIG. 5 according to the present invention; and

FIG. 7 is a cross-sectional view of another package structure disclosed in the present invention.

Detailed ways

The present invention discloses a package structure of a complementary metal oxide semiconductor sensing chip and a manufacturing method thereof. Therefore, the present invention is aimed at packaging the manufactured and cut complementary metal oxide semiconductor sensing chip. However, for ease of description, the CMOS sensing chip in the present invention is defined as having a plurality of sensing elements arranged in an array on an active surface and a plurality of bonding pads around the sensing elements. 2 to 8 are schematic cross-sectional views illustrating the packaging structure of the complementary metal-oxide-semiconductor sensing chip disclosed in the present invention and a flow chart of manufacturing steps, respectively.

Please refer to FIG. 2 , which is a schematic cross-sectional view showing forming a plurality of patterned metal layers on a carrier. Firstly, a carrier substrate 10 having an upper surface and a lower surface is provided. In a specific embodiment of the present invention, the carrier substrate 10 is a transparent material, which may be glass or optical grade glass. As shown in FIG. 2 , the method of forming a plurality of patterned metal layers 12 on the carrier 10 includes: first forming a metal layer on the carrier 10; then coating a photoresist layer on the metal layer and passing through a After the patterned photomask is exposed and developed, a patterned photoresist layer (not shown) is formed on the metal layer; then an etching step is performed to remove part of the metal layer; There is a patterned photoresist layer, thereby forming a plurality of identically patterned metal layers 12 on the carrier 10 .

In addition, the above-mentioned method of forming a plurality of patterned metal layers 12 on the carrier 10 may also include: first coating the photoresist layer on the carrier 10, then exposing and developing a patterned photomask, and then Patterned grooves or trenches are formed on the photoresist layer, and metal materials are filled into the grooves or trenches, and finally the photoresist is removed to form a patterned metal layer 12 on the carrier 10 . In the present invention, the above-mentioned metal material can be formed by evaporating process or sputtering process, and in a preferred embodiment, it is formed by plating.

In addition, the dotted line 101 on the carrier board 10 is a cutting road (sawing street). It should be emphasized here that the dotted line 101 can be formed on the carrier board 10, and it can also be a line that does not exist. The invention is not limited, and its purpose is to be a reference line for cutting the carrier board 10 after the components are packaged, so as to form a plurality of single packaged components.

Next, please refer to FIG. 3 , which is a schematic cross-sectional view showing a plurality of complementary metal-oxide-semiconductor sensing chips (CMOS chip, Complementary Metal-Oxide Semiconductorchip) 20 attached to a plurality of patterned metal layers 12, wherein complementary The active surface 202 of the type metal oxide semiconductor sensing chip 20 has a plurality of sensing elements (not shown in the figure) arranged in groups and a plurality of pads 2022 around the sensing elements. As shown in FIG. 3 , in the manner of flip chip technology, the upper surface of the plurality of pads 2022 on each complementary metal oxide semiconductor sensing chip 20 facing the patterned metal layer 12, And a plurality of bonding pads 2022 are electrically connected to part of the upper surface of the patterned metal layer 12, so that the flip-chip technology makes a plurality of sensor arrays arranged in groups on each complementary metal oxide semiconductor sensor chip 20 The sensing component performs sensing through the transparent carrier 10 . Here, conductive glue (not shown in the figure), such as solder paste, can be used to electrically connect the plurality of pads 2022 to a part of the upper surface of the patterned metal layer 12 .

Next, please refer to FIG. 4 , which is a schematic cross-sectional view showing a plurality of electrical connection components formed on the structure in FIG. 3 . As shown in FIG. 4 , a plurality of electrical connecting elements (connecting elements) 30 are formed on the upper surface of the exposed part of the patterned metal layer 12, and adjacent to each CMOS sensing chip 20, each of which The heights of the electrical connection components 30 are uniform and higher than the thickness of the CMOS sensor chip 20; insulating material (such as plastic) or ceramic material (ceramic) to cover a plurality of metal lines 302 corresponding to the patterned metal layer 12; ), such as solder paste (paste), is electrically connected to the patterned metal layer 12 on the carrier 10 .

In the manufacturing process of above-mentioned Fig. 2 and Fig. 3, all use conductive glue material as electrical connection material, so in manufacturing, can choose to coat conductive glue material on the patterned metal layer 12; Certainly, its It can also be coated on the bonding pad 202 of the CMOS sensing chip 20 and the terminal of the electrical connection component 30 respectively, and the present invention is not limited thereto.

Next, as shown in FIG. 5 , it is a cross-sectional view showing the encapsulant 40 covering the structure in FIG. 4 . After the plurality of electrical connection components 30 are electrically connected to the patterned metal layer 12, the injection molding process (molding process) is performed immediately to form a colloid 40 to cover the CMOS sensing chip 20. , a plurality of electrical connection components 30 and the patterned metal layer 12 . Then, part of the encapsulant 40 is removed to expose the electrical connection element 30 , for example, when the electrical connection element 30 is a gold finger structure, part of the encapsulant 40 is removed to expose the terminal of the metal wire 302 . In addition, it is also possible to choose to use a protective layer (not shown in the figure), such as adhesive tape, to cover the electrical connection component 30 before the injection molding process, such as the terminal of the metal wire 302, and then inject the mold flow into the After the electrical connection components 30 have the same height, debonding is performed to expose a plurality of electrical connection components 30 . In a specific embodiment of the present invention, the material of the encapsulant 40 includes epoxy or colloid.

Next, please continue to refer to FIG. 6 , which is a schematic diagram showing a plurality of conductive components formed on the electrical connection component 30 (such as the metal wire 302 ). In this specific embodiment, a plurality of conductive components 50 are formed on the top of each exposed electrical connection component 30 by using the existing technology in packaging technology, such as ball planting, so that the conductive components 50 serve as a package body other electrical connections. It should be emphasized here that the conductive component 30 may be a solder ball, or it may be a metal bump.

In addition, the present invention also discloses another specific embodiment, as shown in FIG. 7 . In this embodiment, after the plurality of CMOS sensing chips 20 are electrically connected to the plurality of patterned metal layers 12 on the carrier 10, the injection molding process is first performed to form a package. The colloid 40 is used to cover a plurality of CMOS sensing chips 20 and a part of the patterned metal layer 12 . Next, after the alignment process is completed, an etching step, such as dry etching or reactive ion etching (RIE), is used to remove part of the encapsulant 40 on the patterned metal layer 12 to form multiple layers. A hole is formed and a part of the metal layer 12 exposed by patterning is exposed; then, the hole is filled with conductive material by electroplating to form a plurality of electrical connection components 30, and then a plurality of conductive components 50 are formed. After the multiple electrical connection components 30 are made, the packaging operation steps of the CMOS sensing chip 20 can be completed. Likewise, the conductive component 30 in this embodiment may be a solder ball or a metal bump.

After the above-mentioned steps in FIG. 6 and FIG. 7 are completed, the chip dicing process (diesawing) is performed, and the carrier 10 is cut according to the position of the dicing line 101 to form a plurality of packaged CMOS sensors. device. Obviously, it can be seen from the process disclosed in the present invention that the process of forming a plurality of patterned metal layers 12 on the carrier 10 and the process of completing the complementary metal oxide semiconductor sensing chip 20 can be implemented separately, so it can be effectively Shorten the packaging time; in addition, in the process disclosed in the present invention, it can be known that the 5 faces of each complementary metal oxide semiconductor sensor chip 20 (except the active face connected to the transparent carrier 10) are covered by the encapsulant 40 Therefore, the reliability of the CMOS sensing chip 20 can be improved.

After the complementary metal oxide semiconductor sensing chip 20 is packaged to form a complementary metal oxide semiconductor sensing device, it can pass through a plurality of conductive components 50 and a circuit board (not shown) on the complementary metal oxide semiconductor sensing device. (shown in the figure) is electrically connected, and is electrically connected with other control devices through the circuit board, so as to drive the CMOS sensing device of the present invention to read images. Especially when the CMOS sensing device of the present invention is connected with a flexible circuit, it can be applied to various portable digital imaging devices, such as digital cameras and personal digital assistants. Devices (PDA), communication devices with camera function (such as mobile phones), etc., to increase the applicability of CMOS sensor package components.

Although the present invention is disclosed above with the foregoing preferred embodiments, it is not intended to limit the present invention. Those skilled in the art should be able to make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of patent protection shall be subject to the limitations of the claims.

Explanation of main component symbols

10 carrier board 101 cutting lane

102 sensing area 12 metal layer

20 Complementary metal oxide semiconductor sensor chip (CMOS chip)

202 active surface 2022 pad

30 Electrical connection components 302 Metal wires

40 Sealant 50 Conductive components

Claims (10)

1. A packaging structure for a complementary metal oxide semiconductor sensing chip, comprising: a carrier plate having an upper surface and a lower surface; a patterned metal layer disposed on the upper surface of the carrier and exposing the metal layer; The complementary metal oxide semiconductor sensing chip has a plurality of complementary metal oxide semiconductor sensing components configured on its active surface and has a plurality of pads arranged near the periphery of the active surface, and these pads are electrically connected connected to a portion of the patterned metal layer; A plurality of electrical connection components are arranged on part of the patterned metal layer and form electrical connections; an encapsulant covering the upper surface of the carrier, the electrical connection components and the CMOS sensing device; and A plurality of conductive components are formed on the connection components. 2. The package structure according to claim 1, wherein the electrical connection components are a golden finger structure. 3. A packaging method for a complementary metal oxide semiconductor sensing chip, comprising: providing a carrier plate having an upper surface and a lower surface; forming a plurality of identically patterned metal layers on the upper surface of the carrier, comprising: forming a metal layer on the carrier; forming a plurality of identically patterned photoresist layers on the metal layer; removing part of the metal layer to form the patterned metal layer, and exposing part of the upper surface of the carrier; and removing said photoresist layer having these patterns; Electrically connecting a plurality of complementary metal oxide semiconductor sensing chips to the plurality of patterned metal layers, wherein the active surface of the complementary metal oxide semiconductor sensing chip has a plurality of complementary metal oxide semiconductor sensing chips The test component has a plurality of pads disposed near the periphery of the active surface, and is electrically connected to part of the patterned metal layer through these pads; electrically connecting a plurality of electrical connection components on a portion of the patterned metal layer; performing an injection molding step to cover the upper surface of the carrier board, the electrical connection components and the CMOS sensing chips; exposing the terminals of these electrically connected components; forming a plurality of conductive elements at the terminals of each of the exposed electrical connection elements; and A cutting step is performed to form a plurality of packaged CMOS sensing devices. 4. The packaging method according to claim 3, wherein the electrical connection components are a golden finger structure. 5. A packaging method for a complementary metal oxide semiconductor sensing chip, comprising: providing a carrier plate with an upper surface and a lower surface; forming a plurality of identically patterned metal layers on the upper surface of the carrier; Electrically connecting a plurality of complementary metal oxide semiconductor sensing chips to the plurality of patterned metal layers, wherein the active surface of the complementary metal oxide semiconductor sensing chip has a plurality of complementary metal oxide semiconductor sensing chips The test component has a plurality of pads disposed near the periphery of the active surface, and is electrically connected to part of the patterned metal layer through these pads; Injecting mold flow to form an encapsulant to cover the upper surface of the carrier plate and the CMOS sensing chip; forming a plurality of holes to expose part of the patterned metal layer; filling the holes to form a plurality of electrical connection components; forming a plurality of conductive components over the electrically connected components; and A cutting step is performed to form a plurality of packaged CMOS sensing devices. 6. The packaging method according to claim 5, wherein the method of forming the patterned metal layers comprises: forming a metal layer on the carrier; forming a plurality of identically patterned photoresist layers on the metal layer; removing a portion of the metal layer to form these same patterned metal layers and exposing a portion of the upper surface of the carrier; and removing the patterned photoresist layer. 7. The packaging method according to claim 5, wherein the holes are formed by etching. 8. A packaging method for a complementary metal oxide semiconductor sensing device, comprising: providing a carrier plate having an upper surface and a lower surface; forming a plurality of identically patterned metal layers on the upper surface of the carrier, wherein the method of forming these identically patterned metal layers comprises: forming a metal layer on the carrier; forming a patterned photoresist layer on the metal layer; removing part of the metal layer to form the patterned metal layer, and exposing part of the upper surface of the carrier; and removing the patterned photoresist layer; Electrically connecting a plurality of CMOS sensing chips to the plurality of patterned metal layers, wherein the active surface of the CMOS sensing chip has a plurality of CMOS sensing chips The sensing component has a plurality of pads disposed near the periphery of the active surface, and is electrically connected to part of the patterned metal layer through these pads; electrically connecting a plurality of electrical connection components on a portion of the patterned metal layer; forming an isolation layer on the other end of the plurality of electrical connection components relative to the patterned metal layer; performing an injection molding step to cover the upper surface of the carrier board, the electrical connection components and the CMOS sensing devices; peeling off the isolation layer to expose metal ends of the plurality of electrical connection components relative to the patterned metal layer; forming a plurality of conductive elements on said exposed metal end of each of these electrically connected elements; and A cutting step is performed to form a plurality of packaged CMOS sensing devices. 9. An image reading device, which is formed by electrically connecting a packaged complementary metal oxide semiconductor sensing device to a flexible circuit board, wherein the complementary metal oxide semiconductor sensing device is characterized in that ,include: a carrier plate having an upper surface and a lower surface; a patterned metal layer disposed on the upper surface of the carrier and exposing the metal layer; The complementary metal oxide semiconductor sensing chip has a plurality of complementary metal oxide semiconductor sensing components configured on its active surface and has a plurality of pads arranged near the periphery of the active surface, and these pads are electrically connected on a portion of the patterned metal layer; A plurality of electrical connection components are arranged on part of the patterned metal layer and form electrical connections; an encapsulant covering the upper surface of the carrier, the electrical connection components and the CMOS sensing device; and A plurality of conductive components are formed on the connection components and electrically connected with the flexible circuit board. 10. A digital device having a complementary metal oxide semiconductor sensing device selected from the group consisting of a digital camera, a mobile phone, and a personal digital assistant, wherein the complementary metal oxide semiconductor sensing device The measuring device is characterized in that it includes a carrier plate having an upper surface and a lower surface; a patterned metal layer disposed on the upper surface of the carrier and exposing the metal layer; The complementary metal oxide semiconductor sensing device has a plurality of complementary metal oxide semiconductor sensing elements configured on its active surface and has a plurality of pads arranged near the periphery of the active surface, and the pads are electrically connected Sexually connected to a portion of the patterned metal layer; A plurality of electrical connection components are arranged on part of the patterned metal layer and form electrical connections; an encapsulant covering the upper surface of the carrier, the electrical connection components and the CMOS sensing device; and A plurality of conductive components are formed on the connection components.

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