CN101425799B - Protection circuit to prevent NMOS components from overvoltage - Google Patents

Abstract

The present invention provides a protection circuit for an NMOS component, comprising a series NMOS transistor and an adjustment circuit. The series NMOS transistor is connected in series between the NMOS component and an external voltage source. The adjustment circuit is coupled to the external voltage source, a first internal voltage source, and a gate of the series NMOS transistor, and is used to adjust the gate voltage of the series NMOS transistor according to the voltage of the external voltage source and the first internal voltage source, thereby protecting the NMOS component from an over-high voltage caused by the external voltage source.

Description

Protection circuit to prevent NMOS components from overvoltage

technical field

The invention relates to a protection circuit, in particular to a protection circuit for preventing NMOS components from being subjected to excessive high voltage.

Background technique

Due to advances in integrated circuit technology in recent years, the dimensions of CMOS transistor components have continued to shrink. In order to match the characteristics of small-sized components and reduce the power consumed by the CMOS transistor components, the power supply voltage supplied to the CMOS transistor components generally also decreases with the size of the components.

However, earlier IC chips still use higher supply voltages (eg, 5V). In order to cooperate with these circuits using higher supply voltages, circuits using lower supply voltages (such as 3.3V or 1.8V) must use special circuit architectures as interface circuits between high and low voltages. Please refer to FIG. 1 . FIG. 1 is an embodiment of an interface circuit in the prior art.

As shown in FIG. 1 , a series NMOS transistor NC is connected in series between the NMOS element ND and an external voltage source VEXT. The gate of transistor NC is usually coupled to the internal voltage source VINT of the integrated circuit to which it belongs. The function of the transistor NC is to provide a cross voltage between its drain and source, so as to prevent the NMOS component ND from being directly subjected to the excessive voltage that may be caused by the external voltage source VEXT.

Take the voltage of the external voltage source VEXT as 5V and the voltage of the internal voltage source VINT as 3.3V as an example. The source voltage of the transistor NC is usually lower than the gate voltage, and the voltage difference is the threshold voltage of the transistor NC itself. Therefore, when the gate voltage of transistor NC is 3.3V, the transistor The source voltage of NC will be approximately equal to 2.3V. In this case, the voltage across the drain and source of transistor NC is 2.7V. Since the cross-voltage is still within the tolerance range of the transistor NC, the transistor NC will not encounter the problem of over-voltage, and thus can play the function of protecting the device ND.

However, if the voltage of the external voltage source VEXT is 5V and the voltage of the internal voltage source VINT is reduced to 1.8V, the source voltage of the transistor NC will be approximately equal to 1V, and the voltage across the drain and source of the transistor NC will be 4V. In this case, the transistor NC is likely to be damaged due to excessive voltage, and thus loses the function of protecting the device ND.

Contents of the invention

To solve the above problems, the present invention provides a protection circuit. In the protection circuit of the invention, the voltage supplied to the gate of transistor NC is related to the voltage of the external/internal voltage source. More specifically, the voltage will be appropriately adjusted with the voltage variation of the external/internal voltage source. Therefore, the protection circuit of the present invention can maintain the transistor NC in a normal working state, thereby protecting the device ND from overvoltage caused by an external voltage source.

A preferred embodiment of the present invention is a protection circuit for NMOS devices, which includes a series-connected NMOS transistor and an adjustment circuit. The series NMOS transistor is connected in series between the NMOS element and an external voltage source. The adjusting circuit is coupled to the external voltage source, a first internal voltage source, and a gate of the series-connected NMOS transistor, and is used for adjusting the series-connected NMOS transistor according to voltages of the external voltage source and the first internal voltage source voltage of the gate, thereby protecting the NMOS device from an excessive voltage caused by the external voltage source.

Description of drawings

In order to make the above-mentioned and other purposes, features and advantages of the present invention more obvious and understandable, preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings:

Fig. 1 is the embodiment of an interface circuit in the prior art;

Fig. 2 is the schematic diagram of protection circuit of the present invention; And

3A, 3B, 4 and 5 are preferred embodiments of the adjustment circuit of the present invention.

Detailed ways

A preferred embodiment of the present invention is a protection circuit for NMOS devices. Please refer to FIG. 2, which is a schematic diagram of the protection circuit. In this embodiment, the protection circuit 20 is used to prevent the NMOS device ND from being subjected to excessive voltage, and includes a series-connected NMOS transistor NC and an adjustment circuit 22 .

The transistor NC is connected in series between the device ND and an external voltage source VEXT. The adjustment circuit 22 is coupled to the external voltage source VEXT, a first internal voltage source VINT, and the gate of the transistor NC, and is used to adjust the gate of the transistor NC according to the voltages of the external voltage source VEXT and the first internal voltage source VINT. pole voltage.

According to the present invention, when the voltage of the external voltage source VEXT is less than or equal to the voltage of the first internal voltage source VINT, the adjusting circuit 22 can make the voltage of the gate of the transistor NC approximately equal to the voltage of the first internal voltage source VINT. When the voltage of the external voltage source VEXT is higher than the voltage of the first internal voltage source VINT, the adjustment circuit 22 can moderately increase the gate voltage of the transistor NC to reduce the cross voltage between the drain and the source of the transistor NC. In this way, the adjustment circuit 22 can prevent the transistor NC from being damaged due to excessive voltage. The protection circuit 20 is in turn able to protect the component ND from overvoltage caused by the external voltage source VEXT.

Take the voltage of the first internal voltage source VINT as 1.8V as an example. If the voltage of the external voltage source VEXT is 0-1.8V, the adjusting circuit 22 can make the voltage of the gate of the transistor NC be 1.8V. In contrast, if the voltage of the external voltage source VEXT is 1.8-5V, the adjustment circuit 22 can increase the voltage supplied to the gate of the transistor NC to 1.8V-3.3V. At this time, the voltage of the gate of the transistor NC is equal to the external voltage The voltage of source VEXT has a proportional relationship.

Please refer to FIG. 3A . FIG. 3A is a preferred embodiment of the adjustment circuit 22 . In this embodiment, the voltage of the first internal voltage source VINT is assumed to be 1.8V; the adjustment circuit 22 includes a voltage divider 22A, a switch 22B and a second PMOS transistor P2. The voltage divider 22A is coupled between the external voltage source VEXT and a second internal voltage source (ground). The voltage divider 22A in this embodiment is composed of MOS transistors; in practical applications, the constituent components of the voltage divider 22A are not limited thereto. In addition, the switch 22B is coupled between the external voltage source VEXT and the gate of the transistor P2. The source and the drain of the transistor P2 are respectively coupled to the first internal voltage source VINT and the gate of the transistor NC.

The switch 22B in this embodiment includes a third: PMOS transistor P3 and a first NMOS transistor N1 coupled in the form of a transmission gate. The gates of the transistor P3 and the transistor N1 are both coupled to the first internal voltage source VINT. When the voltage of the external voltage source VEXT is between 0-1.8V, the voltage of the gate of the transistor P2 will be slightly lower than 1.8V. Due to the small voltage difference between the gate and source of transistor P2, transistor P2 will be in a linear or sub-threshold state; the voltage at the gate of transistor NC will thus be charged to 1.8 V. Since the voltage of the external voltage source VEXT is not higher than 1.8V, in this case, the transistor NC will not encounter the problem of overvoltage, so it can play the function of protecting the device ND.

The divided voltage provided by the voltage divider 22A to the gate of the transistor NC varies with the voltage of the external voltage source VEXT. By properly designing the resistance of each component in the voltage divider 22A, when the voltage of the external voltage source VEXT is 5V, the divided voltage provided by the voltage divider 22A to the gate of the transistor NC can be set to 3.3V. In this case, the voltage at the source of the transistor NC is approximately equal to 2.3V, and the voltage across the drain and source of the transistor NC is approximately equal to 2.7V. Since the cross-voltage value is still within the range that the transistor NC can withstand, the transistor NC can also work normally and play the function of protecting the component ND. In addition, when the voltage of the external voltage source VEXT is 5V, the voltage of the gate of the transistor P2 is approximately equal to 5V; the transistor P2 is thus turned off.

Please refer to FIG. 3B , which is another preferred embodiment of the adjustment circuit 22 . In this embodiment, the adjustment circuit 22 further includes a first PMOS transistor P1 and an ESD protection resistor RESD. The electrostatic protection resistor RESD is used to prevent the circuit connected to the external voltage source VEXT from being damaged by electrostatic charges.

The gate, source and drain of the transistor P1 are respectively coupled to the first internal voltage source VINT, the external voltage source VEXT, and the voltage divider 22A. When the voltage of the external voltage source VEXT is between 0 and 1.8V, the transistor P1 will be turned off. Therefore, when the voltage divider 22A is a resistor embodiment and the external voltage source VEXT is 0, it can prevent the gate of the transistor NC from being connected to the external voltage. A leakage current path is created between the source VEXT, causing the gate voltage of the transistor NC to be affected.

Please refer to FIG. 4 , which is another preferred embodiment of the adjustment circuit 22 . In this embodiment, the two ends of the voltage divider 22A are respectively connected between the external voltage source VEXT and the first internal voltage source VINT. Therefore, when the voltage of the external voltage source VEXT is lower than 1.8V (that is, when the transistor P2 is turned on), the voltage divider 22A will not provide a leakage path between the first internal voltage source VINT and the original ground.

In practical applications, when the voltage of the first internal voltage source VINT is 1.8V, due to the sub-threshold current, the gate voltage of the transistor P2 may be charged to 1.8V; the transistor P2 may therefore be turned off and cause The voltage at the gate of transistor NC enters an indeterminate state. To prevent this from happening, the adjustment circuit 22 may further include a second NMOS transistor N2 and a third NMOS transistor N3. Please refer to FIG. 5 , which is a schematic diagram corresponding to the adjustment circuit 22 . Transistors N2 and N3 provide a small leakage path between the gate of transistor P2 and ground, keeping the gate of transistor P2 at a state slightly lower than 1.8V to solve the above-mentioned problem that transistor P2 may be turned off.

As described above, in the protection circuit of the present invention, the voltage supplied to the gate of the transistor NC is adaptively adjusted according to the voltage of the external/internal voltage source. Thereby, the protection circuit of the present invention can ensure that the transistor NC maintains a normal state, so as to protect the device ND from overvoltage caused by the external voltage source.

The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent modifications or replacements without departing from the spirit of the present invention. , these equivalent modifications or replacements are all included within the scope defined by the claims of the present application.

Claims (8)

1. one kind in order to avoid a NMOS assembly to bear the protective circuit of too high voltages, it is characterized in that, comprises:

One series connection nmos pass transistor is serially connected with between a described NMOS assembly and the external voltage source; And

One adjusts circuit; be coupled to described external voltage source; one first internal source voltage; an and grid of described series connection nmos pass transistor; in order to voltage according to described external voltage source and described first internal source voltage; adjust the voltage of the described grid of described series connection nmos pass transistor; protect described NMOS assembly to avoid bearing a too high voltages that causes because of described external voltage source whereby; wherein said adjustment circuit comprises a voltage divider; described voltage divider is coupled between described external voltage source and one second internal source voltage; when the voltage of described external voltage source is higher than the voltage of described first internal source voltage, described voltage divider offers a dividing potential drop the described grid of described series connection nmos pass transistor.

2. protective circuit as claimed in claim 1; it is characterized in that: described adjustment circuit further comprises one the one PMOS transistor; the transistorized grid of a described PMOS is coupled to described first internal source voltage; the transistorized one source pole of a described PMOS is coupled to described external voltage source, and the transistorized drain electrode of a described PMOS is coupled to described voltage divider.

3. one kind in order to avoid a NMOS assembly to bear the protective circuit of too high voltages, it is characterized in that, comprises:

One series connection nmos pass transistor is serially connected with between a described NMOS assembly and the external voltage source; And

One adjusts circuit; be coupled to described external voltage source; one first internal source voltage; an and grid of described series connection nmos pass transistor; in order to voltage according to described external voltage source and described first internal source voltage; adjust the voltage of the described grid of described series connection nmos pass transistor; protect described NMOS assembly to avoid bearing a too high voltages that causes because of described external voltage source whereby; wherein said adjustment circuit comprises a voltage divider; described voltage divider is coupled between described external voltage source and described first internal source voltage; when the voltage of described external voltage source is higher than the voltage of described first internal source voltage, described voltage divider offers a dividing potential drop the described grid of described series connection nmos pass transistor.

4. protective circuit as claimed in claim 3; it is characterized in that: described adjustment circuit further comprises one the one PMOS transistor; the transistorized grid of a described PMOS is coupled to described first internal source voltage; the transistorized one source pole of a described PMOS is coupled to described external voltage source, and the transistorized drain electrode of a described PMOS is coupled to described voltage divider.

5. one kind in order to avoid a NMOS assembly to bear the protective circuit of too high voltages, it is characterized in that, comprises:

One series connection nmos pass transistor is serially connected with between a described NMOS assembly and the external voltage source; And

One adjusts circuit; be coupled to described external voltage source; one first internal source voltage; an and grid of described series connection nmos pass transistor; in order to voltage according to described external voltage source and described first internal source voltage; adjust the voltage of the described grid of described series connection nmos pass transistor; protect described NMOS assembly to avoid bearing a too high voltages that causes because of described external voltage source whereby; wherein said adjustment circuit comprises a switch and one the 2nd PMOS transistor; described switch is coupled between described external voltage source and the transistorized grid of described the 2nd PMOS; the transistorized one source pole of the 2nd PMOS is coupled to described first internal source voltage; the transistorized drain electrode of the 2nd PMOS is coupled to the described grid of described series connection nmos pass transistor; when the voltage of described external voltage source is lower than the voltage of described first internal source voltage, described switch makes described the 2nd PMOS transistor turns.

6. protective circuit as claimed in claim 5; it is characterized in that: described switch comprises one the 3rd PMOS transistor and one first nmos pass transistor of the transmission gate form that is coupled to, and a grid of transistorized grid of described the 3rd PMOS and described first nmos pass transistor all is coupled to described first internal source voltage.

7. protective circuit as claimed in claim 5; it is characterized in that: described adjustment circuit further comprises one second nmos pass transistor and one the 3rd nmos pass transistor; one grid of described second nmos pass transistor is coupled to the described grid of described series connection nmos pass transistor; one drain electrode of described second nmos pass transistor is coupled to the transistorized grid of described the 2nd PMOS; the one source pole of described second nmos pass transistor is coupled to a drain electrode of described the 3rd nmos pass transistor, and the one source pole of described the 3rd nmos pass transistor and a grid all are coupled to one second internal source voltage.

8. as each described protective circuit in the claim 1,3,5, it is characterized in that: be coupled with an electrostatic defending resistance between described external voltage source and the described adjustment circuit.

Images