CN101459046B - Test construction for light doped drain doping region square resistor and manufacturing method thereof - Google Patents
Test construction for light doped drain doping region square resistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN101459046B CN101459046B CN2007100945580A CN200710094558A CN101459046B CN 101459046 B CN101459046 B CN 101459046B CN 2007100945580 A CN2007100945580 A CN 2007100945580A CN 200710094558 A CN200710094558 A CN 200710094558A CN 101459046 B CN101459046 B CN 101459046B
- Authority
- CN
- China
- Prior art keywords
- region
- ldd
- doped region
- layer
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000010276 construction Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 238000005530 etching Methods 0.000 claims abstract description 30
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 144
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 claims description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000002349 favourable effect Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000002513 implantation Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A manufacturing method for a test structure of an LDD doped region square resistance comprises steps of providing a semiconductor substrate with a grid layer, wherein the semiconductor substrate is provided with a first region and a second region, patterning the grid layer, forming a grid electrode on the second region and at least two grid electrode on the first region, executing an LDD doping process to form LDD doped regions respectively in the semiconductor substrate between the grid electrodes of the first region and on the semiconductor substrate on two sides of the grid electrode of the second region, forming dielectric layers on the semiconductor substrate on the grid electrodes, on the lateral walls of the grid electrodes and between the grid electrodes, etching to remove the dielectric layers on the top of the grid electrodes and remaining a part of or the total dielectric layers on the LDD doped region of the first region. The invention further provides a test structure of an LDD doped region square resistance, which can be favorable for increasing testing precision of the LDD doped region square resistance.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a structure for testing square resistance of a lightly doped drain doping region and a manufacturing method thereof.
Background
With the continuous development of the complementary metal oxide semiconductor transistor manufacturing technology, the integration level is higher and higher, the line width of the gate is smaller and smaller, and the length of the conductive channel below the gate is also reduced continuously.
In order to avoid or suppress the leakage current between the source and the Drain caused by the shortened length of the conductive channel, a Lightly Doped Drain (LDD) implantation process is introduced, i.e., shallow junction implantation is performed with ions having a larger molecular weight before heavy doping of the source and the Drain.
In the LDD process, the implantation energy is required to be low, the junction depth is shallow, and the square resistance after implantation is as small as possible. U.S. patent application No. US7105427 discloses a method of shallow junction implantation, in which a semiconductor substrate surface is bombarded by high-energy ions to generate more holes on the semiconductor substrate surface; then, boron ion implantation is carried out; then, carrying out an annealing process; the holes in the surface of the semiconductor substrate can prevent boron ions from being implanted too deeply during implantation.
While the skilled artisan is studying how to form the shallow junction LDD doping layer, it is also necessary to study how to test the sheet resistance of the formed LDD doping layer to determine whether the LDD doping process meets the requirements.
When the square resistance measurement is carried out on the LDD doped region, a test structure of the LDD doped region is required to be formed firstly; generally, in order to save cost and time, different layers or structures of a semiconductor device are formed in different regions of a semiconductor substrate to form a test semiconductor substrate, so that the entire manufacturing process of the semiconductor device can be comprehensively tested, for example, a gate is formed in a first region of the semiconductor substrate, an LDD doped region is formed in a second region, and a metal interconnection line is formed in a third region.
Fig. 1 to 4 are schematic structural views corresponding to steps of a conventional method for forming a test semiconductor substrate including an LDD doped region sheet resistance test structure.
Referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 having a first region 102, a second region 104, and a third region and a fourth region (not shown).
Referring to fig. 2, an N-well 108 and a P-well 110 are doped in the second region 104, and a P-well 112 is formed in the first region 102 at the same time as the P-well 110 is formed.
Referring to fig. 3, a gate 117 is formed on the N-well 108 region, a gate 115 is formed on the P-well 110 region, and a gate dielectric layer (not shown) is disposed between the gate 117, the gate 115 and the semiconductor substrate 110.
Referring to fig. 4, PLDD doped regions 116 are formed in the N-well 108 on both sides of the gate 117, NLDD doped regions 114 are formed in the P-well 110 on both sides of the gate 115, and NLDD doped regions 118 are formed in the P-well 112 of the first region 102 at the same time as the NLDD doped regions 114 are formed. Next, a sidewall layer (not shown) is formed on sidewalls of the gate electrode 117 and the gate electrode 115.
Then, a contact plug and a subsequent metal interconnect layer (not shown) are formed.
The NLDD doped region 118 formed in the first region 102 is used to test the sheet resistance to detect whether the NLDD doping process meets the requirement.
However, since the NLDD doped region has a small thickness (i.e., a shallow junction depth), it is easily affected by other processes, for example, by performing an acid solution cleaning process, a plasma etching process, etc. on the layer or structure on the second region 104, a defect (Film Lost) such as surface damage and Film loss of the NLDD doped region may be caused, which affects the test precision of the sheet resistance of the NLDD doped region, thereby affecting the detection precision of the NLDD doped region; when the square resistance of the NLDD doped region is detected not to meet the requirement, whether the square resistance is caused by the NLDD doped process or the NLDD doped region defect cannot be determined.
Disclosure of Invention
The invention provides a test structure of a square resistor of an LDD doped region and a manufacturing method thereof, which are beneficial to improving the measurement precision of the square resistor of the LDD doped region.
The invention provides a manufacturing method of a test structure of square resistance of an LDD doped region, which comprises the following steps:
providing a semiconductor substrate with a gate layer, wherein the semiconductor substrate is provided with a first region and a second region;
patterning the gate layer, forming a gate in the second region, and forming at least two gates in the first region;
performing an LDD doping process to form LDD doped regions in the semiconductor substrate on both sides of the gate of the second region and in the semiconductor substrate between the gates of the first region;
forming dielectric layers on the grid electrode, the side wall and the semiconductor substrate between the grid electrodes;
and etching to remove the dielectric layer on the top of the grid, reserving the dielectric layers on the side walls of the grids of the first area and the second area, and reserving the dielectric layer with partial thickness or all the dielectric layers on the LDD doped area of the first area.
Optionally, when the distance between adjacent gates is less than or equal to 1.2 times of the target thickness of the formed dielectric layer,
and when the dielectric layer on the grid is removed by etching, etching the dielectric layer by using a plasma etching process until the dielectric layer on the grid is removed.
Optionally, when the distance between adjacent gates is greater than 1.2 times of the target thickness of the formed dielectric layer, in the process of removing the dielectric layer on the gate by etching, a mask layer is formed on the dielectric layer in the LDD doped region, and after the dielectric layer on the gate is removed, the mask layer is removed.
Optionally, the mask layer is a photoresist.
Optionally, the etching is anisotropic etching.
Optionally, the dielectric layer is silicon nitride, silicon oxide, or a combination thereof.
Optionally, the ion implanted by the LDD doping process is phosphorus or arsenic.
Optionally, the ion implanted by the LDD doping process is boron or boron difluoride.
Optionally, the method for forming the dielectric layer is chemical vapor deposition or atomic layer deposition.
The invention also provides a testing structure of the square resistance of the LDD doped region, which comprises the following steps:
a semiconductor substrate;
at least two gates on the semiconductor substrate;
side wall layers on two sides of the grid;
LDD doped regions in the semiconductor substrate between adjacent gates; wherein,
the LDD doped region is covered with a protective layer, and the material of the protective layer is the same as that of the side wall layer.
Optionally, the sidewall layer is one of silicon nitride, silicon oxide-silicon nitride, and silicon oxide-silicon nitride-silicon oxide.
Optionally, the LDD doped region is an NLDD type doped region.
Optionally, the impurity doped in the NLDD doping region is phosphorus or arsenic.
Optionally, the LDD doped region is a PLDD doped region.
Optionally, the impurity doped in the PLDD doping region is boron or boron difluoride.
Compared with the prior art, one of the technical schemes has the following advantages:
the protection layer is formed on the LDD doped region, the material of the protection layer is the same as that of the side wall layer, the LDD doped region can be protected from being influenced by other processes or external environment, particularly when the LDD doped region test structure and other test structures are manufactured together, after the LDD doped region is formed, certain damage can be caused to the surface of the LDD doped region by a subsequent cleaning process or a plasma etching process, the loss of a film layer of the LDD doped region is caused, the damage and/or the loss of the film layer on the surface of the LDD doped region can be avoided by forming the side wall layer material on the LDD doped region as the protection layer, the influence cannot be caused to the square resistance of the LDD doped region, and the square resistance of the LDD doped region can be truly reflected whether the LDD doped;
in addition, the manufacturing method of the LDD doped region sheet resistance test structure of the embodiment can be performed simultaneously with other test structures without additional processes and steps.
Drawings
Fig. 1 to 4 are schematic structural views corresponding to respective steps of a conventional method for forming a test semiconductor substrate;
FIG. 5 is a flowchart of an embodiment of a method for manufacturing a test structure for LDD doped region square resistance according to the present invention;
FIGS. 6 to 14 are schematic cross-sectional views of structures corresponding to steps of a method for manufacturing a test structure of LDD doped region square resistance according to an embodiment of the present invention;
FIG. 15 is a cross-sectional view of an embodiment of a testing structure for the sheet resistance of LDD doped regions according to the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
When the LDD doping process is detected, it is required to form an LDD doped region through the LDD doping process and measure the sheet resistance of the LDD doped region. Generally, to save time and cost, a plurality of test structures including LDD doping regions are formed on a semiconductor substrate in order to inspect the manufacturing process of the entire semiconductor device including the LDD doping process. The invention provides a manufacturing method of a test structure of a square resistor of an LDD doping area, which can be synchronously manufactured with other test structures and can protect the LDD doping area from being influenced by other manufacturing processes, so that the square resistor of the LDD doping area can accurately reflect whether the LDD doping process meets the requirements or not.
FIG. 5 is a flowchart illustrating a method for manufacturing a test structure for LDD doped region square resistance according to an embodiment of the present invention.
Referring to fig. 5, in step S100, a semiconductor substrate having a gate layer is provided, the semiconductor substrate having a first region and a second region.
The semiconductor substrate can be provided with an N well or a P well, and can also be provided with a shallow trench isolation structure. A gate layer is formed on the semiconductor substrate.
Step S110, patterning the gate layer, forming a gate in the second region, and forming at least two gates in the first region.
In one embodiment, the gate layer is patterned by photolithography and etching processes to form a gate electrode.
Step S120, performing an LDD ion implantation process to form LDD doped regions in the semiconductor substrate at both sides of the gate of the second region and in the semiconductor substrate between the gates of the first region.
The LDD doped region may be a PLDD doped region or an NLDD doped region.
Step S130, forming dielectric layers on the grid electrodes, on the side walls and on the semiconductor substrate between the grid electrodes.
The dielectric layer may be silicon oxide or silicon nitride or a combination thereof.
Step S140, etching to remove the dielectric layer on the top of the grid, reserving the dielectric layers on the side walls of the grids of the first area and the second area, and reserving the dielectric layer with partial thickness or all of the thickness on the LDD doped area of the first area.
The partial thickness or the whole dielectric layer reserved on the LDD doped region of the first region is used for protecting the LDD doped region of the first region, so that the LDD doped region is prevented from being damaged by other subsequent processes, such as a cleaning process, a plasma etching process and the like, and a Film layer loss (Film Lost) of the LDD doped region is avoided.
In the embodiment, the LDD doped regions in the first region are protected from other processes or external environments by forming the dielectric layer as a protection layer, particularly when the LDD doped region test structures of the first region are fabricated together with other test structures of the second region, after forming the LDD doped region of the first region, the subsequent cleaning process or plasma etching process may cause some damage to the surface of the LDD doped region of the first region, resulting in the loss of the LDD doped region film, and by forming a sidewall material as a protection layer on the LDD doped regions of the first region, can avoid the surface damage and/or film loss of the LDD doped region of the first region, and will not affect the sheet resistance of the LDD doped region of the first region, the square resistance of the LDD doping area of the first area can truly reflect whether the LDD doping process meets the requirement or not.
In addition, the manufacturing method of the LDD doped region sheet resistance test structure of the embodiment can be performed simultaneously with other test structures without additional processes and steps, except that the gate pattern is provided at a corresponding position on the mask plate so as to form a gate on the LDD doped region.
The following describes an embodiment of the method for manufacturing an LDD doped region sheet resistance test structure in detail with reference to the cross-sectional view, wherein other test structures are formed at the same time of manufacturing the LDD doped region sheet resistance test structure, and a gate test structure is formed in other regions for example.
Referring to fig. 6, a semiconductor substrate 10 for testing is provided, the semiconductor substrate 10 may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon, the semiconductor substrate 10 may also be a silicon germanium compound, and the semiconductor substrate 10 may further have a silicon-on-insulator structure or a silicon-on-silicon epitaxial layer structure.
The semiconductor substrate 10 is provided with a first area 12a and a second area 12b in the transverse direction, wherein the first area 12a is used for forming a gate test structure, and the second area 12b is used for forming an LDD doped region square resistance test structure.
The first region 12a further has a shallow trench isolation structure 14a therein, the second region 12b further has a shallow trench isolation structure 14b therein, the shallow trench isolation structure 14a is used for isolating the first region 12a from other regions, and the shallow trench isolation structure 14b is used for isolating an active region in the semiconductor substrate 10.
A third region and a fourth region (not shown) may be provided in the semiconductor substrate 10.
Referring to fig. 7, an N well 11 and a P well 13 are formed in the active region of the second region 12b, and a P well 15 is formed in the first region 12a at the same time as the P well 13 is formed.
Referring to fig. 8, a gate dielectric layer 16 is formed on the semiconductor substrate 10, the gate dielectric layer 16 is silicon oxide or silicon oxynitride, the method for forming silicon oxide is one of high temperature furnace oxidation, rapid thermal oxidation, and in-situ steam generation oxidation, and the thickness of the formed silicon oxide may be 5 to 100 nm. The silicon oxynitride can be formed by performing a nitridation process on the silicon oxide, wherein the nitridation process can be one of high-temperature furnace tube nitridation, rapid thermal annealing nitridation and plasma nitridation.
After the gate dielectric layer 16 is formed, a polysilicon layer 18 is formed on the gate dielectric layer 16 as a gate layer, and the thickness of the polysilicon layer 18 is determined according to the thickness of the gate to be detected. The method for forming the polysilicon layer 18 may be chemical vapor deposition or atomic layer deposition.
Alternatively, impurities may be doped into the polysilicon layer 18 to reduce the resistivity of the formed gate. For example, N-type impurities such as phosphorus or arsenic are doped in a region of the polysilicon layer 18 serving as an NMOS gate; a P-type impurity, such as boron, is doped in the region of the polysilicon layer 18 that serves as a PMOS gate.
In other embodiments, the polysilicon layer 18 may be a multilayer.
In other embodiments, the polysilicon layer 18 may also have a metal silicide layer thereon.
Referring to fig. 9, a photoresist layer is spin-coated on the polysilicon layer, and at least two gate patterns 20a are formed in the first region 12a by an exposure and development process, wherein the two gate patterns 20a are parallel or nearly parallel to each other; gate patterns 20b and 20c are formed in the second region 12b, the gate pattern 20b being located above the N-well 11, and the gate pattern 20c being located above the P-well 13.
Referring to fig. 10, the gate patterns 20a, 20b, and 20c are used as an etching mask layer to etch the polysilicon layer 18, form a gate 18a in the first region 12a, and form gates 18b and 18c in the second region 12b, where the etching is anisotropic etching, and in one embodiment, the etching is plasma etching, and the etching gas is a fluorine-containing gas, and the fluorine-containing gas may be CF4、CF4/O2、SF6、C2F6/O2、NF3One or a combination thereof. That is, the gates 18a, 18b, and 18c may be simultaneously formed by etching.
And continuously etching the gate dielectric layer 16 which is not covered by the gates 18a, 18b and 18c until the surface of the semiconductor substrate 10 between the gates 18a, 18b and 18c is exposed.
Next, the gate patterns 20a, 20b, 20c are removed.
Referring to fig. 11, first, the P- wells 13 and 15 are covered by a photoresist layer (not shown), and a PLDD doping process is performed on the N-well 11 at two sides of the gate 20b to form a PLDD doped region 22, wherein an impurity doped in the PLDD doping process may be boron or boron difluoride. And then, removing the photoresist layer.
Referring to fig. 12, the N-well 11 is covered by a photoresist layer (not shown), an NLDD doping process is performed, NLDD doping regions 24 are formed in the P-well 13 on both sides of the gate 18c, and NLDD doping regions 26 are formed in the P-well 15 on both sides of the gate 18 a. The impurity doped by the NLDD doping process is phosphorus or arsenic. And then, removing the photoresist layer.
After the NLDD and PLDD doping processes are completed, an annealing process is performed to activate the doped impurity ions.
Referring to fig. 13, a dielectric layer 28 is formed on the gates 18a, 18b and 18c, on the sidewalls and on the semiconductor substrate 10 between the gates 18a, 18b and 18c, wherein the dielectric layer 28 is continuous and wraps around the gates 18a, 18b and 18 c.
The dielectric layer 28 may be one of silicon nitride, silicon oxide, or a combination thereof, and may be, for example, a stacked structure of silicon oxide-silicon nitride (O-N), or a stacked structure of silicon oxide-silicon nitride-silicon oxide (O-N-O).
The method of forming the dielectric layer 28 may be chemical vapor deposition or atomic layer deposition.
Fig. 13 schematically illustrates only the dielectric layer 28 as silicon oxide.
Then, an etching process is performed, referring to fig. 14, in the second region 12b, the dielectric layers on the tops of the gates 18b and 18c and the dielectric layer on the semiconductor substrate 10 between the gates 18b and 18c are removed, but the dielectric layers on the sidewalls of the gates 18b and 18c are remained, and a sidewall layer 30 surrounding the sidewalls of the gates 18b and 18c is formed; in the second region 12a, the dielectric layer on the top of the gate 18a is removed, and the dielectric layer surrounding the sidewall of the gate 18a and the dielectric layer on the NLDD doped region in partial thickness or in whole are remained. The etching of the dielectric layers of the first region 12a and the second region 12b is performed simultaneously, and the etching is anisotropic etching.
In one embodiment, when the distance between the gates 18a is less than or equal to 1.2 times the target thickness of the dielectric layer 28 (where the target thickness is a thickness that needs to be formed to meet the electrical requirement of the formed semiconductor device), the minimum thickness of the dielectric layer 28 on the NLDD doped region 26 between the gates 18a is also greater than the target thickness of the dielectric layer 28 after the dielectric layer 28 is deposited due to the smaller distance between the gates 18a, and when the etching process is performed, the dielectric layer 28 may be completely exposed to the etching environment, and when the dielectric layer 28 on the gates 18a is just completely removed, the dielectric layer 28 with a residual thickness is included on the NLDD doped region 26 between the gates 18 a. That is, by forming the gates 18a with smaller spacing so that the minimum thickness of the dielectric layer 28 between the gates 20a is greater than the target thickness of the dielectric layer 28 after the dielectric layer 28 is deposited, the whole dielectric layer 28 is exposed to the etching environment when the etch-back process is performed, and the LDD doped region 26 between the gates 18a has a partial thickness of the dielectric layer 28a just after the dielectric layer on the gates 18a is removed by using the thickness difference between the minimum thickness of the dielectric layer 28 between the gates 18a and the thickness of the dielectric layer on the gates 18a (equal to or close to the target thickness). The dielectric layer 28a with a certain thickness serves as a protective layer to protect the LDD doped region from being damaged or causing film loss in other subsequent processes.
After the etching is completed, a test structure of the LDD doped region sheet resistance is formed, which includes the LDD doped region 26 and the protection layer thereon.
The method of the present embodiment can be manufactured simultaneously with other test structures without adding an additional process, except that the gate electrode 18a is patterned on the mask plate at a position corresponding to the first region 12a so as to form the gate electrode 18 a.
After the LDD doped region sheet resistance test structure shown in fig. 14 is formed in the first region 12a, other processes such as forming a silicide contact layer in the second region 12b, forming a plug in the first region 12a and the second region 12b, etc. are continuously performed. Because the protection layer is arranged on the LDD doping area 26, the subsequent process does not affect the LDD doping area 26, after the whole test piece is manufactured, the square resistance of the LDD doping area 26 is tested, and the square resistance can accurately reflect whether the LDD doping process condition meets the requirement or not. The defect that in the prior art, when the square resistance of the detected LDD doped region 26 does not meet the requirement, whether the square resistance is caused by the damage or thickness loss of the LDD doped region or the LDD doping process cannot be judged is overcome.
In another embodiment, when the distance between adjacent gates 18a is greater than 1.2 times the target thickness of the formed dielectric layer 28, a mask layer, which may be a photoresist, is formed on the dielectric layer 28 of the LDD doped region 26 in the process of etching to remove the dielectric layer 28 on the gates 18a, and is removed after removing the dielectric layer 28 on the gates 18 a.
The invention also provides a test structure of the square resistance of the LDD doped region. The LDD doped region square resistance test structure comprises a semiconductor substrate and at least two gates on the semiconductor substrate; side wall layers are arranged on two sides of the grid; an LDD doping area is arranged in the semiconductor substrate between the adjacent gates; and the LDD doped region is covered with the material of the side wall layer.
FIG. 15 is a cross-sectional view of an embodiment of a testing structure for the sheet resistance of LDD doped regions according to the present invention.
Referring to fig. 15, a semiconductor substrate 200 has a gate 206 thereon, sidewall layers 208 are formed around the sidewalls of the gate 206, LDD doped regions 203 are formed in the semiconductor substrate 200 between the gates 206, a protection layer 209 is further formed on the LDD doped regions 203 between the sidewall layers 208 of adjacent gates 206, and the protection layer 208 and the sidewall layers 209 are made of the same material.
Also in the semiconductor substrate are a P-well 201 and shallow trench isolation 202.
The sidewall layer 208 may be one of silicon nitride, silicon oxide-silicon nitride, and silicon oxide-silicon nitride-silicon oxide.
In one embodiment, the gate is polysilicon or a stacked structure of polysilicon and metal silicide.
In one embodiment, the LDD doped region is an NLDD type doped region. The impurity doped in the NLDD doped region is phosphorus or arsenic.
In one embodiment, the LDD doped region is a PLDD doped region. The impurity doped in the PLDD doped region is boron or boron difluoride.
In the structure for testing the square resistance of the LDD doped region of the present invention, the protection layer 209 is disposed on the LDD doped region 203 to protect the LDD doped region 203 from other manufacturing processes or external environments.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto, and variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.
Claims (13)
1. A manufacturing method of a test structure of square resistance of an LDD doped region is characterized by comprising the following steps:
providing a semiconductor substrate with a gate layer, wherein the semiconductor substrate is provided with a first region and a second region;
patterning the gate layer, forming a gate in the second region, and forming at least two gates in the first region;
performing an LDD doping process to form LDD doped regions in the semiconductor substrate on both sides of the gate of the second region and in the semiconductor substrate between the gates of the first region;
forming dielectric layers on the grid electrode, the side wall and the semiconductor substrate between the grid electrodes;
when the distance between adjacent grids is less than or equal to 1.2 times of the target thickness of the formed dielectric layer, etching the dielectric layer by using a plasma etching process in the process of etching and removing the dielectric layer on the grids until the dielectric layer on the grids is removed, reserving the dielectric layers on the side walls of the grids of the first area and the second area, and reserving the dielectric layer with partial thickness on the LDD doped area of the first area;
or when the distance between adjacent gates is larger than 1.2 times of the target thickness of the formed dielectric layer, in the process of removing the dielectric layer on the gates by etching, forming a mask layer on the dielectric layer of the LDD doped region of the first region, reserving the dielectric layers on the side walls of the gates of the first region and the second region, reserving all the dielectric layers on the LDD doped region of the first region, and removing the mask layer after removing the dielectric layer on the gate.
2. The method of claim 1 wherein the method further comprises the steps of: the mask layer is photoresist.
3. The method for manufacturing a structure for testing the sheet resistance of LDD doped regions as claimed in any one of claims 1 to 2, wherein: the etching is anisotropic etching.
4. The method for manufacturing a structure for testing the sheet resistance of LDD doped regions as claimed in any one of claims 1 to 2, wherein: the dielectric layer is silicon nitride, silicon oxide or a combination thereof.
5. The method for manufacturing a structure for testing the sheet resistance of LDD doped regions as claimed in any one of claims 1 to 2, wherein: the ions implanted by the LDD doping process are phosphorus or arsenic.
6. The method of fabricating a lateral test structure of LDD doped region square resistor as claimed in any of claims 1 to 2, wherein: the ions implanted by the LDD doping process are boron or boron difluoride.
7. The method for manufacturing a structure for testing the sheet resistance of LDD doped regions as claimed in any one of claims 1 to 2, wherein: the method for forming the dielectric layer is chemical vapor deposition or atomic layer deposition.
8. A kind of test structure of the square resistance of LDD doped region, characterized by that, including:
a semiconductor substrate;
at least two gates on the semiconductor substrate;
side wall layers on two sides of the grid;
LDD doped regions in the semiconductor substrate between adjacent gates; wherein,
the LDD doped region is covered with a protective layer, and the material of the protective layer is the same as that of the side wall layer.
9. The structure for testing the sheet resistance of an LDD doped region of claim 8, wherein: the side wall layer is one of silicon nitride, silicon oxide-silicon nitride and silicon oxide-silicon nitride-silicon oxide.
10. The structure for testing the sheet resistance of an LDD doped region of claim 8, wherein: the LDD doped region is an NLDD doped region.
11. The structure for testing the sheet resistance of an LDD doped region of claim 10, wherein: the impurity doped in the N LDD doped region is phosphorus or arsenic.
12. The structure for testing the sheet resistance of an LDD doped region of claim 8, wherein: the LDD doped region is a PLDD doped region.
13. The structure for testing the sheet resistance of LDD doped regions of claim 12, wherein: the impurity doped in the PLDD doped region is boron or boron difluoride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100945580A CN101459046B (en) | 2007-12-13 | 2007-12-13 | Test construction for light doped drain doping region square resistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100945580A CN101459046B (en) | 2007-12-13 | 2007-12-13 | Test construction for light doped drain doping region square resistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101459046A CN101459046A (en) | 2009-06-17 |
| CN101459046B true CN101459046B (en) | 2010-11-10 |
Family
ID=40769818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100945580A Expired - Fee Related CN101459046B (en) | 2007-12-13 | 2007-12-13 | Test construction for light doped drain doping region square resistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101459046B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101696992B (en) * | 2009-10-28 | 2013-03-27 | 上海宏力半导体制造有限公司 | Measurement method of base resistance of bipolar transistor |
| US8816715B2 (en) * | 2011-05-12 | 2014-08-26 | Nanya Technology Corp. | MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test |
| CN103137603B (en) * | 2011-11-23 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Under monitoring polysilicon side wall, light dope injects test structure and the method for stability |
| CN108878304A (en) * | 2018-06-28 | 2018-11-23 | 德淮半导体有限公司 | Leakage tests structure and leakage tests method |
| CN109309079B (en) * | 2018-09-18 | 2020-05-05 | 成都迈斯派尔半导体有限公司 | Semiconductor test structure, manufacturing method and square resistance measuring method |
| CN111223916B (en) * | 2020-01-13 | 2023-06-16 | 长江存储科技有限责任公司 | Semiconductor device and its manufacturing method and three-dimensional memory |
| CN114446812B (en) * | 2020-11-06 | 2024-09-27 | 长鑫存储技术有限公司 | Test structure and manufacturing method thereof |
| CN112992864B (en) * | 2021-02-20 | 2023-12-12 | 长江存储科技有限责任公司 | Semiconductor test structure and test method |
| CN114023698A (en) * | 2021-10-28 | 2022-02-08 | 武汉华星光电技术有限公司 | Manufacturing method of array substrate and display panel |
| CN117116915B (en) * | 2023-10-25 | 2024-01-19 | 合肥晶合集成电路股份有限公司 | Semiconductor structure, preparation method thereof and square resistance measuring method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933020A (en) * | 1996-10-16 | 1999-08-03 | Vlsi Technology, Inc. | Parasitic resistance measuring device |
| US6287877B1 (en) * | 2000-09-22 | 2001-09-11 | Advanced Micro Devices | Electrically quantifying transistor spacer width |
| US20060151817A1 (en) * | 2003-04-30 | 2006-07-13 | Won-Ho Lee | CMOS image sensor having test pattern therein and method for manufacturing the same |
-
2007
- 2007-12-13 CN CN2007100945580A patent/CN101459046B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933020A (en) * | 1996-10-16 | 1999-08-03 | Vlsi Technology, Inc. | Parasitic resistance measuring device |
| US6287877B1 (en) * | 2000-09-22 | 2001-09-11 | Advanced Micro Devices | Electrically quantifying transistor spacer width |
| US20060151817A1 (en) * | 2003-04-30 | 2006-07-13 | Won-Ho Lee | CMOS image sensor having test pattern therein and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101459046A (en) | 2009-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101459046B (en) | Test construction for light doped drain doping region square resistor and manufacturing method thereof | |
| JP4782821B2 (en) | Device structure having a self-aligned damage layer | |
| TWI613816B (en) | Semiconductor device and method of manufacturing same | |
| US20060276014A1 (en) | Self-aligned high-energy implantation for deep junction structure | |
| US8460993B2 (en) | Method for fabricating CMOS image sensor with plasma damage-free photodiode | |
| US8071415B2 (en) | Method of fabricating semiconductor device | |
| US20090096023A1 (en) | Method for manufacturing semiconductor device | |
| JP2012028562A (en) | Method of manufacturing semiconductor device | |
| TW201735120A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JP2010147247A (en) | Method of manufacturing semiconductor device | |
| CN101593728B (en) | Complementary metal oxide semiconductor (CMOS) device with stress membrane and manufacturing method thereof | |
| US6143595A (en) | Method for forming buried contact | |
| US20120052615A1 (en) | Method and structure for reducing dark current in a cmos image sensor | |
| KR101450436B1 (en) | Method for forming well of semiconductor device | |
| KR100559572B1 (en) | Method for manufacturing semiconductor device having salicide | |
| US20080048272A1 (en) | Silicidation monitoring pattern for use in semiconductor manufacturing process | |
| JP5205779B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| US7271414B2 (en) | Semiconductor device and method for fabricating the same | |
| US20080237740A1 (en) | Semiconductor device and the manufacturing method thereof | |
| TWI669786B (en) | Method for manufacturing semiconductor integrated circuit device | |
| KR100668509B1 (en) | Method of manufacturing semiconductor device having gate of asymmetric step structure | |
| CN100468752C (en) | Semiconductor element and manufacturing method thereof | |
| US8823138B1 (en) | Semiconductor resistor including a dielectric layer including a species creating fixed charges and method for the formation thereof | |
| JP2012049350A (en) | Method of manufacturing semiconductor device | |
| KR100591178B1 (en) | Manufacturing Method of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101110 Termination date: 20181213 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |