CN101471321B - Carrier tape and chip packaging structure for packaging chips - Google Patents

Abstract

The invention relates to a bearing belt for packaging a chip and a chip packaging structure, wherein a plurality of shared test pads are arranged in a test pad area between two packaging areas on the bearing belt to electrically connect the two packaging areas at the same time, so that the area of the test pad area on the bearing belt is reduced, the cutting waste can be reduced, the repeated actuation time of an electrical testing device can be saved during electrical testing, and the testing efficiency is improved.

Description

Carrier tape and chip packaging structure for packaging chips

technical field

The invention relates to a carrier tape and a chip packaging structure for packaging chips; in particular, a carrier tape and a chip packaging structure with a common test pad area.

Background technique

With the advancement of industry, various liquid crystal screens and electronic products with folding functions have been widely used in daily life. Among them, because the flexible circuit board has the advantages of thin thickness, small pin spacing, and high number of pins, when the LCD screen is to save space, or the electronic product is to achieve the function of folding, the flexible circuit board becomes indispensable. missing components.

Generally speaking, the flexible circuit board utilizes chip packaging technology to bond semiconductor chips thereon. Among them, the tape automatic bonding package (Tape Automatic Bonding, TAB) technology is to fix the chip on the carrier tape, and use the bumps or pads of the chip to align with the metal lead layer of the carrier tape. One of the common chip packaging technologies. It can be divided into two types of packaging: Tape Carrier Package (TCP) and Chip-On-Film (COF).

Fig. 1 shows the schematic diagram of existing chip package structure 1, and chip package structure 1 comprises carrying tape 10, and carrying tape 10 has a plurality of positioning holes 111, a plurality of test pads 131, 131 ', first pin part 141 and The second pin portion 142 . Wherein, a plurality of positioning holes 111 are distributed on two sides of the carrier tape 10 along a conveying direction X, for conveying the carrier tape 10, or for positioning the position of the carrier tape 10, so that the chip 21 is bonded to the carrier tape 10 is connected to or connected to an electrical testing device (not shown) for electrical testing.

For convenience of description, as shown in Figure 1, a package area 121 and two test pad areas 13, 13' respectively located on both sides of the package area 121 are defined on the carrier tape 10, wherein the package area 121 is arranged on the carrier tape 10 two sides. Between the positioning holes 111 on the side and distributed along the conveying direction X, the chip 21 is arranged in the package area 121, and the test pads 131, 131' are respectively arranged in the first test pad area 13 and the second test pad area 13 'superior. The first pin portion 141 extends from the packaging area 121 to the first test pad area 13 and is electrically connected to the test pad 131, and the second pin portion 142 extends from the packaging area 121 to the second test pad area 13' and the test pad. 131' is electrically connected.

Since the chip 21 is bonded to the packaging area 121 of the carrier tape 10, and is electrically connected to the first lead portion 141 and the second lead portion 142 with an input end and an output end (not shown) respectively, to form the chip package Structure 1. In this way, the input end and the output end of the chip 21 can be electrically connected to the test pad 131 of the first test pad area 13 and the second test pad area 13 through the first pin portion 141 and the second pin portion 142 respectively. 'Test Pad 131'. After the chip 21 is packaged in the package area 121 of the carrier tape 10, the chip 21 can be electrically tested once the electrical test device electrically connects the test pad 131 and the test pad 131' simultaneously with a probe.

It can be clearly seen from FIG. 1 that in the existing chip packaging structure 1, the test pads 131, 131' are arranged on two sides of each chip 21 respectively. After the electrical test of the chip 21 is completed, the first test pad area 13 and the second test pad area 13' all need to be cut and removed, leaving only the chip 21 on the package area 121, the first lead portion 141 and the second test pad area 141. Pin section 142. Conceivably, if the area used by the first test pad area 13 and the second test pad area 13' is larger, more parts will be cut and removed, which will cause unnecessary waste of the carrier tape 10. In addition, in the existing chip packaging structure 1, when performing an electrical test on the chip 21, the probes of the electrical testing device are sequentially and repeatedly electrically connected to the test pad 131 and the test pad 131', The electrical test needs to move the probes repeatedly, resulting in a large amount of process time and poor production test efficiency.

In view of this, it is an urgent problem to be solved in this field to provide a carrier tape and a chip packaging structure that can reduce the amount of cutting and improve the testing efficiency.

Contents of the invention

An object of the present invention is to provide a carrier tape and a chip packaging structure for packaging chips. Two adjacent chip packaging structures can share a test pad area to reduce the area ratio of the test pad area on the carrier tape. Since the test pad area will be cut and removed eventually, when the carrier tape and the chip package structure of the present invention are cut after the test is completed, the waste of the carrier tape caused by cutting the test pad area can be reduced, thereby saving the manufacturing cost.

Another object of the present invention is to provide a carrier tape and a chip packaging structure for packaging chips. Since adjacent two-chip packaging structures can be electrically connected to an electrical testing device through a shared test pad area, the electrical performance is improved. The test device can conduct electrical tests on the two chips simultaneously or independently, which can at least reduce the repeated contact and separation between the probes of the test machine and the test pads, thereby saving the working time of electrical tests and improving the efficiency of production testing.

To achieve the above purpose, the carrier tape provided by the present invention at least includes two transmission areas, two packaging areas, a test pad area, a plurality of test pads and a metal circuit layer. The transmission areas are respectively defined on the two sides of the carrier tape and extend along a conveying direction; the second packaging area is defined between the conveying areas and distributed along the conveying direction; the test pad area is defined on the second packaging Between the areas, the test pads are arranged on it; the metal circuit layer is distributed on the two packaging areas. Wherein, the second packaging area includes a first packaging area and a second packaging area, and the metal circuit layer at least includes a first pin portion extending from the first packaging area to the test pad area, and a The second package area extends to the second pin portion of the test pad area. The feature is that the first pin portion and the second pin portion are correspondingly connected to the common test pads in the test pad area.

The present invention also provides a chip packaging structure, which uses the above-mentioned carrier tape, and further includes a first chip and a second chip, which are respectively arranged in the first packaging area and the second packaging area of the carrier tape. , the first chip is electrically connected to the first pin portion, and the second chip is electrically connected to the second pin portion. Thereby, the first chip and the second chip are simultaneously connected to the corresponding test pads through the first pin portion and the second pin portion, so that the first chip and the second chip can be connected to the corresponding test pads through these The test pad is simultaneously connected to the electrical testing device for electrical testing.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of an existing chip packaging structure;

Figure 2 is a schematic diagram of the carrier tape of the present invention; and

Fig. 3 is a schematic diagram of the chip packaging structure of the present invention.

Description of main component symbols:

1 Chip package structure 10 Carrier tape

111 Positioning hole 121 Package area

13 The first test pad area 13 The second test pad area

131 Test Pad 131’ Test Pad

141 First pin part 142 Second pin part

21 Chip 3 Carrying tape

31 Transmission area 311 Positioning hole

321 First package area 321a Chip bonding area

322 second package area 322a chip bonding area

33 Test pad area 331 Test pad

341 first pin part 341a first inner pin

341b The first outer pin 342 The second pin part

342a second inner pin 342b second outer pin

343 Third Pin Section 344 Fourth Pin Section

4 Chip package structure 41 The first chip

42 The second chip X conveying direction

Detailed ways

An embodiment of the present invention discloses a carrier tape 3 for packaging chips, which can extend along a conveying direction X. As shown in FIG. , a test pad area 33 , a plurality of test pads 331 and a metal circuit layer disposed on the test pad area 33 .

In this embodiment, the two transmission areas 31 of the carrier belt 3 are respectively defined on the two sides of the carrier belt 3 and extend along the conveying direction X. , and adjacent to a plurality of positioning holes 311 disposed on two sides of the carrier belt 3 . The carrier tape 3 is transported and positioned through the positioning hole 311. For example, when the carrier tape 3 is positioned at one position, it is suitable for chip packaging, and then positioned at another position for cutting.

For convenience of description, the encapsulation areas 321 and 322 can be divided into a first encapsulation area 321 and a second encapsulation area 322 defined between the two transmission areas 31 . It should be noted that the packaging areas on the carrier tape 3 are sequentially distributed along the conveying direction X, and this embodiment only focuses on two adjacent packaging areas as an example, and is not intended to limit the present invention. Wherein, the first packaging area 321 and the second packaging area 322 each include a chip bonding area 321a and 322a for chip placement.

Different from the test pad area in the prior art, which corresponds to the packaging area alone, there must be two test pad areas between the two adjacent packaging areas. In this embodiment, only the first packaging area 321 and the second packaging area 322 A common test pad area 33 is provided. Since each test pad area 33 arranged on the carrier tape 3 must be cut and removed after the chip is packaged in each chip bonding area 321a and 322a and the packaging test is completed, the present embodiment uses a common test pad area 33, The number and area of the test pad area 33 can be greatly reduced, and the unnecessary waste of the packaging carrier tape can be significantly reduced, thereby reducing the packaging cost.

In addition, the metal wiring layer is distributed on the first packaging area 321 and the second packaging area 322, and extends to the test pad area 33. For the convenience of illustration, the metal wiring layer can be defined to include the first pin portion 341, the second pin portion The foot part 342 , the third pin part 343 and the fourth pin part 344 . In this embodiment, the first lead portion 341 extends from the first package area 321 to the test pad area 33, and the second lead portion 342 extends from the second package area 322 to the test pad area 33, and The first pin portion 341 and the second pin portion 342 are respectively connected to the corresponding test pads 331 in the test pad area 33 . In this way, only one common test pad area 33 is used between the first packaging area 321 and the second packaging area 322 , which can be used for subsequent electrical testing.

Preferably, the first pin portion 341 and the second pin portion 342 of the present invention have the same number of pins, so each pin of the first pin portion 341 and each pin of the second pin portion 342 The feet can be connected to the corresponding test pads 331 respectively, which is more convenient for conducting electrical tests.

In addition, the third lead portion 343 is disposed on the other side of the chip bonding area 321a in the first package area 321 relative to the first lead portion 341, and extends from the first package area 321 to another and other packages. area (not shown) common test pad area; and the fourth pin part 344 is the other side of the chip bonding area 322a that is arranged in the second packaging area 322 relative to the second pin part 342, and from the second The package area 322 extends to another test pad area shared with other package areas (not shown).

And for bonding with the chip and connecting the test pad 331, the first pin portion 341 includes a first inner pin 341a and a first outer pin 341b, and the second pin portion 342 includes a second inner pin 342a and a first outer pin 341b. The second outer pin 342b. The first inner pins 341a and the second inner pins 342a respectively extend in the chip bonding regions 321a and 322a for bonding with the bumps of the chip respectively. The first external pin 341 b and the second external pin 342 b respectively extend from the first package area 321 and the second package area 322 into the test pad area 33 , and are electrically connected to the corresponding test pad 331 . Each chip packaged in each packaging area 321, 322 is electrically connected to the inner pins 341a and 342a through a plurality of bumps of each chip, and is electrically connected to the test pad area 33 through the outer pins 341b, 342b. The test pad 331 is used for subsequent electrical testing through the test pad 331 . Similarly, the aforementioned third pin portion 343 and fourth pin portion 344 also include inner and outer pins respectively, which will not be repeated here.

Please refer to FIG. 3 , which shows a schematic diagram of a chip package structure 4 disclosed in the second embodiment of the present invention. This chip package structure 4 includes the carrier tape 3 as described above, and the first chip 41 and the second chip 42 is engaged on the carrier belt 3 . The first chip 41 and the second chip 42 are respectively disposed on the chip bonding areas 321a and 322a in the first package area 321 and the second package area 322 on the carrier tape 3 (as shown in FIG. 2 ). The first pin portion 341 includes a first inner pin 341a and a first outer pin 341b, the second pin portion 342 includes a second inner pin 342a and a second outer pin 342b, the first inner pin 341a and the first outer pin 341b The two inner pins 342a are respectively in the chip bonding areas 321a, 322a, and are electrically connected to the bumps of the first chip 41 and the second chip 42 respectively, and the first outer pins 341b and the second outer pins 342b are respectively connected independently The first encapsulation area 321 and the second encapsulation area 322 extend into the test pad area 33 and are electrically connected to the corresponding test pads 331 . Other detailed structures of the carrying belt 3 are the same as the above-mentioned structure of the carrying belt 3 , and will not be repeated here.

The test pad 331 on the test pad area 33, after the first chip 41 and the second chip 42 are respectively bonded to the first packaging area 321 and the second packaging area 322 to complete packaging, an electrical testing device (not shown) can be connected externally. , to perform an electrical test on the first chip 41 and the second chip 42 . And because the first pin portion 341 and the second pin portion 342 are connected to the same test pad 331, when the different chips packaged in the first packaging area 321 and the second packaging area 322 are electrically tested, only The action of electrically connecting the test pad 331 to the electrical testing device is performed once, so the working time of the electrical testing can be saved, and the production efficiency can be significantly improved.

For example, the first pin part 341 is connected to an input terminal of the first chip 41 through the first inner pin 341a, and the second pin part 342 is connected to the second chip 42 through the second inner pin 342a. The third pin part 343 and the fourth pin part 344 of the carrier tape are respectively connected to an output end of the first chip 41 and an output end of the second chip 42 . In this way, the test pad 331 can be electrically connected to the input terminals of the first chip 41 and the second chip 42 at the same time. When the probe (not shown) of the electrical testing device is electrically connected to the test pad 331, the first chip 41 and the second The chip 42 performs an electrical test. Preferably, the first pin portion 341 and the second pin portion 342 may have the same number of pins, and be connected to the same number of test pads 331 as the first pin portion 341 or the second pin portion 342. The electrical testing device can test the first chip 41 and the second chip 42 at the same time or separately only by electrically connecting the test pad 331 once, and the electrical testing device does not need to frequently perform plugging and unplugging operations.

Alternatively, the first pin portion 341 is connectable to the output end of the first chip 41, the second pin portion 342 is connectable to the output end of the second chip 42, and the third pin portion 343 is connected to the first chip 41. The input terminal of the chip 41 , the fourth pin portion 344 is connected to the input terminal of the second chip 42 . In this way, the test pad 331 can be electrically connected to the output terminals of the first chip 41 and the second chip 42 at the same time, and the other structures are the same as the above-mentioned embodiments, and will not be repeated here.

In the above-mentioned embodiments of the present invention, the first chip 41 and the second chip 42 can be substantially the same chip or different chips, both of which can implement the concept of the present invention. It only needs to be designed to extend the first pin portion 341 and the second pin portion 342 to the common test pad area 33 and connect to the corresponding test pad 331 at the same time. For example, if the first chip 41 and the second chip 42 are the same two chips, it is only necessary to symmetrically arrange the same two chips on the carrier tape 3, and the adjacent sides of the chips can have the same number of chips. Therefore, the first pin portion 341 and the second pin portion 342 with the same number of pins can be easily used and electrically connected to the same number of test pads 331 at the same time. However, if the first chip 41 is different from the second chip 42, the purpose of using the common test pad area of the present invention can also be achieved through the design of the pins and test pads.

By virtue of the above-mentioned structure of the carrier tape 3, the carrier tape 3 can save the area of the carrier tape occupied by two test pad areas between adjacent packaging areas in the prior art, so that the carrier tape 3 needs to be cut after the electrical test. Fewer parts to remove allow better utilization of the carrier tape, resulting in material cost savings. After being bonded to the chip, the chip packaging structure 4 of the present invention can be connected to the electrical test device through the shared test pad area 33, and then perform electrical tests separately or simultaneously, and the electrical test device does not need to perform frequent plugging and unplugging operations. It can also save working time for electrical testing, significantly speed up production efficiency, and reduce production costs.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (12)

1. carrying band that is used for packaged chip, be suitable for extending along a throughput direction, this carrying brings to and includes two transmission regions less, two packaging areas, one test pad area, a plurality of testing cushion and a metallic circuit layer, described transmission region is defined in the dual side-edge of this carrying band respectively, and extend along this throughput direction, described two packaging areas are between described transmission region, distribute along this throughput direction, this test pad area is between described two packaging areas, for described testing cushion setting thereon, this metallic circuit layer is to be distributed on described two packaging areas, wherein, described two packaging areas comprise one first packaging area and one second packaging area, this metallic circuit layer comprises one first pin part and one second pin part at least, this first pin partly is to extend to this test pad area from this first packaging area, this second pin partly is to extend to this test pad area from this second packaging area, and this first pin part and this second pin part, be in this test pad area, the common described testing cushion of corresponding connection.

2. carrying band as claimed in claim 1 is characterized in that, the described testing cushion on this test pad area is suitable for an external testing electrical property device, to carry out a testing electrical property.

3. carrying band as claimed in claim 1 is characterized in that, this first pin part partly is the pin with equal number with this second pin.

4. carrying band as claimed in claim 1, it is characterized in that, this first packaging area and this second packaging area comprise a chip bonding area respectively, this first pin partly comprises pin and one first outer pin in one first, this second pin partly comprises pin and one second outer pin in one second, this first interior pin and this second interior pin are to extend respectively in this chip bonding area, this first outer pin and this second outer pin are to extend in this test pad area from this first packaging area and this second packaging area respectively, and the common described testing cushion of corresponding connection.

5. carrying band as claimed in claim 1, it is characterized in that, this metallic circuit layer also comprises one the 3rd pin part and one the 4th pin part, the 3rd pin partly is with respect to this first pin part, extend from this first packaging area, the 4th pin partly is with respect to this second pin part, and this second packaging area extends certainly.

6. chip-packaging structure is characterized in that comprising:

One carrying band, be suitable for extending along a throughput direction, this carrying brings to and includes two transmission regions less, two packaging areas, one test pad area, a plurality of testing cushion and a metallic circuit layer, described transmission region is defined in the dual side-edge of this carrying band respectively, and extend along this throughput direction, described two packaging areas are between described transmission region, distribute along this throughput direction, this test pad area is between described two packaging areas, for described testing cushion setting thereon, this metallic circuit layer is to be distributed on described two packaging areas, wherein, described two packaging areas comprise one first packaging area and one second packaging area, and this metallic circuit layer comprises one first pin part and one second pin part at least, and this first pin partly is to extend to this test pad area from this first packaging area, this second pin partly is to extend to this test pad area from this second packaging area, and this first pin part and this second pin part are in this test pad area, the common described testing cushion of corresponding connection; One first chip and one second chip, be arranged at respectively this carrying with on this first packaging area and this second packaging area, this first chip and this first pin partly electrically connect, and second chip and this second pin partly electrically connect.

7. chip-packaging structure as claimed in claim 6, it is characterized in that, described testing cushion on this test pad area, be suitable for an external testing electrical property device, to pass through this first pin part and this second pin part at the same time or separately, to this first chip and this second chip, carry out a testing electrical property.

8. chip-packaging structure as claimed in claim 6, it is characterized in that, this first packaging area and this second packaging area comprise a chip bonding area respectively, this first pin partly comprises pin and one first outer pin in one first, this second pin partly comprises pin and one second outer pin in one second, this first interior pin and this second interior pin are to extend respectively in this chip bonding area, this first outer pin and this second outer pin are to extend in this test pad area from this first packaging area and this second packaging area respectively, and the common described testing cushion of corresponding connection.

9. chip-packaging structure as claimed in claim 6 is characterized in that, this first pin partly is an input that is connected in this first chip, and this second pin partly is an input that is connected in this second chip.

10. chip-packaging structure as claimed in claim 9, it is characterized in that, this carrying band also comprises one the 3rd pin part and one the 4th pin part, and the 3rd pin partly is connected in an output of this first chip, and the 4th pin partly is connected in an output of this second chip.

11. chip-packaging structure as claimed in claim 6 is characterized in that, this first pin partly is an output that is connected in this first chip, and this second pin partly is an output that is connected in this second chip.

12. chip-packaging structure as claimed in claim 11, it is characterized in that, this carrying band also comprises one the 3rd pin part and one the 4th pin part, and the 3rd pin partly is connected in an input of this first chip, and the 4th pin partly is connected in an input of this second chip.

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