CN101483386B - DC to DC Converter - Google Patents

Abstract

A dc-to-dc converter comprising: the control circuit receives and compares the direct current output voltage, when the direct current output voltage does not exceed a first threshold voltage, the control circuit outputs a pulse width modulation signal with a first frequency, and when the direct current output voltage exceeds the first threshold voltage, the control circuit outputs a pulse width modulation signal with a second frequency, wherein the second frequency is greater than the first frequency; the gate driving circuit receives the pulse width modulation signal and converts the pulse width modulation signal into a first driving signal and a second driving signal; and the power level circuit converts the direct current input voltage into direct current output voltage according to the first driving signal and the second driving signal.

Description

DC to DC Converter

technical field

The present invention relates to a DC-to-DC converter, and in particular to a DC-to-DC converter and a control method for reducing overshoot. the

Background technique

As we all know, a DC-to-DC converter (DC-to-DC converter) can convert a DC input voltage (DC input voltage) into a DC output voltage (DC output voltage) of different magnitudes. the

Please refer to FIG. 1 , which is a schematic diagram of a known DC-to-DC converter. The DC-to-DC converter includes a control circuit 10 , a gate driver 20 , and a power stage 30 . Generally speaking, the control circuit 10 can receive the DC output voltage (Vout) generated by the power stage circuit 30, and generate a corresponding pulse width modulation signal (pulse width modulation signal, hereinafter) according to the change of the DC output voltage (Vout). Referred to as PWM signal). Moreover, the gate drive circuit 20 receives the PWM signal and converts it into a first drive signal and a second drive signal to the power stage circuit 30, and the power stage circuit 30 can convert DC The input voltage (Vin) is converted to a DC output voltage (Vout). the

Furthermore, the gate driving circuit 20 includes a first driver 22 and a second driver 24 . The first driver 22 receives the PWM signal and generates a first driving signal in phase with the PWM signal; and the second driver 24 receives the PWM signal and generates a second driving signal in phase opposite to the PWM signal. the

Moreover, the power stage circuit 30 includes an upper power transistor (upper power transistor) 32, a lower power transistor (lower power transistor) 34, an output inductor (Lo), and an output capacitor (Co). The drain of the upper power transistor 32 is connected to the DC input voltage (Vin), and the gate of the upper power transistor 32 receives the first driving signal. The drain of the lower power transistor 34 is connected to the source of the upper power transistor 32, the gate of the lower power transistor 34 receives the second driving signal, and the source of the lower power transistor 34 is connected to the ground terminal (GND). The first end of the output inductor (Lo) is connected to the source of the upper power transistor 32, and the second end of the output inductor (Lo) is the output end of the power stage circuit 30 for outputting a DC output voltage (Vout). Furthermore, two terminals of the output capacitor (Co) are respectively connected between the output terminal of the power stage circuit 30 and the ground terminal (GND). Generally speaking, when the DC input voltage (Vin) is greater than the DC output voltage (Vout), the DC-to-DC converter can be regarded as a step-down DC-to-DC converter (Buck DC-to-DC converter). the

For a step-down DC-to-DC converter, the first drive signal and the second drive signal generated by the gate drive circuit 20 can turn on (turn on) the upper power transistor 32 and the lower power transistor 34 respectively, and the upper power transistor 32 and the lower power transistor 34 can be turned on respectively. The power transistors 34 cannot be turned on at the same time. That is to say, when the upper power transistor 32 is turned on, the lower power transistor 34 is closed (turn off), and at this moment the second current (I2) is zero, and the output current Iout of the power stage circuit 30 is caused by turning on the upper power transistor 32 The generated first current (I1) is provided. On the contrary, when the lower power transistor 34 is turned on, the upper power transistor 32 is closed, and now the first current (I1) is zero, and the output current Iout of the power stage circuit 30 is the second current ( I2) provided. Generally speaking, when the DC output voltage (Vout) received by the control circuit 10 is lower than a default value (for example, 3.3V), the pulse width of the PWM signal will become wider. Therefore, the first driving signal generated by the gate driving circuit 20 can be The upper power transistor 32 is controlled to be turned on for a longer time, and the second driving signal is used to control the lower power transistor 32 to be turned off for a longer time. Conversely, when the DC output voltage (Vout) received by the control circuit 10 is higher than the default value (for example, 3.3V), the pulse width of the PWM signal will be narrowed, so the first drive signal generated by the gate drive circuit 20 can control the upper The power transistor 32 is turned on for a short time, and the second driving signal can control the power transistor 32 to be turned off for a short time. the

Furthermore, the control circuit 10 in the DC-to-DC converter has many control modes. Generally, there are voltage control mode (voltage mode), current control mode (current mode) and constant on-time control mode (constant on-time mode). The three control modes will be described in detail below, and the structures of the gate driving circuit 20 and the power stage circuit 30 are the same, so they will not be described again. the

Please refer to FIG. 2A , which is a schematic diagram of a DC-to-DC converter with a known voltage control mode. The DC-to-DC converter in voltage control mode includes: a control circuit 210 , a gate drive circuit 220 , and a power stage circuit 230 . Wherein, the control circuit 210 includes: an error amplifier (error amplifier) 212, a modulation unit (modulator) 214 and a signal generator (wave generator) 216. The error amplifier 212 receives the DC output voltage (Vout) and a reference voltage (Vref), and the error amplifier 212 can compare the DC output voltage (Vout) with the reference voltage (Vref) to generate a compensation signal (comp) to the modulation unit 214 . the

Furthermore, the signal generator 216 can output a sawtooth signal (ramp) of a first frequency to the modulation unit 214, so that the modulation unit 214 can generate a PWM signal according to the compensation signal (comp) and the ramp signal. Of course, the signal generator 216 can also output signals of other shapes, such as a triangle signal (triangle signal), in addition to the sawtooth signal (ramp). the

Please refer to FIG. 2B , which is a schematic diagram of a compensation signal (comp), a sawtooth signal (ramp), a PWM signal, a first signal, and a second signal in a DC-DC converter in voltage control mode. When the compensation signal (comp) is greater than the sawtooth signal (ramp), the PWM signal is at high level; otherwise, when the compensation signal (comp) is less than the ramp signal, the PWM signal is at low level. Obviously, when the compensation signal (comp) is changing, the pulse width of the PWM signal will also change accordingly. Furthermore, the first driving signal is in phase with the PWM signal, and the second driving signal is in phase opposite to the PWM signal. Both the frequency of the PWM signal and the frequency of the sawtooth signal are the first frequency. the

Please refer to FIG. 3A , which shows a DC-to-DC converter with a known current control mode. The DC-to-DC converter in current control mode includes: a control circuit 310 , a gate drive circuit 320 , and a power stage circuit 330 . Wherein, the control circuit 310 includes: an error amplifier 312, a PWM comparator (PWM comparator) 313, a signal generator 314, a current sense amplifier (current sense amplifier) 315, an adder (adder) 316, and an SR Latch (SR latch) 317. The error amplifier 312 receives the DC output voltage (Vout) and a reference voltage (Vref), and the error amplifier 312 can compare the DC output voltage (Vout) with the reference voltage (Vref) to generate a compensation signal (comp) to the PWM comparator 313 . the

Furthermore, the current sense amplifier 315 can detect the first current ( I1 ) flowing through the upper power transistor or the second current ( I2 ) flowing through the lower power transistor in the power stage circuit 330 . For example, the current sense amplifier 315 can convert the current (I1) of the upper power transistor into a sense signal (Vsense). the

Furthermore, the signal generator 314 can simultaneously output a ramp signal (ramp) and a clock signal (CLK), and the ramp signal (ramp) and the clock signal (CLK) have the same first frequency. The ramp signal (ramp) and the sensing signal (Vsense) are superposed by the adder 316 to become a sum signal (sum). The sum signal (sum) and the compensation signal (comp) are input to the PWM comparator 313 . When the sum signal (sum) is greater than the compensation signal (comp), the PWM comparator 313 will output a pulse to the reset terminal (reset terminal, R) of the SR latch 317 . Furthermore, the clock signal (CLK) is input to the set terminal (S) of the SR latch 317 . The PWM signal can be generated according to the signal changes of the reset terminal (R) and the set terminal (S) of the SR latch 317 . Of course, the signal generator 216 can also output signals of other shapes, such as a triangle signal (triangle signal), in addition to the sawtooth signal (ramp). the

Please refer to FIG. 3B, which shows the output current (Iout), the sense signal (Vsense), the sawtooth signal (ramp), the compensation signal (comp), and the sum signal ( sum), the reset terminal (R) and the set terminal (S) signal of the SR latch, and the schematic diagram of the PWM signal. the

Wherein, the area where the output current (Iout) rises is the first current (I1) of the upper power transistor, and the area where the output current (Iout) drops is the second current (I2) of the lower power transistor. Therefore, the current sense amplifier 315 can sense the first current (I1) to generate a sense signal (Vsense). It can be seen from the figure that when the setting terminal (S) of the SR latch receives a pulse wave, the PWM signal is at a high level, and when the reset terminal (R) of the SR latch receives a pulse wave, The PWM signal is low. Therefore, the pulse width of the PWM signal changes with the magnitude of the first current ( I1 ). the

Please refer to FIG. 4A , which shows a DC-to-DC converter with a known fixed on-time control mode. The DC-to-DC converter in the fixed turn-on time control mode includes: a control circuit 410 , a gate drive circuit 420 , and a power stage circuit 430 . Wherein, the control circuit 410 includes: a loop comparator (loop comparator) 412 , an SR latch (SR latch) 414 , and an on-time timer (on-time timer) 416 . Wherein, the on-time timer 416 uses a constant current source (Ion) to charge a capacitor (Con), and the relationship between the charging voltage (Vcharge) and the constant current source (Ion) is: $V_{\mathrm{ch}\arg e}=\frac{1}{C}\∫I_{\mathrm{on}}\mathrm{dt}.$ That is to say, each time the on-time timer 416 is activated, the charging operation starts, and when the charging voltage reaches a predetermined voltage, the on-time timer 416 will output a pulse to the SR latch 414 Reset terminal (R). Since both the constant current source (Ion) and the capacitor (Con) have fixed values, the time for each charging voltage (Vcharge) to reach a predetermined voltage value is the fixed turn-on time of Ton.

Furthermore, the loop comparator 412 receives the DC output voltage (Vout) and a reference voltage (Vref), and when the DC output voltage (Vout) is lower than the reference voltage (Vref), the loop comparator 412 will output a pulse to the SR lock The setting terminal (S) of the register 414. When the loop comparator 412 outputs a pulse wave to the setting terminal (S) of the SR latch 414, it will also control the on-time timer 416 to start counting, and output a pulse wave to the SR latch 414 after the Ton time. Reset terminal (R). The PWM signal can be generated according to the signal changes of the reset terminal (R) and the set terminal (S) of the SR latch 414 . the

Please refer to Figure 4B, which shows the output voltage (Vout), the reset terminal (R) and the set terminal (S) signal of the SR latch and the PWM Signal schematic. the

Wherein, when the output voltage (Vout) is lower than the reference voltage, the setting terminal (S) of the SR latch receives a pulse wave. After the time Ton elapses, the on-time timer 416 generates a pulse to the reset terminal (R) of the SR latch. It can be seen from the figure that when the setting terminal (S) of the SR latch receives a pulse, the PM signal is at a high level, and when the reset terminal (R) of the SR latch receives a pulse, PM signal is low level. the

As we all know, the operating voltages used by the central processing unit (CPU), dynamic random access memory (DRAM), graphics chip (graphic chip), and chipset (chip set) in a computer system are all different. Therefore, many DC-to-DC converters are needed in the computer system to convert the DC input voltage (for example, 19V) provided by the power supply into the operating voltage required by each component. However, the transient of the DC-to-DC converter will have a great impact on the performance of the above components. the

When the load (load) of the DC-to-DC converter changes drastically, the output current (Iout) will change rapidly. For example, when the output current (Iout) of the DC-to-DC converter suddenly decreases, the DC output voltage (Vout) will correspondingly increase rapidly, and this phenomenon is called overshoot. Conversely, when the output current (Iout) of the DC-to-DC converter suddenly increases, the DC output voltage (Vout) will decrease correspondingly and rapidly. This phenomenon is called undershoot. the

When the overshoot or undershoot occurs, the control circuit in the DC-to-DC converter must restore the overhigh or underlow DC output voltage to a steady state voltage. Taking the overshoot phenomenon as an example, when the overshoot phenomenon occurs transiently, the DC output voltage will be higher than the steady-state DC output voltage, and the overshoot voltage is the overshoot voltage. the

As shown in Figure 5, taking the operating frequency of the PWM signal of the DC-to-DC converter in the voltage control mode as 200KHz and the steady-state DC output voltage as 1.26V as an example, when the output current drops sharply from 90A to 5A, the transient The DC output voltage will increase to 1.36V, that is, the overshoot voltage is 100mV. As shown in Figure 6, taking the PWM signal operating frequency of the DC-DC converter in the fixed on-time control mode as 276KHz and the steady-state DC output voltage as 1.96V as an example, when the output current drops sharply from 25A to 1.5A , the transient DC output voltage will increase to 2.04V, that is, the overshoot voltage is 80mV. the

Therefore, the designer of the DC-to-DC converter will propose ways to improve the overshoot and undershoot phenomena. However, most designers of DC-to-DC converters focus on improving the undershoot phenomenon, but rarely propose to improve the overshoot phenomenon. the

For example, U.S. Patent No. 7,157,943 proposes a switching mode power converter (Frequency selection of switch mode power converters via softstart voltage level) with soft start voltage level for frequency selection. The switch-mode power converter proposed in this patent claims to reduce overshoot. However, this patent does not mention how to practice and reduce the overshoot phenomenon. the

Furthermore, Chinese Taiwan patent I251395 proposes a pulse width modulation device that uses an output voltage feedback hysteresis circuit to automatically change the output frequency. Obviously, this patent is to solve the influence caused by the loss of the upper power transistor or the lower power transistor. Furthermore, the PWM signal of this patent will constantly change, so the stability of the entire DC-to-DC converter will deteriorate. the

Contents of the invention

The present invention proposes a DC-to-DC converter, including: a control circuit that receives and compares a DC output voltage, and outputs a pulse width modulation of a first frequency when the DC output voltage does not exceed a first threshold voltage. The signal is changed, and when the DC output voltage exceeds the first threshold voltage, a pulse width modulation signal of a second frequency is output, and the second frequency is greater than the first frequency; a grid driving circuit receives the pulse width modulation signal and converted into a first driving signal and a second driving signal; a power stage circuit converts a DC input voltage into a DC output voltage according to the first driving signal and the second driving signal. the

The present invention further proposes a control method for a DC-to-DC converter. The DC-to-DC converter includes a control circuit, a gate drive circuit, and a power stage circuit, and the control circuit can receive the power generated by the power stage circuit. A DC output voltage, and a corresponding pulse width modulation signal is generated according to the change of the DC output voltage, and the gate drive circuit receives the pulse width modulation signal and converts it into a first driving signal and a second driving signal To the power stage circuit, so that the power stage circuit can convert a DC input voltage into a DC output voltage according to the change of the first driving signal and the second driving signal. The control method of the DC-to-DC converter includes the following steps: continuously monitor the output DC voltage; when the DC output voltage does not exceed a first threshold voltage, switch the operating frequency of the PWM signal to a first frequency; and, when the DC output voltage exceeds the first threshold voltage, switch The operating frequency of the PWM signal is adjusted to a second frequency, and the second frequency is greater than the first frequency. the

The present invention also proposes a control method for a DC-to-DC converter. The DC-to-DC converter includes a control circuit, a gate drive circuit, and a power stage circuit, and the control circuit can receive the constant voltage generated by the power stage circuit. DC output voltage, and generates a corresponding pulse width modulation signal according to the change of the DC output voltage, and the gate drive circuit receives the pulse width modulation signal and converts it into a first driving signal and a second driving signal to The power stage circuit, so that the power stage circuit can convert a DC input voltage into a DC output voltage and an output current through a sensing impedance and a load according to the change of the first driving signal and the second driving signal, and the DC to DC converter The control method includes the following steps: continuously monitoring a sensing voltage generated by the output current flowing through the copper foil measuring impedance; when the sensing voltage is less than a bias compensation voltage, switching the operating frequency of the pulse width modulation signal to a first frequency; and, when the sharp drop of the output current causes the sensing voltage to increase, switch the operating frequency of the PWM signal to a second frequency, and the second frequency is greater than the first frequency. the

Therefore, the advantage of the present invention is to continuously monitor the DC output voltage (Vout). When the DC output voltage exceeds the first threshold voltage (for example, 1.03 times the steady-state DC output voltage), it means that the DC-to-DC converter overshoots Phenomenon. At this time, the control circuit increases the operating frequency of the PWM signal. The switching speed of the upper power transistor and the lower power transistor is increased to suppress the overshoot voltage. When the DC output voltage is lower than the first threshold voltage (for example, 1.03 times of the steady-state DC output voltage), it means that the DC-to-DC converter is about to return to a steady state. At this time, the control circuit returns to the normal operating frequency of the PWM signal. the

Description of drawings

In order for the examiner to further understand the characteristics and technical content of the present invention, please refer to the following detailed description and drawings of the present invention, but the attached drawings are only for reference and description, and are not used to limit the present invention, among which:

Figure 1 shows a schematic diagram of a known DC-to-DC converter;

Figure 2A shows a DC-to-DC converter with a known voltage control mode;

FIG. 2B is a schematic diagram of a compensation signal (comp), a sawtooth signal (ramp), a PWM signal, a first signal, and a second signal in a DC-to-DC converter in a voltage control mode;

Figure 3A shows a DC-to-DC converter with a known current control mode;

Figure 3B shows the output current (Iout), the sense signal (Vsense), the sawtooth signal (ramp), the compensation signal (comp), the sum signal (sum), and SR in the DC-DC converter in the current control mode Schematic diagram of the signals of the reset terminal (R) and the set terminal (S) of the latch, and the PWM signal;

Figure 4A shows a DC-to-DC converter with a known fixed on-time control mode;

4B is a schematic diagram of the output voltage (Vout), the signals of the reset terminal (R) and the set terminal (S) of the SR latch, and the PWM signal in the DC-to-DC converter in the fixed on-time control mode;

Figure 5 is a schematic diagram of the overcharge voltage of the DC-to-DC converter with a known voltage control mode;

Fig. 6 is a schematic diagram of the overcharge voltage of the DC-DC converter with a known fixed on-time control mode. the

Fig. 7 shows the flow chart of the control method of the DC-to-DC converter of the present invention;

Figure 8A shows the DC-to-DC converter in the voltage control mode of the first embodiment of the present invention;

FIG. 8B is a schematic diagram of the compensation signal (comp), the sawtooth signal (ramp), and the PWM signal in the DC-to-DC converter in the voltage control mode;

Figure 9 is a schematic diagram of the overcharge voltage of the DC-to-DC converter in the voltage control mode of the present invention;

FIG. 10A shows a DC-to-DC converter in current control mode according to the second embodiment of the present invention. the

Figure 10B shows the output current (Iout), sense signal (Vsense), sawtooth signal (ramp), compensation signal (comp), summation signal (sum), SR Schematic diagram of the signals of the reset terminal (R) and the set terminal (S) of the latch, and the PWM signal;

FIG. 11A shows a DC-to-DC converter in a fixed on-time control mode according to the third embodiment of the present invention;

Figure 11B, which shows the output voltage (Vout), the reset terminal (R) and set terminal (S) signals of the SR latch, and the PWM signal in the DC-to-DC converter in the fixed on-time control mode schematic diagram;

Figure 12 is a schematic diagram of the overcharge voltage of the DC-to-DC converter in the fixed on-time control mode of the present invention;

Figure 13 shows the DC-to-DC converter in voltage control mode. the

Detailed ways

Please refer to FIG. 7 , which is a flow chart of the control method of the DC-to-DC converter of the present invention. First, continuously monitor the DC output voltage (step S10). When the DC output voltage is less than the first threshold voltage (step S12), then jump to step S10; otherwise, when the DC output voltage is greater than the first threshold voltage (step S12), then increase the frequency of the PWM signal, that is, Increase from a first frequency to a second frequency (step S14). Next, continuously monitor the DC output voltage (step S16). When the DC output voltage is greater than the first threshold voltage (step S18), then jump to step S16; otherwise, when the DC output voltage is less than the first threshold voltage (step S18), then restore the frequency of the original PWM signal, that is , decrease from the second frequency to the first frequency (step S20), and skip to (step S10). the

According to an embodiment of the present invention, the DC output voltage will be continuously monitored, and when the DC output voltage exceeds the first threshold voltage (Vth1) (for example, Vth1=Vout+Delta, and Vout is the steady-state DC output voltage, and Delta can be set to 0.03Vout), which means that the DC-to-DC converter overshoots. At this time, the control circuit increases the operating frequency of the PWM signal to the second frequency. The switching speed of the upper power transistor and the lower power transistor is increased, therefore, the overshoot voltage can be effectively suppressed. the

Furthermore, when the DC output voltage is lower than the first threshold voltage (for example, 1.03 times of the steady-state DC output voltage), it means that the DC-to-DC converter is about to return to a steady state. At this time, the control circuit restores the operating frequency of the PWM signal to the first frequency. the

The DC-to-DC converter in the voltage control mode, the DC-to-DC converter in the current control mode, and the DC-to-DC converter in the fixed turn-on time control mode of the present invention will be introduced in detail below. the

Please refer to FIG. 8A , which shows the DC-to-DC converter in voltage control mode according to the first embodiment of the present invention. The DC-to-DC converter in the voltage control mode includes: a control circuit 610, a gate drive circuit 620, and a power stage circuit 630. Wherein, the control circuit 610 includes: an error amplifier 612 , a modulation unit 614 , a signal generator 616 , and a comparator 618 . the

The error amplifier 612 receives the DC output voltage (Vout) and a reference voltage (Vref), and the error amplifier 612 can compare the DC output voltage (Vout) with the reference voltage (Vref) to generate a compensation signal (comp) to the modulation unit 6 14. the

Furthermore, the signal generator 616 can selectively output the sawtooth wave signal (ramp) of the first frequency (F1) or the second frequency (F2) to the modulation unit 614, so that the modulation unit 614 can And a sawtooth signal (ramp) to generate a PWM signal. Of course, the signal generator 616 can output the sawtooth wave signal (ramp) of the first frequency (F1) or the second frequency (F2), and other signals of the first frequency (F1) or the second frequency (F2). A shape signal, such as a triangle signal. Wherein, the first frequency (F1) is smaller than the second frequency (F2). the

Furthermore, the comparator 618 can receive the first threshold voltage ( Vth1 ) and the DC output voltage ( Vout ). When the DC output voltage (Vout) is less than the first threshold voltage (Vth1), the comparator 618 can output the first level to the signal generator 616, so that the signal generator 616 outputs a sawtooth signal of the first frequency (F1) ( ramp) to the modulation unit 614. Conversely, when the DC output voltage (Vout) is greater than the first threshold voltage (Vth1), the comparator 618 can output a second level to the signal generator 616, so that the signal generator 616 outputs a sawtooth wave with a second frequency (F2) The signal (ramp) is sent to the modulation unit 614 . the

Please refer to FIG. 8B , which is a schematic diagram of the compensation signal (comp), the sawtooth signal (ramp), and the PWM signal in the DC-DC converter in the voltage control mode. When the compensation signal (comp) is greater than the sawtooth signal (ramp), the PWM signal is at a high level; otherwise, when the compensation signal (comp) is smaller than the ramp signal, the PWM signal is at a low level. Obviously, when the sawtooth signal (ramp) is changing, the pulse width of the PWM signal will also change accordingly; moreover, when the sawtooth signal (ramp) is at the first frequency (F1), the PWM signal operates at The first frequency (F1); when the sawtooth signal (ramp) is at the second frequency (F2), the PWM signal operates at the second frequency (F2). Therefore, the DC-DC converter in the voltage control mode of the present invention can control the operating frequency of the PWM signal according to the magnitude of the DC output voltage (Vout). the

As shown in Figure 9, according to the first embodiment of the present invention, when the first frequency of the PWM signal of the DC-to-DC converter in the voltage control mode is 200KHz and the steady-state DC output voltage is 1.26V as an example, when the output current When sharply reducing from 90A to 5A, adjusting the PWM signal to the second frequency (342KHz) will increase the transient DC output voltage to 1.33V, that is, the overshoot voltage is 70mV. Therefore, the overshoot voltage can be effectively suppressed. the

Please refer to FIG. 10A , which shows a DC-to-DC converter in a current control mode according to a second embodiment of the present invention. The DC-to-DC converter in the current control mode includes: a control circuit 710 , a gate drive circuit 720 , and a power stage circuit 730 . Wherein, the control circuit 710 includes: an error amplifier 712, a PWM comparator 713, a signal generator 714, a current sense amplifier 715, an adder 716, an SR latch 717, and a comparator 718. The error amplifier 712 receives the DC output voltage (Vout) and a reference voltage (Vref), and the error amplifier 712 can compare the DC output voltage (Vout) with the reference voltage (Vref) to generate a compensation signal (comp) to the PWM comparator 713 . the

Furthermore, the current sense amplifier 715 can detect the first current ( I1 ) flowing through the upper power transistor or the second current ( I2 ) flowing through the lower power transistor in the power stage circuit 730 . For example, the current sense amplifier 715 can convert the current (I1) of the upper power transistor into a sense signal (Vsense). the

Moreover, the signal generator 314 can simultaneously output a ramp signal (ramp) and a clock signal (CLK), and the ramp signal (ramp) and the clock signal (CLK) can selectively have the same first frequency ( F1) or the second frequency (F2). The sawtooth signal (ramp) and the sensing signal (Vsense) are superposed by the adder 716 to become a sum signal (sum). Wherein, the first frequency (F1) is smaller than the second frequency (F2). the

The sum signal (sum) and the compensation signal (comp) are input to the PWM comparator 313. When the sum signal (sum) is greater than the compensation signal (comp), the PWM comparator 313 will output a pulse to the SR latch 317. Reset terminal (reset terminal, R). Furthermore, the clock signal (CLK) is input to the set terminal (S) of the SR latch 317 . The PWM signal can be generated according to the signal changes of the reset terminal (R) and the set terminal (S) of the SR latch 317 . Of course, the signal generator 216 can also output a triangle signal (triangle signal) in addition to the ramp signal. the

Furthermore, the comparator 718 can receive the first threshold voltage ( Vth1 ) and the DC output voltage ( Vout ). When the DC output voltage (Vout) is less than the first threshold voltage (Vth1), the comparator 718 can output the first level to the signal generator 716, so that the signal generator 714 outputs a sawtooth signal of the first frequency (F1) ( ramp) and clock signal (CLK). Conversely, when the DC output voltage (Vout) is greater than the first threshold voltage (Vth1), the comparator 718 can output a second level to the signal generator 714, so that the signal generator 714 outputs a sawtooth signal with a second frequency (F2). Wave signal (ramp) and clock signal (CLK). the

Please refer to FIG. 10B, which shows the output current (Iout), the sense signal (Vsense), the sawtooth signal (ramp), the compensation signal (comp), and the sum signal ( sum), the reset terminal (R) and set terminal (S) signals of the SR latch, and the schematic diagram of the PM signal. the

Wherein, the area where the output current (Iout) rises is the first current (I1) of the upper power transistor, and the area where the output current (Iout) drops is the second current (I2) of the lower power transistor. Therefore, the current sense amplifier 315 can sense the first current (I1) to generate a sense signal (Vsense). It can be seen from the figure that when the setting terminal (S) of the SR latch receives a pulse wave, the PWM signal is at a high level, and when the reset terminal (R) of the SR latch receives a pulse wave, The PWM signal is low. Therefore, the pulse width of the PWM signal changes with the magnitude of the first current ( I1 ). Furthermore, when the ramp signal (ramp) and the clock signal (CLK) are at the first frequency (F1), the PWM signal operates at the first frequency (F1); when the ramp signal (ramp) and the clock signal (CLK ) is the second frequency (F1), the PWM signal operates at the second frequency (F2). Therefore, the current control mode DC-DC converter of the present invention can control the operating frequency of the PWM signal according to the magnitude of the DC output voltage (Vout). the

Please refer to FIG. 11A , which shows a DC-to-DC converter in a fixed on-time control mode according to a third embodiment of the present invention. The DC-to-DC converter in the fixed on-time control mode includes: a control circuit 810 , a gate drive circuit 820 , and a power stage circuit 830 . Wherein, the control circuit 810 includes: a loop comparator 812 , an SR latch 814 , an on-time timer 816 , and a comparator 818 . Wherein, the on-time timer 816 can use a first constant current source (Ion1) or a second constant current source (Ion2) to charge a capacitor (Con), wherein the first constant current source (Ion1) is smaller than the first constant current source (Ion1) Two constant current sources (Ion2). The relationship between the charging voltage (Vcharge) and the first constant current source (Ion1) is: $V_{\mathrm{ch}\arg e}=\frac{1}{C}\∫I_{\mathrm{on}1}\mathrm{dt};$ The relationship between the charging voltage (Vcharge) and the second constant current source (Ion2) is: $V_{\mathrm{ch}\arg e}=\frac{1}{C}\∫I_{\mathrm{on}2}\mathrm{dt}.$ That is to say, each time the on-time timer 816 starts, the first constant current source (Ion1) or the second constant current source (Ion2) can be used to start charging a capacitor (Con). When the charging voltage reaches a certain When the predetermined voltage is reached, the on-time timer 816 outputs a pulse to the reset terminal (R) of the SR latch 814 . Obviously, when charging by the first constant current source (Ion1), the time for the charging voltage (Vcharge) to reach the predetermined voltage value is the fixed turn-on time of Ton1; similarly, charging by the second constant current source (Ion2) , the time for the charging voltage (Vcharge) to reach the predetermined voltage value is the fixed turn-on time of Ton2.

Moreover, the loop comparator 812 receives the DC output voltage (Vout) and a reference voltage (Vref), and when the DC output voltage (Vout) is lower than the reference voltage (Vref), the loop comparator 812 will output a pulse to the SR lock The setting terminal (S) of the register 814. And when the loop comparator 812 outputs the pulse wave to the setting terminal (S) of the SR latch 814, it will also control the on-time timer 816 to start counting, and output a pulse wave to the SR latch after Ton1 or Ton2 time 814 reset terminal (R). The PWM signal can be generated according to the signal changes of the reset terminal (R) and the set terminal (S) of the SR latch 814 . the

Furthermore, the comparator 818 can receive the first threshold voltage ( Vth1 ) and the DC output voltage ( Vout ). When the DC output voltage (Vout) is less than the first threshold voltage (Vth1), the comparator 818 can output the first level to control the switch (SW), so that the first current source (Ion1) can conduct the capacitor (Con) Conversely, when the DC output voltage (Vout) is greater than the first threshold voltage (Vth1), the comparator 818 can output a second level to control the switch (SW), so that the second current source (Ion2) can charge the capacitor (Con) to charge. the

Please refer to FIG. 11B, which shows the output voltage (Vout), the signals of the reset terminal (R) and the set terminal (S) of the SR latch, and Schematic diagram of the PWM signal. the

Wherein, when the output voltage (Vout) is lower than the reference voltage, the setting terminal (S) of the SR latch receives a pulse wave. When the switch (SW) is switched to the first constant current source (Ion1), after the time of Ton1, the on-time timer 816 generates a pulse wave to the reset terminal (R) of the SR latch; otherwise, when the switch ( When SW) is switched to the second constant current source (Ion2), after the time Ton2 elapses, the on-time timer 816 generates a pulse to the reset terminal (R) of the SR latch. It can be seen from the figure that when the setting terminal (S) of the SR latch receives a pulse wave, the PWM signal is at a high level, and when the reset terminal (R) of the SR latch receives a pulse wave, The PWM signal is low. Obviously, controlling the first current source ( Ion1 ) or the second current source ( Ion2 ) to charge the capacitor ( Con ) can select a fixed turn-on time of Ton1 or a fixed turn-on time of Ton2 . The frequency of the PWM signal is lower when the fixed turn-on time of Ton1 is selected; the frequency of the PWM signal is higher when the fixed turn-on time of Ton2 is selected. Therefore, the DC-DC converter in the fixed on-time control mode of the present invention can control the operating frequency of the PWM signal according to the magnitude of the DC output voltage (Vout). the

As shown in Figure 12, according to the third embodiment of the present invention, when the operating frequency of the PWM signal of the DC-DC converter in the fixed on-time control mode is 276KHz and the steady-state DC output voltage is 1.96V as an example, when the output When the current drops sharply from 25A to 1.5A, adjusting the PWM signal to the second frequency (342KHz) will increase the transient DC output voltage to 2.01V, that is, the overshoot voltage is 50mV. Therefore, the overshoot voltage can be effectively suppressed. the

Moreover, in addition to using the DC output voltage (Vout) to adjust the frequency of the PWM signal, designers who are familiar with this memory can also judge the overcharge phenomenon according to the change of the output current (Iout), and reduce the overcharge voltage. . Please refer to FIG. 13 , which shows a DC-to-DC converter in voltage control mode. The DC-DC converter in this voltage control mode includes: a control circuit 610 , a gate driving circuit 620 , a power stage circuit 630 , offset voltage (Voffset), a sensing impedance 642 and a load 640 . As shown in the figure, the control circuit 610 includes: an error amplifier 612 , a modulation unit 614 , a signal generator 616 and a hysteresis comparator (hysteresis comparator) 619 . the

The error amplifier 612 receives the DC output voltage (Vout) and a reference voltage (Vref), and the error amplifier 612 can compare the DC output voltage (Vout) with the reference voltage (Vref) to generate a compensation signal (comp) to the modulation unit 614 . the

Furthermore, the signal generator 616 can selectively output the sawtooth wave signal (ramp) of the first frequency (F1) or the second frequency (F2) to the modulation unit 614, so that the modulation unit 614 can And a sawtooth signal (ramp) to generate a PWM signal. the

According to this embodiment, the sensing impedance 642 can be an inductive impedance. When the output current (Iout) decreases sharply, the load voltage (Vload) at the end of the load 640 drops sharply. At this time, due to the impedance effect of the sensing impedance 642 itself, the direct current output voltage (Vout) will not change immediately, therefore, a sensing voltage (ΔV, sense voltage) will be generated on the sensing impedance 642 . the

When the sensing voltage (ΔV) is greater than the offset voltage (Voffset), it means that overcharging will occur at this time, and the hysteresis comparator 619 can control the signal generator 616 to increase from the first frequency (F1) to the second frequency ( F2). That is to say, when the sensing voltage (ΔV) is very small, the hysteresis comparator 619 can output the first level to the signal generator 616, so that the signal generator 616 outputs a sawtooth wave signal ( ramp) to the modulation unit 614. Conversely, when the output current (Iout) drops sharply so that the result of subtracting the offset voltage (Voffset) from the sensing voltage (ΔV) reaches the level change point of the hysteresis comparator 619, the hysteresis comparator 619 can output a second voltage. level to the signal generator 616 , so that the signal generator 616 outputs a sawtooth signal (ramp) of the second frequency ( F2 ) to the modulation unit 614 . the

Furthermore, the comparators 618 , 718 , and 818 in the above three embodiments can also use hysteresis comparators to prevent the disturbance of the DC output voltage, so that the DC-to-DC converter can operate more stably. the

In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. and retouching, so the protection scope of the present invention should be defined by the claims. the

Claims (3)

1. A DC-to-DC converter, characterized in that, comprising: The control circuit receives and compares the DC output voltage, and outputs a pulse width modulation signal with a first frequency when the DC output voltage does not exceed the first threshold voltage, and when the DC output voltage exceeds the first threshold voltage , outputting the above-mentioned pulse width modulation signal of a second frequency, and the above-mentioned second frequency is greater than the above-mentioned first frequency; a gate drive circuit, receiving the pulse width modulation signal and converting it into a first drive signal and a second drive signal; and the power stage circuit converts the DC input voltage into the DC output voltage according to the first driving signal and the second driving signal, Wherein the above-mentioned control circuit includes: a loop comparator, receiving the above-mentioned DC output voltage and the reference voltage, and generating the first pulse wave; a comparator, receiving the first threshold voltage and the DC output voltage; when the DC output voltage is less than the first threshold voltage, the comparator outputs a first level; when the DC output voltage is greater than the first threshold voltage, the comparator outputs the second level; Turn on the time timer to generate a second pulse wave when the comparator outputs the first level, and the difference between the first pulse wave and the second pulse wave is the first turn-on time, and when the comparator outputs the second level , generating a third pulse wave, and the difference between the first pulse wave and the third pulse wave is a second turn-on time, and the first turn-on time is greater than the second turn-on time; and The SR latch generates the pulse width modulation signal according to the first pulse wave and the second pulse wave, or generates the pulse width modulation signal according to the first pulse wave and the third pulse wave. 2. The DC-to-DC converter according to claim 1, wherein the on-time timer uses the first constant current source and the second constant current source to charge the capacitor to obtain the first on-time and the second 2. Turn on time, and the above-mentioned first constant current source is smaller than the above-mentioned second constant current source. 3. The DC-to-DC converter according to claim 1, wherein the comparator is a hysteresis comparator.

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