CN101506956A - Manufacturing method of semiconductor device - Google Patents

Abstract

A method of fabricating a power semiconductor device is disclosed.

Description

Manufacturing method of semiconductor device

related application

This application is based upon and claims the benefit of U.S. Provisional Application No. 60/709,020, filed August 17, 2005, entitled TrenchMOSFET Process Using Four Masks, from which priority is hereby claimed and that The disclosure of the provisional application is hereby incorporated by reference.

technical field

The present invention relates to semiconductor fabrication, and more particularly to methods of fabricating power semiconductor devices such as power metal oxide semiconductor field effect transistors (MOSFETs).

Background technique

Photolithography is well known and is a commonly used technique in the fabrication of semiconductor devices such as power MOSFETs. In general, photolithography involves depositing a masking material on a surface of a semiconductor body and selectively removing the masking material to form a mask having openings in the mask. This mask is then used to define the properties of the semiconductor body. For example, dopants may be implanted into the semiconductor body through the mask opening, or a portion of the semiconductor body may be removed through the opening to recess or "groove" the semiconductor body as desired.

A typical fabrication process may require some masks. For example, a mask may be required to define gate trenches, or a mask may be required to define source regions.

It is desirable to reduce the number of masks, as an increase in the number of masks generally increases the cost by making the fabrication process more complex, and more masks increases the chance of obtaining a higher percentage of defective parts, thereby Reduced output and increased overall costs.

Contents of the invention

An object of the present invention is to provide a process for fabricating a power semiconductor device such as a power MOSFET.

A process according to the invention includes covering a mask body on the surface of a semiconductor body; removing a portion of the mask body to define an opening extending to the semiconductor body; removing semiconductor from the bottom of the opening to define a plurality of gate trenches and disposed in Termination trenches around the gate trenches, said gate trenches being separated from each other by mesas; removing the mask body; oxidizing the sidewalls of the gate trenches; depositing gate electrode material; an electrode is left in the trench; a channel dopant is implanted to define a body region adjacent to said gate trench; a source mask is formed on the body region; a source dopant is implanted through the source mask to form source implant region; deposit low density oxide on semiconductor body; deposit contact mask; etch low density oxide through the contact mask; deposit metal layer on top of semiconductor body; form front metal mask on top of the metal layer film; and etching the metal layer to form at least one source contact and gate runner.

Thus, in the process according to the invention, a power semiconductor device can be obtained using four masks, namely, a trench mask for defining gate trenches and termination trenches; a source mask; a contact mask and Mask used to define source and gate electrodes.

The process according to the invention also includes forming an oxidation inhibitor on at least sidewalls of the gate trench and the termination trench, and growing a thick oxide on the bottom of the gate trench and the bottom of the termination trench. Then, the oxidation inhibitor can be removed before oxidizing the sidewall of the gate trench, and then the process can also include oxidizing the mesa structure; depositing the gate electrode material on the mesa structure; etching away the gate electrode material from the mesa structure; and The oxide is etched away from the mesas prior to source implantation.

In another variation, an opening may be defined in the mask body and a portion of the semiconductor body may be removed to define an equipotential ring (EQR) trench around the termination trench.

Other characteristics and advantages of the invention will become apparent from the following description of the invention with reference to the accompanying drawings.

Description of drawings

Figure 1 schematically shows a cross-sectional view of a part of a device made according to a preferred embodiment of the invention;

2A-2H show the fabrication process of a power semiconductor device according to a preferred embodiment of the present invention.

Detailed ways

)形成在栅极沟槽14的侧壁上，厚氧化体(例如，SiO₂)22(比栅极氧化物20厚)形成在栅极沟槽14的底部，以及栅电极24(优选为由导电多晶硅构成)形成在栅极沟槽14里面。Referring to FIG. 1 , the device according to the invention is preferably a power MOSFET comprising an active region 10 and a termination region 12 . Active region 10 includes at least one gate trench 14 extending through base region 16 to drift region 18 . Gate oxide (eg, SiO ₂ ) 20 with a suitable thickness (eg, 1000

) is formed on the sidewalls of the gate trench 14, a thick oxide (eg, SiO ₂ ) 22 (thicker than the gate oxide 20) is formed at the bottom of the gate trench 14, and a gate electrode 24 (preferably made of Conductive polysilicon) is formed inside the gate trench 14 .

The active region also includes a source region 26 adjacent to the gate trench 14 and formed in the base region 16 , and a highly conductive contact region 28 formed in the base region 16 . A source contact 30 ohmically connects to the source region 26 and the highly conductive contact region 28 . Note that the base region 16 and the highly conductive contact region 28 have an opposite polarity to the source region 26 and the drift region 18 as is well known. Thus, in an N-channel device, the base region 16 and the highly conductive contact region 28 are P-type, while the drift region 18 and source region 26 are N-type. The device according to the invention also comprises a silicon substrate 32 having the same polarity as the drift region 18 , and a drain contact 34 which is ohmically connected to the substrate 32 . Note that the drift region 18 as well as the base region 16 are part of an epitaxially grown silicon body 31 grown on a substrate 32 as is generally known.

The termination region 12 includes a termination trench 36 disposed around the active region 10 and extending to a depth below the base region 16, a first silicon dioxide body 38, the first silicon dioxide body 38 A second silicon dioxide body 40 is located on the bottom surface and sidewalls of the termination trench 38 and on the first silicon dioxide body 38 . The first silicon dioxide body 38 is a grown oxide formed by growing silicon dioxide by oxidation of the epitaxially grown silicon body 31 and by depositing a low density silicon dioxide such as tetraethyl silicate (TEOS). body 40 to form the second silicon dioxide body 40 . The first silicon dioxide body 38 and the second silicon dioxide body 40 together form a field insulator. An extension of the source contact 30 lies on the second silicon dioxide body 40 , thereby forming a field plate 42 . Preferably, the termination region 12 further includes an equipotential ring (EQR) structure 44 disposed around the termination trench 36 . The EQR 44 includes an EQR trench 46 having silicon dioxide on its sidewalls and bottom, and polysilicon disposed in the EQR trench 46 .

2A-2H schematically illustrate the method according to the invention.

Referring to FIG. 2A , starting from a silicon substrate 32 having an epitaxial silicon body 31 formed on the silicon substrate 32 , first a hard mask 50 is formed on the surface of, for example, N-type epitaxially grown silicon 31 . The hard mask 50 is formed by depositing _a hard mask body composed of, for example, silicon nitride ( _Si3N4 ), in which the opening 52 is defined, and silicon is removed from the bottom of the opening 52 to define the gate trench. trench 14 , termination trench 36 and EQR trench 44 .

Next, an oxidation inhibitor 54 such as Si ₃ N ₄ is formed on the sidewalls of the gate trench 14 , the sidewall of the termination trench 36 and the sidewall of the EQR trench 44 . Thereafter, the bottoms of gate trenches 14 , termination trenches 36 , and EQR trenches 44 are oxidized to form thick oxide 22 as shown in FIG. 2B .

Referring next to FIG. 2C, the mask 50 and the oxidation inhibitor 54 are removed and the exposed silicon is oxidized, thereby forming a gate oxide 20 on the sidewalls of the gate trench 14 and forming a gate oxide 20 on the remaining exposed silicon. Oxide liner 56 is formed on the remaining exposed silicon including the sidewalls of termination trench 36 , the sidewalls of EQR trench 44 and the mesa structures between trenches 14 , 36 and 44 . Note that oxide liner 56 on the sidewalls of termination trench 36 and thick oxide 22 at the bottom of termination trench 36 form first oxide 38 . Thereafter, as shown in FIG. 2D, polysilicon 58 is deposited. Polysilicon 58 may be rendered conductive by implanting dopants after polysilicon 58 is deposited or by in-situ doping. Then, as shown in FIG. 2E , polysilicon 58 is removed leaving gate electrode 24 in gate trench 14 and polysilicon body 48 in EQR trench 44 . Alternatively, an anisotropic etch may be used to leave polysilicon spacers 59 on the sidewalls of termination trenches 36, as shown in FIG. 2E'. Polysilicon spacers 59 may be electrically floating.

Referring now to FIG. 2F , oxide 58 is removed from the top of the mesas between trenches 14 , 36 and 44 , and dopants for forming base region 16 are implanted. Note that thick oxide 22 at the bottom of termination trench 34 prevents penetration of dopants into the silicon below the bottom of termination trench 36 . After the base implant, a source mask is provided and source dopants are implanted. The source and base implants are then activated to form base region 16 and source region 28 . Thereafter, as shown in FIG. 2G , a low density oxide layer 60 such as TEOS is deposited. Then, as shown in FIG. 2H , the low density oxide is patterned in a masking stage and a portion of the low density oxide is removed to form contact openings 62 in the low density oxide. Note that a second oxide body 40 and an oxide plug 25 are thus formed. Through each opening 62 , a portion of silicon is removed to form a recess, and dopants having the same conductivity as base region 16 (eg, P-type) are implanted and activated to form highly conductive contact region 28 .

Afterwards, a metal layer (eg aluminum) is deposited on the upper side of the silicon and in another masking stage, this metal layer is patterned to obtain the source contact 30 and the gate contact of the device. A drain contact 34 is then formed on the substrate 32 to obtain the device according to FIG. 1 .

While the invention has been described in terms of particular embodiments thereof, it is apparent that many other changes and modifications, as well as other applications, will be apparent to those skilled in the art. Preferably, therefore, the invention is not limited by the specific disclosure herein, but only by the appended claims.

Claims (11)

1. A method for manufacturing a power semiconductor device, the method comprising: covering the surface of the semiconductor body with a mask; removing a portion of the mask body to define an opening extending to the semiconductor body; removing semiconductor from the bottom of the openings to define a plurality of gate trenches and termination trenches disposed around the gate trenches, the gate trenches being separated from each other by mesas; removing the mask body; oxidizing sidewalls of the gate trench; depositing gate electrode material; etching the gate electrode material to leave a gate electrode in the gate trench; implanting channel dopants to define a body region adjacent to the gate trench; forming a source mask over the body region; implanting a source dopant through the source mask to form a source implantation region; depositing a low density oxide on the semiconductor body; depositing a contact mask; etching the low density oxide through the contact mask; depositing a metal layer on top of the semiconductor body; forming a front metal mask on top of the metal layer; and The metal layer is etched to form at least one source contact and a gate runner. 2. The method of claim 1, further comprising: forming an oxidation inhibitor on at least sidewalls of the gate trench and sidewalls of the termination trench; A thick oxide is grown on the bottom of the gate trench and the bottom of the termination trench. 3. The method of claim 1, further comprising: removing the oxidation inhibitor prior to oxidizing sidewalls of the gate trench; oxidizing the mesa structure; depositing a gate electrode material on the mesa structure; etching away gate electrode material from the mesa structure; and Oxide is etched away from the mesas prior to source implantation. 4. The method of claim 1, wherein the semiconductor body is epitaxially grown silicon. 5. The method of claim 1, wherein the mask body is a hard mask comprising silicon nitride. 6. The method of claim 1, wherein the oxidation inhibitor is comprised of silicon nitride. 7. The method of claim 1, wherein the low density oxide is composed of tetraethyl orthosilicate. 8. The method of claim 1, wherein the gate material is comprised of polysilicon. 9. The method of claim 1, further comprising defining an equipotential ring opening in the mask body; and removing a portion of the semiconductor body to define an equipotential ring around the termination trench. 10. The method of claim 1, wherein the power semiconductor device is a metal oxide semiconductor field effect transistor. 11. The method of claim 1, wherein the semiconductor body is disposed on a semiconductor substrate and the method further comprises forming a back metal layer on the substrate.

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