CN101515601B - Capacitor structure and method for forming the same for booster circuit - Google Patents

Abstract

The invention discloses a capacitor structure used in a booster circuit and a forming method thereof. The capacitor structure comprises a substrate, a U-shaped lower electrode positioned in the substrate, a T-shaped upper electrode embedded with the U-shaped lower electrode, and a dielectric layer between the U-shaped lower electrode and the T-shaped upper electrode. The invention uses a three-dimensional technical means to increase the contact area between the upper polar plate and the lower polar plate so as to greatly improve the capacitance value of the booster circuit.

Description

Capacitor structure and method for forming the same for booster circuit

technical field

The invention relates to a capacitor structure and a forming method thereof, in particular to a capacitor structure used in a boost circuit and a forming method thereof.

Background technique

In a conventional dynamic random access memory (DRAM), a boost circuit plays an important role in generating a high voltage for driving a cell to operate. Especially with the continuous evolution of dynamic random access memory (DRAM) technology, when the operating voltage of the driving unit is still relatively high, such as about 2.6V, the initial voltage (Vint) may drop to 1.0V-1.5V V around, which makes the work of the boost circuit more difficult.

The boost efficiency of the boost circuit mainly depends on the size of the capacitor in the boost circuit. The larger the capacitance, the greater the boost efficiency and the greater the output voltage can be provided. Since the capacitance usually depends on the contact area between the upper and lower plates, how to increase the contact area between the upper and lower plates becomes a key issue.

However, with the continuous evolution of dynamic random access memory (DRAM) technology, the allocation of limited space on the substrate has become more and more penny-pinching, because in traditional dynamic random access memory (DRAM), the boost circuit is used General planar capacitors greatly limit the possibility of increasing the contact area space between the upper and lower plates. In order to solve the problem of the drop between the operating voltage and the initial voltage of the driving unit once and for all, how to increase the capacitance of the boost circuit becomes an urgent problem to be solved.

Contents of the invention

The present invention therefore provides a novel capacitor structure, using three-dimensional technical means to increase the contact area between the upper and lower plates, so as to greatly increase the capacitance value of the boost circuit.

The capacitive structure used in the boost circuit of the present invention includes: a substrate, a U-shaped lower electrode located in the substrate, a T-shaped upper electrode embedded with the U-shaped lower electrode, and a U-shaped lower electrode and a T-shaped Dielectric layer between top electrodes. Since the upper and lower electrode plates fit each other in a three-dimensional shape, the largest contact area can be created in a limited space, thus greatly increasing the capacitance value of the booster circuit.

Description of drawings

Fig. 1 illustrates a preferred embodiment of the capacitor structure of the present invention.

2A and 2B illustrate possible arrangements of capacitor structures of the present invention.

3-4 illustrate a preferred embodiment of fabricating the capacitive structure of the present invention.

Explanation of reference signs

100 capacitor structure 110 base material

111 oxide layer 112 polysilicon layer

113 grooves 120U-shaped lower electrode

130T-shaped upper electrode 140 dielectric layer

141 Dielectric layer in horizontal direction 142 Dielectric layer in vertical direction

131/132 polysilicon layer 150 inner spacers

Detailed ways

The capacitance structure of the present invention can greatly increase the capacitance value of the boost circuit, thus creating the maximum boost performance in a limited space. Please refer to FIG. 1 , which shows a preferred embodiment of the capacitor structure of the present invention. The capacitor structure 100 of the present invention includes a substrate 110 , a U-shaped bottom electrode 120 , a T-shaped top electrode 130 and a dielectric layer 140 . Substrate 110 is typically a semiconductor material, such as silicon.

The U-shaped lower electrode 120 is located in the substrate 110 . The material of the U-shaped bottom electrode 120 is usually the same as that of the base material 110 , and a known method is used, such as adding ion dopants to make it conductive. The dielectric layer 140 is located on the U-shaped lower electrode 120 and is in direct contact with the U-shaped lower electrode. The dielectric layer 140 generally includes a material with a high dielectric constant, such as silicon oxide. Generally, the thickness of the dielectric layer 140 is preferably between 3 nm-10 nm. In addition, the thickness of the dielectric layer 140 in the horizontal direction and the vertical direction may also be different. For example, after implanting fluorine ions into the substrate, a thicker oxide layer can be produced through thermal oxidation treatment, and a thinner oxide layer can be produced if nitrogen ions are implanted. Therefore, the thickness of the dielectric layer 141 in the horizontal direction may be about 3.8 nm, and the thickness of the dielectric layer 142 in the vertical direction may be about 5 nm.

The T-shaped upper electrode 130 is located above the dielectric layer 140 . The T-shaped upper electrode 130 usually includes a conductive material, such as lightly doped polysilicon, and is embedded with the U-shaped lower electrode 120 . By fitting the T-shaped upper electrode 130 and the U-shaped lower electrode 120 , the contact area between the upper electrode and the lower electrode of the capacitive structure 100 can be increased.

If necessary, an inner spacer 150 may be further included between the dielectric layer 140 and the T-shaped upper electrode 130 .

Figures 2A and 2B illustrate various possibilities for the arrangement of the capacitive structures of the present invention. For example, it may be the staggered pattern shown in FIG. 2A or the checkerboard pattern shown in FIG. 2B. Different arrangements can be made as the case requires.

Please refer to FIGS. 3-4 , which illustrate a preferred embodiment of manufacturing the capacitor structure of the present invention. First, please refer to FIG. 3 , a substrate 110 is provided, on which an oxide layer 111 and a polysilicon layer 112 can be formed, and a trench 113 can be formed. The depth of the groove 113 depends on the situation.

Please continue to refer to FIG. 4 , through an oxidation process, such as a water vapor oxidation method, the horizontal direction dielectric layer 141 and the vertical direction dielectric layer 142 in the trench 113 are formed. A polysilicon layer 131/132 is then deposited. If necessary, an inner spacer 150 may be further formed in the groove 113 . The thickness of the dielectric layer in the horizontal direction 141 and the vertical direction 142 can also be different. For example, after implanting fluorine ions into the substrate, a thicker oxide layer can be produced through thermal oxidation treatment, and a thinner oxide layer can be produced if nitrogen ions are implanted.

Please continue to refer to FIG. 1 , and continue to deposit a polysilicon layer to form the T-shaped upper electrode 130 , and then the capacitor structure 100 of the present invention is completed. The T-shaped upper electrode 130 is composed of the polysilicon layer 112 , the polysilicon layers 131 / 132 , and the finally deposited polysilicon layer. Since the above method is compatible with common dynamic random access memory (DRAM) technology, this is another feature of the capacitor structure of the present invention.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (8)

1. A capacitor structure used in a boost circuit, comprising: Substrate; The lower electrode is located in the substrate and has a recess; an upper electrode, located on the substrate, fits into the recess of the lower electrode; and a dielectric layer between the lower electrode and the upper electrode, wherein the dielectric layer on the sidewall of the recess extends upwards beyond the lower electrode, and the dielectric layer at the bottom of the recess has a A first uniform thickness, the dielectric layer on the sidewall of the recess has a second uniform thickness, wherein the first uniform thickness is different from the second uniform thickness. 2. The capacitor structure of claim 1, wherein the bottom electrode comprises ion-doped silicon. 3. The capacitor structure of claim 2, wherein the top electrode comprises doped polysilicon. 4. The capacitor structure as claimed in claim 1, wherein the thickness of the dielectric layer is between 3.8nm-5nm. 5. The capacitive structure as claimed in claim 3, wherein the capacitive structure further comprises an inner spacer, the inner spacer is located on a part of the surface of the sidewall of the dielectric layer of the recess, and is interposed between the dielectric layer and the between the upper electrodes. 6. A method for forming a capacitor structure, comprising: A substrate is provided, the substrate includes ion-doped silicon, and an oxide layer and a first conductor layer are sequentially formed on the substrate; forming a trench through the first conductor layer and the oxide layer and extending into the substrate; conformally forming a dielectric layer on the bottom and sidewalls of the trench; and A second conductor layer is formed on the surfaces of the first conductor layer and the dielectric layer, and fills the trench. 7. The method of claim 6, wherein forming the second conductor layer comprises forming a spacer layer on a part of the sidewall of the trench before forming the second conductor layer. 8. The method of claim 6, wherein the first conductor layer and the second conductor layer comprise ion-doped polysilicon.

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