CN101510538A - Device mounting board and manufacturing method, semiconductor module and portable apparatus therefor - Google Patents
Device mounting board and manufacturing method, semiconductor module and portable apparatus therefor Download PDFInfo
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- CN101510538A CN101510538A CN 200910130758 CN200910130758A CN101510538A CN 101510538 A CN101510538 A CN 101510538A CN 200910130758 CN200910130758 CN 200910130758 CN 200910130758 A CN200910130758 A CN 200910130758A CN 101510538 A CN101510538 A CN 101510538A
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- 239000004065 semiconductor Substances 0.000 title claims description 100
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000004020 conductor Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 19
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 186
- 229910000679 solder Inorganic materials 0.000 description 62
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000113 differential scanning calorimetry Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 150000007974 melamines Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A device mounting board has a double-layer wiring structure where a first wiring layer and a second wiring layer are stacked together with an insulating layer held between the first and second wiring layers. The first wiring layer and the second wiring layer are electrically connected by way of a via conductor provided on a side wall of a through-hole that penetrates the insulating layer. The through-hole that penetrates the insulating layer has a stepped portion. The via conductor, provided along the insulating layer in the via conductor, has a step associated with the stepped portion of the via conductor.
Description
Technical Field
The present invention relates to a substrate for mounting an element, a method for manufacturing the same, a semiconductor module, and a portable device on which the semiconductor module is mounted.
Background
In the process of accelerating the higher functionality of portable electronic devices such as mobile phones, PDAs, DVCs, and DSCs, it is necessary to reduce the size and weight of such products in order to be acceptable to the market, and highly integrated system LSIs are required in order to achieve the reduction in size and weight. On the other hand, these electronic devices are required to be used more conveniently, and LSIs used in the devices are required to have higher functions and higher performance. Therefore, as the number of I/O increases with the high integration of LSI chips, the size and thickness of the package itself are strongly required to be reduced, and in order to achieve both of these requirements, the development of a semiconductor package suitable for high-density substrate mounting of semiconductor components is strongly required. In order to meet such a demand, a device mounting substrate for mounting a semiconductor component is required to be further thinned.
Fig. 14 shows a cross section of a conventional device mounting substrate having a two-layer wiring structure. As shown in fig. 14, a wiring layer 510 and a wiring layer 520 are laminated via an insulating layer 500. A through hole 530 is formed in the insulating layer 500, and a via conductor 540 is formed along a sidewall of the through hole 530 by an electroplating method. The wiring layer 510 and the wiring layer 520 are electrically connected by this via conductor 540.
In the conventional substrate for mounting an element, the via conductor formed in the through-hole is a thin film of about 10 μm, and therefore, there is a problem that the via conductor is easily peeled from the insulating film in the through-hole. In particular, when the insulating layer is provided with a through hole, drilling is performed. Therefore, the side wall of the through hole is linear from one surface of the element mounting substrate to the other surface. In this case, when a force such as bending the element mounting substrate is applied, a vertical shift is likely to occur between the insulating layer and the via conductor in the through hole due to stress, and there is a concern that the connection reliability of the element mounting substrate may be lowered.
Disclosure of Invention
The present invention has been made in view of the above problems, and an object thereof is to provide a technique for improving the adhesion between a via conductor electrically connected between wiring layers laminated with an insulating layer interposed therebetween and an insulating layer, and further improving the connection reliability of an element mounting substrate.
The device mounting board of the present invention includes: the wiring board includes an insulating layer, a first wiring layer provided on one surface of the insulating layer, a second wiring layer provided on the other surface of the insulating layer, a through hole penetrating the insulating layer, and a conductor provided along a sidewall of the through hole and electrically connecting the first wiring layer and the second wiring layer, wherein a step is provided in the through hole.
According to this embodiment, since the step portion can suppress the via conductor from moving in the substrate lamination direction (axial direction of the through hole) by providing the step in the through hole, the via conductor can be suppressed from being displaced from the insulating layer and being peeled off.
In the above aspect, the through-hole may be formed of a first region having an opening on one surface side of the insulating layer and a second region having an opening on the other surface side of the insulating layer and connected to the first region, and the first region may be offset in the surface direction of the insulating layer with respect to the second region. In this case, the diameter of the through hole in the first region and the diameter of the through hole in the second region may be the same.
In the above aspect, the through-hole may include a first region having an opening on one surface side of the insulating layer and a second region having an opening on the other surface side of the insulating layer and connected to the first region, and at least a part of the second region may be located inside the first region when viewed in a projection direction perpendicular to the surface of the insulating layer.
Another embodiment of the present invention provides a method for manufacturing a substrate for mounting an element. The method for manufacturing a device mounting substrate is characterized by comprising the following steps: preparing an insulating layer having a first metal layer on one surface and a second metal layer on the other surface; selectively removing a predetermined region of the first metal layer to form a first opening; forming a second opening by removing a part of the predetermined region of the second metal layer at a position partially shifted in the surface direction from the predetermined region of the first metal layer; irradiating the first opening with laser light to open the insulating layer to the middle, thereby forming a first hole in the insulating layer; a step of irradiating the second opening portion with laser light to open the insulating layer halfway, and forming a second hole connected to the first hole in the insulating layer, thereby forming a through hole in the insulating layer; forming a conductor along a sidewall of the through hole to electrically connect the first metal layer and the second metal layer; patterning the first metal layer to form a first wiring layer; and patterning the second metal layer to form a second wiring layer.
According to this aspect, the through hole having the step can be formed in the insulating layer, and the via conductor can be formed along the through hole. Thus, the via conductors can be prevented from moving in the substrate lamination direction (axial direction of the through holes) by the step portions, and the via conductors can be prevented from being displaced from the insulating layers and being peeled off.
In the manufacturing method of the above aspect, the diameter of the laser beam irradiated from the second opening may be different from the diameter of the laser beam irradiated from the first opening.
In another aspect, the present invention provides a semiconductor device. The semiconductor device is characterized by comprising: the device mounting substrate of any one of the above-described embodiments, and the semiconductor device mounted on the device mounting substrate.
According to this aspect, the connection reliability of the semiconductor device can be improved.
Yet another aspect of the invention provides a portable device. The portable device is characterized by being equipped with the semiconductor module.
According to this mode, the connection reliability of the portable device can be improved.
In addition, a combination of the above elements is also included in the scope of the present invention.
Drawings
Fig. 1 is a sectional view showing a structure of a semiconductor module according to embodiment 1;
fig. 2(a) to (E) are process sectional views showing a method for manufacturing the device mounting substrate according to embodiment 1;
fig. 3(a) to (C) are process sectional views showing a method for manufacturing the device mounting substrate according to embodiment 1;
fig. 4(a) to (B) are process sectional views showing a method for manufacturing the device mounting substrate according to embodiment 1;
fig. 5 is a sectional view showing the structure of a semiconductor module according to embodiment 2;
fig. 6 is a sectional view showing the structure of a semiconductor module according to embodiment 3;
fig. 7 is a sectional view showing the structure of a semiconductor module according to embodiment 4;
fig. 8 is a sectional view showing the structure of a semiconductor module according to embodiment 5;
fig. 9 is a structural diagram showing a mobile phone including the semiconductor module of the embodiment;
fig. 10 is a partial sectional view (sectional view of the first housing) showing the cellular phone shown in fig. 9;
fig. 11 is a cross-sectional view showing an opening portion when a through-hole is formed in the device mounting substrate according to the modification;
fig. 12 is a cross-sectional view showing a structure of a semiconductor module according to a modification;
fig. 13 is a cross-sectional view showing a structure of a semiconductor module according to another modification;
fig. 14 is a cross-sectional view of a conventional device mounting substrate having a two-layer wiring structure.
Detailed Description
The invention will now be described with reference to preferred embodiments. This does not limit the scope of the invention but merely exemplifies the invention.
Embodiments of the present invention will be described below with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
(embodiment mode 1)
Fig. 1 is a sectional view showing the structure of a semiconductor module 10 according to embodiment 1. The semiconductor module 10 is a package structure in which a semiconductor element 30 is mounted on an element mounting substrate 20.
The device mounting substrate 20 has a two-layer wiring structure in which the first wiring layer 40 and the second wiring layer 50 are laminated with the insulating layer 60 interposed therebetween. The first wiring layer 40 and the second wiring layer 50 are each formed of a metal having good conductivity, such as copper. The device mounting substrate 20 is thin without a support substrate, and can mount semiconductor devices and the like at high density. The ISB (registered trademark) developed by the present applicant realizes the above-described structure, and details thereof are described in detail in, for example, japanese laid-open patent publication No. 2002-110717.
The insulating layer 60 is formed by impregnating glass cloth with an insulating resin, and the resin is preferably a melamine derivative such as an epoxy resin or a BT resin, a liquid crystal polymer, a PPE resin, a polyimide resin, a fluororesin, a phenol resin, or an organic resin such as polyamide bismaleimide. The thickness of the insulating layer 60 is, for example, 110 μm.
The first wiring layer 40 and the second wiring layer 50 are electrically connected via conductors 64, and the via conductors 64 are provided on the side walls of the through holes (through holes) 62 penetrating the insulating layer 60. The diameter of the through hole 62 is, for example, 75 μm. The via conductor 64 is formed of a metal having good conductivity, such as copper. The thickness of the via conductor 64 is, for example, 10 μm.
The through hole 62 penetrating the insulating layer 60 is provided with a step 66. In order to provide the via conductor 64 along the insulating layer 60 in the through hole 62, a step corresponding to the step 66 is also formed in the via conductor 64. By providing the step 66 in the through hole 62 in this manner, the step 66 portion can suppress the via conductor 64 from moving in the substrate lamination direction (axial direction of the through hole 62), and thus the via conductor 64 can be suppressed from being displaced from the insulating layer 60 and being peeled off. In other words, the step 66 provided in the through hole 62 functions as a stopper for suppressing the via conductor 64 from being displaced in the substrate stacking direction.
The height of the step 66 is preferably lower than the film thickness of the via conductor 64. Thus, the via conductor 64 is easily formed in the step 66 in accordance with the shape of the insulating layer 60, and therefore, the continuity of the via conductor 64 in the step 66 can be improved. In particular, since the step 66 can be sufficiently covered by forming the via conductor 64 by electroless plating or electrolytic plating, the occurrence of disconnection in the via conductor 64 due to the step 66 can be suppressed.
A plurality of electrode pads 52 are provided in an array at predetermined positions in the second wiring layer 50 on the lower surface side of the element mounting substrate 20. A solder ball 54 is bonded to each electrode pad 52. A heat-resistant solder resist layer 56 is provided on the lower surface of the device mounting substrate 20 in the gap portion between the electrode pads 52. The insulating layer 60 is protected from damage by heat during soldering by the solder resist layer 56.
On the other hand, a plurality of electrode pads 42 are provided at predetermined positions in the first wiring layer 40 on the upper surface side of the device mounting substrate 20. The electrode pads 42 are used for flip-chip connection with the semiconductor element 30. A heat-resistant solder resist layer 44 is provided on the upper surface of the device mounting board 20 in a gap portion between the electrode pads 42. The insulating layer 22 is protected from damage by heat during soldering by the solder resist layer 44.
The semiconductor element 30 is an active element such as an IC (integrated circuit) or an LSI (large scale integrated circuit). The semiconductor element 30 is flip-chip connected to the upper surface of the element-mounting board 20 with the surface on which the electrode pad 32 is formed facing downward. Specifically, the electrode pads 32 provided on the semiconductor element 30 and the electrode pads 42 provided on the element-mounting board 20 are electrically connected via solder balls 70. The adjacent electrode pads 32 are protected by a protective layer 34 made of resin such as polyimide. The underfill 80 is filled between the semiconductor element 30 and the element mounting board 20 (アンダ to フイル). The joint portion between the electrode pad 42 and the solder ball 70 is protected by the underfill 80. The semiconductor element 30 mounted on the element mounting substrate 20 is sealed with a sealing resin 90 to form a package.
(production method)
A method for manufacturing the device mounting substrate 20 according to embodiment 1 will be described with reference to fig. 2 to 4.
Next, as shown in fig. 2(a), an insulating layer 60 is prepared, and the insulating layer 60 is provided with a first metal layer 100 made of copper foil on one surface and a second metal layer 111 made of copper foil on the other surface.
Next, as shown in fig. 2(B), a resist 102 and a resist 113 are patterned on the first metal layer 100 and the second metal layer 111, respectively, using photolithography. A resist 102 is formed so that the first metal layer 100 is partially exposed in the first opening 104. Further, a resist 113 is formed so that the second metal layer 111 is partially exposed in the second opening 115. The first opening 104 is formed offset by, for example, 3 to 5 μm in the surface direction (the left-right direction in the drawing) of the insulating layer 60 with respect to the second opening 115. The first opening 104 and the second opening 115 have, for example, diameters of 75 μm.
Next, as shown in fig. 2(C), the first metal layer 100 in the first opening 104 and the second metal layer 111 in the second opening 115 are removed by a wet etching technique using ferric chloride.
Then, as shown in fig. 2(D), after the resist 102 and the resist 113 are removed, the first opening 104 is irradiated with CO2A laser (e.g., 10 musec, three shots) is used to open (dig) the insulating layer 60 halfway therethrough to form a first hole 106. To pairThe diameter of the laser beam emitted from the first opening 104 is, for example, 100 μm.
Subsequently, as shown in fig. 2(E), the second opening 115 is irradiated with CO2The laser light (for example, 10 μ sec, three shots) opens the insulating layer 60 halfway, and a second hole 117 is formed. The diameter of the laser beam irradiated to the second opening 115 is, for example, 100 μm. The second hole 117 is bored until it joins the first hole 106. Thereby, the through hole 62 is formed in the insulating layer 60. In addition, due to CO2Since the first opening 104 irradiated with the laser beam is shifted in the surface direction of the insulating layer 60 with respect to the second opening 115, the step 66 is formed in the through hole 62. The first hole 106 corresponds to a "first region" of the through hole of the present invention, and the second hole 117 corresponds to a "second region" of the through hole of the present invention.
Furthermore, the first opening 104 and the second opening 115 are irradiated with CO2In the case of laser, CO may be fixed2Light source for laser, replacement and CO2The light source of the laser light is opposite the surface of the insulating layer 60.
Next, as shown in fig. 3(a), via conductors 64 made of copper are formed on the side walls of the through holes 62 by electroless plating and electrolytic plating. The thickness of the via conductor 64 is, for example, 10 μm. Since the through hole 62 is provided with the step 66, the via conductor 64 provided along the insulating layer 60 is also formed with a step corresponding to the step 66. In addition, the first metal layer 100 and the second metal layer 111 are thickened by electroplating.
Next, as shown in fig. 3(B), the first metal layer 100 and the second metal layer 111 are patterned to form the first wiring layer 40 and the second wiring layer 50, respectively.
Next, as shown in fig. 3(C), electrode pads 42 are formed at predetermined portions of the first wiring layer 40. Further, electrode pads 52 are formed at predetermined portions of the second wiring layer 50. The electrode pads 42 and 52 can be formed by forming a Ni/Au layer by electroplating.
Next, as shown in fig. 4(a), a solder resist layer 44 and a solder resist layer 56 are formed on the surfaces of the insulating layer 60 in the gap portion of the first wiring layer 40 and the insulating layer 60 in the gap portion of the second wiring layer 50, respectively.
Next, as shown in fig. 4(B), an external connection solder ball 54 is mounted on the electrode pad 52.
Through the above steps, the device mounting substrate 20 of embodiment 1 can be manufactured.
(embodiment mode 2)
Fig. 5 is a sectional view showing the structure of a semiconductor module 10 according to embodiment 2. As in embodiment 1, the semiconductor module 10 of the present embodiment is a package structure in which a semiconductor element 30 is mounted on an element mounting substrate 20. Hereinafter, the semiconductor module 10 of embodiment 2 will be mainly described as different from that of embodiment 1, with the description of the same structure as that of embodiment 1 appropriately omitted.
In the semiconductor module 10 according to embodiment 2, the solder resist layer 44 is formed on the entire upper surface of the device mounting board 20 except for the mounting region of the solder ball 70. In other words, the solder ball 70 is mounted on the electrode pad 42 at the opening portion of the solder resist layer 44 formed on the entire upper surface of the device mounting substrate 20. Similarly, a solder resist layer 56 is formed on the entire lower surface of the device mounting substrate 20 except for the mounting regions of the solder balls 54. The solder resist layer 45 is embedded in the through hole 62.
The basic manufacturing method of the device mounting substrate 20 used for the semiconductor module 10 of embodiment 2 is the same as that of embodiment 1 (fig. 2 to 4). In the present embodiment, after the step shown in fig. 3(C), the solder resist layer 45 is embedded in the through hole 62, and the solder resist layer 44 and the solder resist layer 56 are formed on the entire surface of the insulating layer 60 on the first wiring layer 40 side and the entire surface of the insulating layer 60 on the second wiring layer 50 side, respectively. After that, the remaining portions are exposed to light using a resist mask and hardened, and thereafter unnecessary portions are removed, whereby openings corresponding to the electrode pads 42 and 52 are formed in the solder resist layer 44 and the solder resist layer 56, respectively. The subsequent steps are the same as those described in embodiment 1 below with reference to fig. 4 (B).
According to this embodiment, the penetration of moisture from the outside into the semiconductor module 10 can be suppressed by filling the through-hole 62 with the solder resist layer 45.
Further, by filling the solder resist layer 45 in the through hole 62, the movement of the via conductor 64 is suppressed by the solder resist layer 45, and disconnection of the via conductor 64 due to thermal shrinkage can be suppressed.
With the above-described effects, the connection reliability of the semiconductor module 10 can be further improved.
(embodiment mode 3)
Fig. 6 is a sectional view showing the structure of a semiconductor module 10 according to embodiment 3. As in embodiment 1, the semiconductor module 10 of the present embodiment is a package structure in which a semiconductor element 30 is mounted on an element mounting substrate 20. Hereinafter, the semiconductor module 10 according to embodiment 3 will be mainly described as different from embodiment 1, with the same configuration as that of embodiment 1 appropriately omitted.
In the semiconductor module 10 according to embodiment 3, the solder resist layer 44 is formed on the entire upper surface of the device mounting board 20 except for the lower portion of the mounting region of the semiconductor device 30 and the mounting region of the solder ball 70. An underfill material 80 is filled between the insulating layer 60 and the first wiring layer 40 under the mounting region of the semiconductor element 30. Then, the underfill material 80 fills the through holes 62 from the openings of the through holes 62 on the first wiring layer 40 side to the middle of the through holes 62 (from the openings of the through holes 62 on the first wiring layer 40 side to the central portion in the hole direction).
On the other hand, a solder resist layer 56 is formed on the entire lower surface of the device mounting substrate 20 except for the mounting regions of the solder balls 54. Further, the solder resist layer 56 fills the through holes 62 from the openings of the through holes 62 on the second wiring layer 50 side to the middle of the through holes 62 (from the openings of the through holes 62 on the second wiring layer 50 side to the central portion in the hole direction).
The basic manufacturing method of the device mounting substrate 20 used for the semiconductor module 10 of embodiment 3 is the same as that of embodiment 1 (fig. 2 to 4). In the present embodiment, after the step shown in fig. 3(C), the solder resist layer is embedded in the through hole 62, and the solder resist layer 44 and the solder resist layer 56 are formed on the entire surface of the insulating layer 60 on the first wiring layer 40 side and the entire surface of the insulating layer 60 on the second wiring layer 50 side, respectively. After that, the remaining portions are exposed to light using a resist mask and hardened, and then unnecessary portions are removed, whereby the solder resist layer 44 is formed on the entire upper surface of the device mounting substrate 20 except for the lower portion of the mounting region of the semiconductor device 30 and the mounting region of the solder ball 70. At this time, the through-holes 62 are hollow from the opening on the first wiring layer 40 side of the through-holes 62 to the middle of the through-holes 62. On the other hand, the solder resist layer 56 on the surface of the insulating layer 60 on the second wiring layer 50 side forms openings corresponding to the electrode pads 52. The solder resist layer is left from the opening of the through hole 62 on the second wiring layer 50 side to the halfway of the through hole 62, and becomes a part of the solder resist layer 56. The subsequent steps are the same as those described in embodiment 1 below with reference to fig. 4 (B). After the semiconductor element 30 is mounted on the element mounting substrate 20, when the underfill material 80 is filled between the element mounting substrate 20 and the semiconductor element 30, the underfill material 80 is also filled in a cavity formed from the opening of the through hole 62 on the first wiring layer 40 side to the middle of the through hole 62.
According to the present embodiment, the underfill 80 and the solder resist layer 56 are filled in the through hole 62, whereby the penetration of moisture from the outside into the semiconductor module 10 can be suppressed.
Further, by filling the underfill 80 and the solder resist layer 56 in the through hole 62, the movement of the via conductor 64 can be suppressed by the solder resist layer 56, and disconnection of the via conductor 64 due to thermal shrinkage can be suppressed.
Due to the above effects, the connection reliability of the semiconductor device 10 can be further improved.
In the present embodiment, the solder resist layer 44 is not formed on the upper surface of the device mounting board 20 corresponding to the lower portion of the mounting region of the semiconductor device 30. Thus, interference between the solder ball 70 and the solder resist layer 44 is suppressed in the mounting region of the semiconductor element 30, so that the size of the solder ball 70 can be reduced, and the gap between the element mounting board 20 and the semiconductor element 30 can be shortened, that is, the semiconductor module 10 can be thinned (reduced in height).
(embodiment mode 4)
Fig. 7 is a sectional view showing the structure of a semiconductor module 10 according to embodiment 4. As in embodiment 1, the semiconductor module 10 of the present embodiment is a package structure in which a semiconductor element 30 is mounted on an element mounting substrate 20. Hereinafter, the semiconductor module 10 according to embodiment 4 will be mainly described as different from embodiment 1, with the same configuration as that of embodiment 1 appropriately omitted.
In the semiconductor module 10 according to embodiment 4, the solder resist layer 44 is formed on the entire upper surface of the device mounting board 20 except for the mounting region of the solder ball 70. In other words, the solder ball 70 is mounted on the electrode pad 42 at the opening portion of the solder resist layer 44 formed on the entire upper surface of the device mounting substrate 20. Similarly, a solder resist layer 56 is formed on the entire lower surface of the device mounting substrate 20 except for the mounting regions of the solder balls 54. The via conductor 64 is embedded in the through hole 62.
The basic manufacturing method of the element mounting substrate 20 used for the semiconductor module 10 of embodiment 4 is the same as that of embodiment 1 (fig. 2 to 4). In the present embodiment, in the plating step shown in fig. 3(a), after the via conductor 64 is embedded in the entire through hole 62, the plated films formed on both main surfaces of the insulating layer 60 are subjected to a thinning treatment. After the processes shown in fig. 3(B) to 3(C), the solder resist layer 44 and the solder resist layer 56 are formed on the entire surface of the insulating layer 60 on the first wiring layer 40 side and the entire surface of the insulating layer 60 on the second wiring layer 50 side, respectively. After that, the remaining portions are exposed to light using a resist mask and hardened, and thereafter unnecessary portions are removed, whereby openings corresponding to the electrode pads 42 and 52 are formed in the solder resist layer 44 and the solder resist layer 56, respectively. The subsequent steps are the same as those described in embodiment 1 below with reference to fig. 4 (B).
According to the present embodiment, since the via conductor 64 is formed over the entire through hole 62, the resistance of the via conductor 64 can be reduced, and the electrical characteristics of the semiconductor module 10 can be improved.
Further, since the step 66 is provided in the through hole 62 filled with the via conductor 64, stress is generated in a dispersed manner in the step 66. As a result, stress concentration at the corner of the via conductor 64 on the first wiring layer 40 side and the corner of the via conductor 64 on the second wiring layer 50 side can be suppressed, peeling of the via conductor 64 or cracking of the via conductor 64 can be suppressed, and reliability of the semiconductor module 10 can be improved.
(embodiment 5)
Fig. 8 is a sectional view showing the structure of a semiconductor module 10 according to embodiment 5. The semiconductor module 10 of the present embodiment is a modification of the semiconductor module 10 of embodiment 4. Next, the same configuration as that of embodiment 4 will be omitted as appropriate for the semiconductor module 10 of embodiment 5, and the configuration different from that of embodiment 1 will be mainly described.
In the semiconductor module 10 according to embodiment 5, as in embodiment 3, the solder resist layer 44 is formed on the entire upper surface of the device mounting board 20 except for the lower portion of the mounting region of the semiconductor device 30 and the mounting region of the solder ball 70. An underfill material 80 is filled between the insulating layer 60 and the first wiring layer 40 under the mounting region of the semiconductor element 30. In addition, as in embodiment 4, the through hole 62 is filled with a via conductor 64.
According to the present embodiment, since the via conductor 64 is formed in the entire through hole 62, the resistance of the via conductor 64 can be reduced, and the electrical characteristics of the semiconductor module 10 can be improved.
Further, since the through hole 62 filled with the via conductor 64 is provided with the step 66, stress is generated dispersedly at this step 66. As a result, stress concentration at the corner of the via conductor 64 on the first wiring layer 40 side and the corner of the via conductor 64 on the second wiring layer 50 side can be suppressed, peeling of the via conductor 64 or cracking of the via conductor 64 can be suppressed, and reliability of the semiconductor module 10 can be improved.
The solder resist layer 44 is not formed on the upper surface of the device mounting substrate 20 corresponding to the lower portion of the mounting region of the semiconductor device 30. Thus, interference between the solder balls 70 and the solder resist layer 44 is suppressed in the mounting region of the semiconductor element 30, so that the size of the solder balls 70 can be reduced, and the gap between the element mounting board 20 and the semiconductor element 30 can be reduced, that is, the semiconductor module 10 can be thinned.
Next, a portable device including the semiconductor module of the present invention will be described. Although a mobile device is shown as an example mounted on a mobile phone, the mobile device may be an electronic device such as a Personal Digital Assistant (PDA), a Digital Video Camera (DVC), a music player, and a Digital Still Camera (DSC).
Fig. 9 is a structural diagram showing a mobile phone including a semiconductor module according to an embodiment of the present invention. The mobile phone 110 has a structure in which a first housing 112 and a second housing 114 are coupled to each other by a movable portion 120. The first housing 112 and the second housing 114 are rotatable about the movable portion 120. The first housing 112 is provided with a display unit 118 for displaying information such as characters and images, and a speaker unit 124. The second housing 114 is provided with an operation unit 122 such as an operation button and a microphone unit 126. The semiconductor module according to each embodiment of the present invention is mounted inside the mobile phone 110. As described above, the semiconductor module of the present invention mounted on a mobile phone can be used as a power supply circuit for driving each circuit, an RF generation circuit for generating RF, a DAC, an encoder circuit, a driving circuit for a backlight of a liquid crystal panel used in a display unit of a mobile phone, and the like.
Fig. 10 is a partial sectional view of the cellular phone shown in fig. 9 (a sectional view of the first housing 112). The semiconductor module 10 according to the embodiment of the present invention is mounted on the printed board 128 via the external connection electrodes (solder balls) 54, and electrically connected to the display portion 118 and the like via the printed board 128. Further, by providing a heat dissipating substrate 116 such as a metal substrate on the back surface side (the surface opposite to the external connection electrode 9) of the semiconductor module 10, it is possible to efficiently dissipate heat generated from the semiconductor module 10 to the outside of the first housing 112 without concentrating the heat inside the first housing 112.
According to the portable device including the semiconductor module according to the embodiment of the present invention, the following effects can be obtained.
In the element mounting substrate constituting the semiconductor module 10, since peeling of the via conductor connected between the wiring layers from the insulating layer is suppressed, the reliability of the semiconductor module 10 is improved, and therefore the reliability of the portable device on which such a semiconductor module 10 is mounted is improved.
Since the heat from the semiconductor element 10 can be efficiently released to the outside through the heat dissipation substrate 116, the temperature rise of the semiconductor element 10 can be suppressed, and the thermal stress between the rewiring pattern 4 and the insulating layer 7 can be reduced. Therefore, as compared with the case where the heat dissipation substrate 116 is not provided, the reliability of connection between the electrodes and the bumps (heat-resistant reliability) is improved, and the re-wiring pattern 4 in the semiconductor module is prevented from being peeled off from the insulating layer 7, thereby improving the reliability of the semiconductor module 10 (heat-resistant reliability). As a result, the reliability (heat-resistant reliability) of the portable device can be improved.
Since the semiconductor module 10 can be made thinner and smaller by using the element mounting substrate manufactured by the manufacturing process described in the above embodiment, a portable device having such a semiconductor module 10 mounted thereon can be made thinner and smaller.
As described above, conventionally, the through-hole 530 is provided in the insulating layer 500 of the device mounting substrate by drilling. In this case, when the insulating layer is a harder insulating layer, or when a through hole is opened in the device mounting substrate from one side by a drilling process by stacking a plurality of insulating layers and a substrate having wiring layers on both surfaces thereof, the openings on the upper surface and the lower surface of the through hole may be largely deviated (several tens μm). Therefore, it is necessary to obtain a margin (マ - ジン) in which the "offset amount" is predicted in advance, and thus, it is difficult to realize both the thinning and the miniaturization of a semiconductor module or a portable device including an element mounting board, not only an element mounting board.
However, when the step of several μm as in the present application is formed, the element mounting substrate is increased only by the size corresponding to the step, and therefore, the element mounting substrate can be thinned and downsized. Further, since the "offset amount" is larger than the step by forming the through holes from both surfaces of the element mounting board than the case of forming the through holes from only one surface, the element mounting board, the semiconductor module and the portable device having the element mounting board can be thinned and miniaturized by adopting the configuration of the present application.
The present invention is not limited to the above-described embodiments, and various design changes and the like can be added based on the knowledge of those skilled in the art, and embodiments to which such modifications are added are also included in the scope of the present invention.
For example, in the above embodiment, in order to form the through hole 62 having the step 66 in the insulating layer 60, one CO is used2The laser irradiates the first opening 104 and the second opening 115 with laser light in this order (see fig. 2D and 2E), but two CO may be used2The laser irradiates the first opening 104 and the second opening 115 with laser light at the same time, thereby forming the through hole 62.
In the above embodiment, the step 66 is formed in the through hole 62 by making the first opening 104 and the second opening 115 have the same diameter and shifting the position where the first opening 104 is provided in the surface direction with respect to the second opening 115, but the method of forming the step 66 is not limited to this. For example, as shown in FIG. 11The aperture of the first opening 104 is made larger than the aperture of the second opening 115, and the second opening 115 is provided in the region of the first opening 104 when viewed from the substrate stacking direction. The first opening 104 is irradiated with CO2Laser is applied to the second opening 115 after the insulating layer 60 is formed halfway through the hole2The laser beam forms the through hole 62 in the insulating layer 60, so that a step can be formed in the through hole 62.
Fig. 12 is a cross-sectional view showing the structure of the semiconductor element 10 manufactured through the step formation step shown in fig. 11. In the present modification, the through-hole 62 is composed of the first region 67 and the second region 68. The first region 67 has an opening on one surface side (upper side in fig. 12) of the insulating layer 60. The second region 68 has an opening on the other surface side (lower side in fig. 12) of the insulating layer 60, and is connected to the first region 67. As shown in fig. 12, the through-holes 62 of the first region 67 have a larger diameter than the through-holes 62 of the second region 68. Therefore, the second region 68 is located inside the first region 67 when viewed from a projection direction (upward in fig. 12) perpendicular to the surface of the insulating layer 60. The same effects as those of the above embodiment can be obtained with this configuration. The through-hole 62 may have a step 66. Therefore, a part of the second region 68 may also be located inside the first region 67 when viewed from a projection direction perpendicular to the surface of the insulating layer 60.
Fig. 13 is a cross-sectional view showing the structure of a semiconductor module according to another modification. In the present modification, the diameter of the through-hole 62 of the first region 67 is smaller than the diameter of the through-hole 62 of the second region 68. Therefore, the first region 67 is located inside the second region 68 when viewed from a projection direction (downward in fig. 12) perpendicular to the surface of the insulating layer 60. The same effects as those of the above embodiment can be obtained with this configuration.
This application is based on and claims priority from prior japanese patent application No. 2008-022061, filed on 31/2008, and prior japanese patent application No. 2009-011616, filed on 22/2009, which are hereby incorporated by reference in their entirety.
Claims (7)
1. A substrate for mounting a device, comprising:
an insulating layer;
a first wiring layer provided on one surface of the insulating layer;
a second wiring layer provided on the other surface of the insulating layer;
a through hole penetrating the insulating layer; and
a conductor provided along a side wall of the through hole and electrically connecting the first wiring layer and the second wiring layer; wherein,
the through hole is provided with a step.
2. The device-mounting board according to claim 1, wherein,
the through-hole is composed of a first region having an opening on one surface side of the insulating layer and a second region having an opening on the other surface side of the insulating layer and connected to the first region,
the first region is offset in a surface direction of the insulating layer with respect to the second region.
3. The device-mounting board according to claim 2, wherein,
the through-hole of the first region has the same diameter as the through-hole of the second region.
4. The device-mounting board according to claim 1, wherein,
the through hole is composed of a first region having an opening on one surface side of the insulating layer and a second region having an opening on the other surface side of the insulating layer and connected to the first region;
at least a part of the second region is located inside the first region when viewed from a projection direction perpendicular to a surface of the insulating layer.
5. A method for manufacturing a substrate for mounting a device, comprising:
preparing an insulating layer having a first metal layer on one surface and a second metal layer on the other surface;
selectively removing a predetermined region of the first metal layer to form a first opening;
forming a second opening by removing a part of the predetermined region of the second metal layer at a position partially shifted in a surface direction from the predetermined region of the first metal layer;
irradiating the first opening with laser light to open the insulating layer halfway, thereby forming a first hole in the insulating layer;
a step of irradiating the second opening with laser light to open the insulating layer halfway, and forming a second hole connected to the first hole in the insulating layer to form a through hole in the insulating layer;
forming a conductor along a sidewall of the through hole to electrically connect the first metal layer and the second metal layer;
patterning the first metal layer to form a first wiring layer; and
and patterning the second metal layer to form a second wiring layer.
6. The method of manufacturing a device mounting substrate according to claim 5, wherein the substrate is a semiconductor substrate,
the diameter of the laser beam irradiated from the second opening is different from the diameter of the laser beam irradiated from the first opening.
7. A semiconductor assembly, comprising:
the substrate for mounting a device according to claim 1; and
and a semiconductor element mounted on the element mounting substrate.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP022061/08 | 2008-01-31 | ||
| JP2008022061 | 2008-01-31 | ||
| JP011616/09 | 2009-01-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101510538A true CN101510538A (en) | 2009-08-19 |
Family
ID=41002872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910130758 Pending CN101510538A (en) | 2008-01-31 | 2009-02-01 | Device mounting board and manufacturing method, semiconductor module and portable apparatus therefor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101510538A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103096619A (en) * | 2011-10-28 | 2013-05-08 | 精工爱普生株式会社 | Circuit substrate, electronic device, electronic apparatus and method of manufacturing circuit substrate |
| CN103443915A (en) * | 2011-03-22 | 2013-12-11 | 瑞萨电子株式会社 | Semiconductor device |
| CN105159027A (en) * | 2015-07-31 | 2015-12-16 | 瑞声声学科技(深圳)有限公司 | Photo mask structure applicable to MEMS (micro-electro-mechanic system) microphone and manufacturing method for photo mask structure |
| CN107637183A (en) * | 2015-03-13 | 2018-01-26 | 奥特斯奥地利科技与系统技术有限公司 | Include the parts carrier of warpage rock-steady structure |
| CN111083879A (en) * | 2019-07-26 | 2020-04-28 | 微智医疗器械有限公司 | Connection method of electronic element and circuit board, circuit board assembly and electronic equipment |
| CN111508923A (en) * | 2019-01-31 | 2020-08-07 | 奥特斯奥地利科技与系统技术有限公司 | Making through-holes with low offset in component carrier material |
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2009
- 2009-02-01 CN CN 200910130758 patent/CN101510538A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103443915A (en) * | 2011-03-22 | 2013-12-11 | 瑞萨电子株式会社 | Semiconductor device |
| US9293405B2 (en) | 2011-03-22 | 2016-03-22 | Renesas Electronics Corporation | Semiconductor device |
| CN103443915B (en) * | 2011-03-22 | 2016-08-17 | 瑞萨电子株式会社 | Semiconductor device |
| CN103096619A (en) * | 2011-10-28 | 2013-05-08 | 精工爱普生株式会社 | Circuit substrate, electronic device, electronic apparatus and method of manufacturing circuit substrate |
| CN107637183A (en) * | 2015-03-13 | 2018-01-26 | 奥特斯奥地利科技与系统技术有限公司 | Include the parts carrier of warpage rock-steady structure |
| US10420206B2 (en) | 2015-03-13 | 2019-09-17 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier comprising a deformation counteracting structure |
| CN107637183B (en) * | 2015-03-13 | 2020-05-01 | 奥特斯奥地利科技与系统技术有限公司 | Component carrier comprising warpage stabilizing structure |
| CN105159027A (en) * | 2015-07-31 | 2015-12-16 | 瑞声声学科技(深圳)有限公司 | Photo mask structure applicable to MEMS (micro-electro-mechanic system) microphone and manufacturing method for photo mask structure |
| CN105159027B (en) * | 2015-07-31 | 2019-09-10 | 瑞声声学科技(深圳)有限公司 | Photomask structure and preparation method thereof suitable for MEMS microphone |
| CN111508923A (en) * | 2019-01-31 | 2020-08-07 | 奥特斯奥地利科技与系统技术有限公司 | Making through-holes with low offset in component carrier material |
| CN111508923B (en) * | 2019-01-31 | 2024-03-26 | 奥特斯奥地利科技与系统技术有限公司 | Manufacturing through holes with low offset in component carrier material |
| CN111083879A (en) * | 2019-07-26 | 2020-04-28 | 微智医疗器械有限公司 | Connection method of electronic element and circuit board, circuit board assembly and electronic equipment |
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Application publication date: 20090819 |