CN101524926B - Printer loose-coupling control mode based on programmable logic - Google Patents
Printer loose-coupling control mode based on programmable logic Download PDFInfo
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Abstract
The invention discloses a printer loose-coupling control mode based on programmable logic, which can solve the problem that a printer control mode in the prior art can not consider the high reliability and the cost reduction at the same time. The printer loose-coupling control mode adopts the following technical schemes: a programmable logical device is connected between a printer controller and an external driving port and realizes the I/O bridging function by hardware language programme; and whatever any CPU is adopted by a system, the printer loose-coupling control mode can map the intelligent control to a motor, a firing pin, a communication port of an external IEEE1284 device and other functional subsystems by the operation of a data bus to an I/O bridge.
Description
Technical field
The invention belongs to the printer apparatus technical field, relate to printer loose-coupling control mode specifically based on FPGA.
Background technology
CPU provides inner interruption and timer resource to cooperate the work of I/O bridge circuit, realizes obtaining data from the external communication port, and data are resolved, and outputs to the external drive of motor and striker equipment.Coupling between existing printer cpu subsystem and peripheral hardware such as the functional subsystems such as motor, striker and exterior I EEE1284 device talk port is too tight, as shown in Figure 1, driving such as motor, striker directly is connected on the I/O of CPU, this kind design is had relatively high expectations to CPU, usually need special control CPU or require CPU to have many I/O and high current drive capability, thereby cause the transplanting of system and expand extremely difficult; On the other hand,, will directly feed back to cpu subsystem, cpu subsystem may be damaged, thereby cause unpredictable catastrophic consequences to take place in case damage owing to comprise such as the drive circuit that drives big electric current or high pressure in the peripheral hardware subsystem.
Too tight for fear of coupling, the mode that existing employing cpu subsystem and many functional subsystems are isolated as shown in Figure 2, CPU drives peripheral hardware by the outside addressing mode, adopt between peripheral hardware and the cpu bus and drive and buffer, need multi-disc to drive buffer at different peripheral hardwares and realize, though can improve the anti-index of ruining, a large amount of logical device of inevitable simultaneously introducing, cost increases, and the most important point is the flexibility of having lost control.
Summary of the invention
The present invention is directed to printer control mode in the prior art and can't take into account and heighten reliability and the problem that reduces cost, a kind of printer loose-coupling control mode based on FPGA is provided.
For solving the problems of the technologies described above, the present invention is achieved by the following technical solutions:
A kind of printer loose-coupling control mode based on FPGA comprises the steps:
A, drive between the port at printer controller and peripheral hardware and to be connected PLD;
B, PLD is carried out hardware configuration, define some function registers;
C, the PLD internal function register is mapped to the Memory space of cpu subsystem;
D, cpu subsystem are addressed to inner function register, have realized the operation to internal function register, thus the control peripheral hardware.
Further, described C step comprises the steps:
The BDB Bi-directional Data Bus of c1, PLD design 8bit is connected on 8bit (D0-D7) data/address bus of cpu subsystem;
C2, PLD design input signal pin is connected on the control bus, address bus of cpu subsystem;
C3, PLD design high speed address decoder and bus buffer utilize the cooperation of above-mentioned three kinds of buses and address assignment to distinguish each inner function register;
Further, described B step comprises the steps:
B1, described PLD internal function register is divided into the I/O of system control register, peripheral hardware status register, paper knife assembly control register, cash box assembly prosecution system register, paper feed stepper motor control register, word vehicle and horse reaches control register, at least two row's striker control register and IEEE1284 device port registers;
B2, be that above-mentioned each function register distributes relative address, and the position in each register is defined.
Further, described striker control register comprises A row striker control register, A row striker expansion control register, B row striker control register, B row striker expansion control register.
Described IEEE1284 device port register comprises IEEE1284 device port sign register, IEEE1284 device port data write-only register, IEEE1284 device port data read-only register.
First of described IEEE1284 device port sign register is defined as Paper End and lacks paper signal, second and be defined as the online signal of printer, the 3rd and be defined as printer ERROR signal, the 4th is defined as BUSY signal in the SPP pattern, the 5th is defined as ack signal in the SPP pattern, other three is preserved signal, and certain definition to every is not defined as said sequence.
First of described peripheral hardware status register is used for discerning by the next Initial printer signal in parallel port, second location status sensor signal that is used for discerning hand papercutter, the 3rd is used for discerning Home Position sensor signal, the 4th is used for discerning Paper End sensor signal, the 5th is used for discerning Black Mark sensor signal, the 6th is used for discerning printer word car 110 temperature signals, the 7th is used for discerning printer word car 130 temperature signals, and the 8th is used for discerning cash box state sensor signal.
First of described system I/O control register is defined as system led indication control signal, and described cpu subsystem is reported to the police to system reliability according to the state of system led indication control signal.
Described PLD exterior I/O pin comprises the bus control section, the cash box control section, IEEE1284 device port part, paper knife control section, striker control A control section, striker control B control section, part is posted in the control of paper feed motor and the word vehicle and horse reach control section.
Compared with prior art, advantage of the present invention and good effect are:
The present invention adopts large-scale FPGA (CPLD) to be programmed in by hardware language and realizes the I/O bridging functionality between printer and the peripheral hardware, I/O bridge controller (PLD) only takies the Memory space of system among the present invention, to the I/O resource of cpu subsystem without any take.Play the bridge joint effect by I/O subsystem (PLD) between cpu subsystem and driver sub-system, cpu system can high speed access I/O bridge controller, thereby has realized the control to peripheral system.
Adopt the loose coupling mode between I/O bridge controller and the cpu subsystem, the CPU of any kind no matter, as long as possess the read-write sequence of external RAM/ROM, just can seamlessly be transplanted to the designed I/O bridge controller of the present invention, the portability and the redundancy of system are more complete.
Description of drawings
Fig. 1 is for adopting closely-coupled printer control chart;
Fig. 2 is for adopting the printer control chart of loose coupling;
Fig. 3 is the built-in function block diagram of I/O bridge controller;
Fig. 4 is the PLD schematic diagram.
The specific embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing.
The present invention drives between the port with peripheral hardware at printer controller and is connected FPGA (CPLD) device, realize the I/O bridging functionality by the hardware language programming, no matter which kind of CPU is system adopt, and it can be mapped to Based Intelligent Control to functional subsystems such as motor, striker and exterior I EEE1284 device talk ports to the operation of I/O bridge by data/address bus.
The hardware configuration process of PLD is as follows:
1) according to the pinout of the connected mode of PLD and peripheral hardware decision PLD.As shown in Figure 4, PLD of the present invention is selected XC95144-TQ100 for use, orientate the 76-99 pin as bus portion, cpu subsystem is operated the PLD internal function register by bus portion, the 71-74 pin definitions is the cash box control section, the 52-70 pin definitions is an IEEE1284 device port part, the 48-50 pin definitions is the paper knife control section, the 33-43 pin definitions is a striker A control section, the 27-31 pin definitions is a striker B control section, the 15-20 pin definitions reaches control section for the word vehicle and horse, and the 9-14 pin definitions is a paper feed motor control section, and PLD links to each other with the peripheral hardware printer by above-mentioned control section.
2) definition (described in follow-up table) of the logical bit of the function register inside that needs by the peripheral functionality Demand Design.The realization of I/O bridge subsystem relies on FPGA flexibly, a plurality of function registers are opened up in FPGA inside, what of external address space scope and programmable resource are the function register quantity that can open up only depend on, the present invention defines 13 function registers.
3) adopt the general hardware descriptive language that the function register design is converted into the programming file that can be cured to FPGA inside.
I/O bridge controller of the present invention adopts the Verilog hardware description language to realize inner register, the function realization of when product lot quantity is produced, programming inner by the outside DLL of JTAG, under the situation of huge volume production, can come to come mask production by submitting hardware description language and RTL net meter file to, can reduce production costs greatly to the chip foundries.
4) correctness of the use simulation software functional definition that the simulation hardware descriptive language is realized on PC.
5) programming cable by special use and the PC file of will programming is programmed into that PLD is inner to form real hardware circuit.
The present invention is the Memory space of cpu subsystem with the Flip-Flop register mappings of FPGA inside, as shown in Figure 3, control for I/O bridge subsystem is quick and convenient just as cpu subsystem read-write memory subsystem, below realizes the mapping in the Memory space of Flip-Flop register and cpu subsystem:
1) BDB Bi-directional Data Bus of FPGA design 8bit is connected on 8bit (D0-D7) data/address bus of cpu subsystem.
2) FPGA design read signal, write signal, reset signal and 3 input signal pins such as interrupt source are connected on the control bus of cpu subsystem.
3) input signal pins such as FPGA design chip selection signal, address wire are connected on the address bus (CS3, AD0-AD3, AD23, AD24) of cpu subsystem.
4) FPGA design high speed address decoder and bus buffer utilize the cooperation of above-mentioned three kinds of buses and address assignment to distinguish each inner function register.The CS3 that wherein is connected to cpu subsystem has determined the absolute address` of entire I/O bridge controller.Each internal function register has been endowed a fixing address according to address decoding, it is the relative address of internal function register, as long as cpu subsystem is according to function register absolute address` and relative address and that be addressed to inside, just as the Memory space of read-write cpu subsystem, read and write this address and just realized operation internal function register.
5) definition of each of the interior function register of I/O bridge has formed the I/O that drives peripheral hardware by its pairing pin, realizes the control from cpu subsystem-I/O bridge controller-peripheral hardware subsystem like this, realizes the state of the loose coupling of printer control.
Function register of the present invention is used for driving and detecting the external equipment of printer respectively, and cpu subsystem connects controller by I/O the equipment of outside is realized seamless control, and relevant register tabulation is as follows:
The I/O of table 1. system control register (SIOR), relative address 0x1000001, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | System led indication control | 1-extinguishes 0-and |
1 |
| Bit?1 | Undefined | For keeping in the future | × |
| Bit?2 | Undefined | For keeping in the future | × |
| Bit?3 | Undefined | For keeping in the future | × |
| Bit?4 | Undefined | For keeping in the future | × |
| Bit?5 | Undefined | For keeping in the future | × |
| Bit?6 | Undefined | For keeping in the future | × |
| Bit?7 | Undefined | For keeping in the future | × |
The I/O bridge controller provides the internal state indicator lamp, and cpu subsystem can be reported to the police to system reliability according to the state of I/O bridge controller.
Table 2. paper knife assembly control register (PKR), relative address 0x1000002, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | The invalid 0-of control external drive 1-is effective | 1 | |
| Bit?1 | Undefined | For keeping in the future | × |
| Bit?2 | Undefined | For keeping in the future | × |
| Bit?3 | Undefined | For keeping in the future | × |
| Bit?4 | Undefined | For keeping in the future | × |
| Bit?5 | Undefined | For keeping in the future | × |
| Bit?6 | Undefined | For keeping in the future | × |
| Bit?7 | Undefined | For keeping in the future | × |
Table 3. cash box assembly prosecution system register (CBR), relative address 0x1000003, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | The control of first via cash box | 1-conducting 0- |
0 |
| Bit?1 | The control of the second road cash box | 1-conducting 0- |
0 |
| Bit?2 | Undefined | For keeping in the future | × |
| Bit?3 | Undefined | For keeping in the future | × |
| Bit?4 | Undefined | For keeping in the future | × |
| Bit?5 | Undefined | For keeping in the future | × |
| Bit?6 | Undefined | For keeping in the future | × |
| Bit?7 | Undefined | For keeping in the future | × |
Table 4. peripheral hardware status register (PSR), relative address 0x1000005, the 8bit register, read-only, relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | By the next Initial printer signal in parallel port | The invalid 0-of 1-is effective, and Host requires Printer to come Initial | Relevant with input |
| Bit?1 | The location status sensor signal of hand papercutter | Definition according to peripheral hardware | Relevant with input |
| Bit?2 | Home Position sensor signal | 1-not at Home position 0-at the Home sensing station | Relevant with input |
| Bit?3 | Paper End sensor signal | 1-has paper 0-to lack paper | Relevant with input |
| Bit?4 | Black Mark sensor signal | 1-does not have black mark signal 0-black mark is arranged | Relevant with input |
| Bit?5 | Printer word car 110 temperature signals | 1-surpasses 110 degrees centigrade of 0-and does not reach 110 degrees centigrade of thresholdings | Relevant with input |
| Bit?6 | Printer word car 130 temperature signals | 1-surpasses 130 degrees centigrade of 0-and does not reach 130 degrees centigrade of thresholdings | Relevant with input |
| Bit?7 | Cash box state sensor signal | Definition according to peripheral hardware | Relevant with input |
Table 5. paper feed stepper motor control register (PFMPR), relative address 0x1000006, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | Motor drives |
The invalid 0-of control external drive 1-is effective | 1 |
| Bit?1 | Motor drives phase transformation control 2 | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?2 | Undefined | For keeping in the future | × |
| Bit?3 | Undefined | For keeping in the future | × |
| Bit?4 | Motor drive |
The invalid 0-of control external drive 1-is effective | 1 |
| Bit?5 | Motor drive current control 2 | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?6 | Motor drive |
The invalid 0-of control external drive 1-is effective | 1 |
| Bit?7 | Motor drive |
The invalid 0-of control external drive 1-is effective | 1 |
Table 6. paper feed stepper motor control register (CRMPR), relative address 0x1000008, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | Motor drives |
The invalid 0-of control external drive 1-is effective | 1 |
| Bit?1 | Motor drives phase transformation control 2 | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?2 | Undefined | For keeping in the future | × |
| Bit?3 | Undefined | For keeping in the future | × |
| Bit?4 | Motor drive |
The invalid 0-of control external drive 1-is effective | 1 |
| Bit?5 | Motor drive current control 2 | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?6 | Motor drive |
The invalid 0-of control external drive 1-is effective | 1 |
| Bit?7 | Motor drive |
The invalid 0-of control external drive 1-is effective | 1 |
Table 7.A row striker control register (HPIN1R), relative address 0x100000a, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | The control of first pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?1 | The control of second pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?2 | The control of the 3rd pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?3 | The control of the 4th pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?4 | The control of the 5th pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?5 | The control of the 6th pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?6 | The control of the 7th pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?7 | The control of the 8th pin | The invalid 0-of control external drive 1-is effective | 1 |
Table 8.A row striker expansion control register (HPIN1ER), relative address 0x100000b, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | Nine kinds of needles control | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?1 | Undefined | For keeping in the future | × |
| Bit?2 | Undefined | For keeping in the future | × |
| Bit?3 | Undefined | For keeping in the future | × |
| Bit?4 | Undefined | For keeping in the future | × |
| Bit?5 | Undefined | For keeping in the future | × |
| Bit?6 | Undefined | For keeping in the future | × |
| Bit?7 | Undefined | For keeping in the future | × |
Table 9.B row striker control register (HPIN2R), relative address 0x100000c, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | The control of first pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?1 | The control of second pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?2 | The control of the 3rd pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?3 | The control of the 4th pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?4 | The control of the 5th pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?5 | The control of the 6th pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?6 | The control of the 7th pin | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?7 | The control of the 8th pin | The invalid 0-of control external drive 1-is effective | 1 |
Table 10.B row striker expansion control register (HPIN2ER), relative address 0x100000d, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | Nine kinds of needles control | The invalid 0-of control external drive 1-is effective | 1 |
| Bit?1 | Undefined | For keeping in the future | × |
| Bit?2 | Undefined | For keeping in the future | × |
| Bit?3 | Undefined | For keeping in the future | × |
| Bit?4 | Undefined | For keeping in the future | × |
| Bit?5 | Undefined | For keeping in the future | × |
| Bit?6 | Undefined | For keeping in the future | × |
| Bit?7 | Undefined | For keeping in the future | × |
Table 11.IEEE1284 device port sign register (IPSSR), relative address 0x100000e 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value |
| Bit?0 | Paper End lacks the paper signal | 1-output high level tells Host paper that 0-is normal to the |
0 |
| Bit?1 | The online signal of printer | The online 0-printer of 1-indication printer is not online | 1 |
| Bit?2 | Printer ERROR signal | 1-exports the normal 0-printer of high printer ERROR and reports to the |
1 |
| Bit?3 | BUSY letter in the SPP pattern | 1-output high level is printed the busy 0-printer |
1 |
| Bit?4 | ACK letter in the SPP pattern | 1-exports high no response 0- |
1 |
| Bit?5 | Undefined | For keeping in the future | × |
| Bit?6 | Undefined | For keeping in the future | × |
| Bit?7 | Undefined | For keeping in the future | × |
Table 12.IEEE1284 device port data write-only registers (IPDRR), relative address 0x1800000, the 8bit register is only write, and relevant bit is defined as:
| The position | Function | Explanation | Initial value | |
| Bit?0 | | Data bit | 0 | High-impedance state |
| Bit?1 | | Data bit | 1 | High-impedance state |
| Bit?2 | Bit2 | Data bit 2 | High-impedance state | |
| Bit?3 | | Data bit | 3 | High-impedance state |
| Bit?4 | | Data bit | 4 | High-impedance state |
| Bit?5 | Bit5 | Data bit 5 | High-impedance state | |
| Bit?6 | Bit6 | Data bit 6 | High-impedance state | |
| Bit?7 | Bit7 | Data bit 7 | High-impedance state |
Table 13.IEEE1284 device port data read-only registers (IPDWR), relative address 0x1800001, the 8bit register, read-only, relevant bit is defined as:
| The position | Function | Explanation | Initial value | |
| Bit?0 | | Data bit | 0 | High-impedance state |
| Bit?1 | | Data bit | 1 | High-impedance state |
| Bit?2 | Bit2 | Data bit 2 | High-impedance state |
| Bit?3 | | Data bit | 3 | High-impedance state |
| Bit?4 | | Data bit | 4 | High-impedance state |
| Bit?5 | Bit5 | Data bit 5 | High-impedance state | |
| Bit?6 | Bit6 | Data bit 6 | High-impedance state | |
| Bit?7 | Bit7 | Data bit 7 | High-impedance state |
Adopt the loose coupling mode between I/O bridge controller and the cpu subsystem, the CPU of any kind no matter, as long as possess the read-write sequence of external RAM/ROM, just can seamlessly be transplanted to the designed I/O bridge controller of the present invention, the portability of system and redundancy are very complete.
Certainly; above-mentioned explanation is not to be limitation of the present invention; the present invention also is not limited in above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present invention also should belong to protection scope of the present invention.
Claims (9)
1. the printer loose-coupling control mode based on FPGA comprises the steps:
A, drive between the port at printer controller and peripheral hardware and to be connected PLD;
B, PLD is carried out hardware configuration, define some function registers;
C, the PLD internal function register is mapped to the Memory space of cpu subsystem;
D, cpu subsystem are addressed to inner function register, have realized the operation to internal function register, thus the control peripheral hardware.
2. control mode according to claim 1 is characterized in that: described C step comprises the steps:
The BDB Bi-directional Data Bus of c1, PLD design 8bit is connected on 8bit (D0-D7) data/address bus of cpu subsystem;
C2, PLD design input signal pin is connected on the control bus, address bus of cpu subsystem;
C3, PLD design high speed address decoder and bus buffer utilize the cooperation of above-mentioned three kinds of buses and address assignment to distinguish each inner function register;
3. control mode according to claim 1 and 2 is characterized in that: described B step comprises the steps:
B1, described PLD internal function register is divided into the I/O of system control register, peripheral hardware status register, paper knife assembly control register, cash box assembly prosecution system register, paper feed stepper motor control register, word vehicle and horse reaches control register, at least two row's striker control register and IEEE1284 device port registers;
B2, be that above-mentioned each function register distributes relative address, and the position in each function register is defined.
4. control mode according to claim 3 is characterized in that: described striker control register comprises A row striker control register, A row striker expansion control register, B row striker control register, B row striker expansion control register.
5. control mode according to claim 3 is characterized in that: described IEEE1284 device port register comprises IEEE1284 device port sign register, IEEE1284 device port data write-only register, IEEE1284 device port data read-only register.
6. control mode according to claim 5, it is characterized in that: first of described IEEE1284 device port sign register is defined as Paper End and lacks paper signal, second and be defined as the online signal of printer, the 3rd and be defined as printer ERROR signal, the 4th is defined as BUSY signal in the SPP pattern, the 5th is defined as ack signal in the SPP pattern, and other three is preserved signal.
7. control mode according to claim 3, it is characterized in that: first of described peripheral hardware status register is used for discerning by the next Initial printer signal in parallel port, second location status sensor signal that is used for discerning hand papercutter, the 3rd is used for discerning the HomePosition sensor signal, the 4th is used for discerning Paper End sensor signal, the 5th is used for discerning Black Mark sensor signal, the 6th is used for discerning printer word car 110 temperature signals, the 7th is used for discerning printer word car 130 temperature signals, and the 8th is used for discerning cash box state sensor signal.
8. control mode according to claim 3, it is characterized in that: first of described system I/O control register is defined as system led indication control signal, and described cpu subsystem is reported to the police to system reliability according to the state of system led indication control signal.
9. control mode according to claim 3, it is characterized in that: described PLD exterior I/O pin comprises the bus control section, the cash box control section, IEEE1284 device port part, paper knife control section, striker control A control section, striker control B control section, part is posted in the control of paper feed motor and the word vehicle and horse reach control section.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1680097A (en) * | 2004-04-07 | 2005-10-12 | 佳能株式会社 | Serial data transmission method, electronic device and recording device |
| EP1754611A1 (en) * | 2005-08-19 | 2007-02-21 | Seiko Epson Corporation | Thermal printer |
| CN101066647A (en) * | 2007-05-28 | 2007-11-07 | 张洪黔 | Portable mark sprayer |
| CN101066645A (en) * | 2007-06-07 | 2007-11-07 | 江南大学 | A control system for textile digital inkjet printing machine |
| CN101189682A (en) * | 2005-05-30 | 2008-05-28 | 精工爱普生株式会社 | semiconductor storage device |
-
2009
- 2009-04-17 CN CN2009100205689A patent/CN101524926B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1680097A (en) * | 2004-04-07 | 2005-10-12 | 佳能株式会社 | Serial data transmission method, electronic device and recording device |
| CN101189682A (en) * | 2005-05-30 | 2008-05-28 | 精工爱普生株式会社 | semiconductor storage device |
| EP1754611A1 (en) * | 2005-08-19 | 2007-02-21 | Seiko Epson Corporation | Thermal printer |
| CN101066647A (en) * | 2007-05-28 | 2007-11-07 | 张洪黔 | Portable mark sprayer |
| CN101066645A (en) * | 2007-06-07 | 2007-11-07 | 江南大学 | A control system for textile digital inkjet printing machine |
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