CN101527281A - Active element array substrate and manufacturing method thereof - Google Patents

Abstract

The invention discloses a manufacturing method of an active element array substrate, which comprises the following steps: a substrate and a multiple transmission photomask are provided. A first metal material layer, a gate insulating material layer, a channel material layer, a second metal material layer and a first photoresist layer are sequentially formed on a substrate. The photoresist layer is patterned by a plurality of transmission photomasks to form a first patterned photoresist layer with two different thicknesses. The first patterned photoresist layer is used as a mask to sequentially perform a first removal process and a second removal process to form a gate, a gate insulating layer, a channel layer and a source/drain. The first patterned photoresist layer is removed. Forming a protective layer and a second patterned photoresist layer on the substrate. A third removal process is performed to form a plurality of contact openings. And forming a pixel electrode material layer on the substrate. And stripping the second patterned photoresist layer to form the pixel electrode.

Description

Active element array substrate and manufacturing method thereof

technical field

The present invention relates to an active element array substrate and a manufacturing method thereof, and in particular to an active element which reduces the number of required photomasks by means of a multi-tone mask Array substrate and its manufacturing method.

Background technique

The multimedia technology in today's society is quite developed, most of which benefit from the progress of semiconductor elements or display devices. As far as displays are concerned, thin film transistor liquid crystal displays with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market.

The thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter substrate and a liquid crystal layer sandwiched between the two substrates. Generally speaking, the manufacturing method of the traditional thin film transistor array substrate needs to go through five photomask processes to complete, wherein the first photomask process is mainly to define the gate and scan line, The process mainly defines the channel layer (channel), the third photomask process mainly defines the source, drain and data line, and the fourth photomask process mainly It is to define the passivation, and the fifth photomask process is mainly to define the pixel electrode.

Since the number of photomask processes will directly affect the manufacturing cost and process time of the entire thin film transistor array substrate, all manufacturers are developing towards reducing the number of photomask process steps. In order to increase the throughput and reduce the manufacturing cost, it is necessary to improve the manufacturing process of the traditional TFT array substrate.

Contents of the invention

The invention provides an active element array substrate and its manufacturing method to solve the problem that the existing manufacturing method cannot effectively reduce the manufacturing cost and manufacturing time.

The invention proposes a method for manufacturing an active device array substrate, which includes the following steps: first, a substrate and a multi-tone mask are provided. Then, a first metal material layer is formed on the substrate. Next, a gate insulating material layer is formed on the first metal material layer. Afterwards, a channel material layer is formed on the gate insulating material layer. Then, a second metal material layer is formed on the channel material layer. Then, a first photoresist layer is formed on the second metal material layer, and the first photoresist layer is patterned by using a multiple transmission photomask to form a first patterned photoresist layer. Wherein, the first patterned photoresist layer has a concave pattern, and part of the second metal material layer is exposed outside the first patterned photoresist layer. Afterwards, a first removal process is performed using the first patterned photoresist layer as a mask to remove the second metal material layer, channel material layer, and gate insulating material layer not covered by the first patterned photoresist layer and the first metal material layer to further form a gate, a gate insulating layer and a channel layer. Then, a second removal process is performed to remove the recessed pattern of the first patterned photoresist layer and the second metal material layer under the corresponding recessed pattern, thereby forming a source/drain and exposing part of the trench road layer. Next, the first patterned photoresist layer is removed. After that, a protection layer is formed on the substrate to cover part of the substrate, source/drain and part of the channel layer. Then, a second patterned photoresist layer is formed on the passivation layer. Wherein, the protection layer corresponding to the top of the source/drain is exposed outside the second patterned photoresist layer. Then, a third removal process is performed using the second patterned photoresist layer as a mask to remove part of the protective layer and form a plurality of contact openings to expose the source/drain. Afterwards, a pixel electrode material layer is formed on the protection layer to cover the second patterned photoresist layer and the exposed source/drain. Then, lift off the second patterned photoresist layer to remove the pixel electrode material layer on the second patterned photoresist layer to form a pixel electrode.

In an embodiment of the present invention, the above-mentioned multi-transmission photomask includes a halftone mask.

In an embodiment of the present invention, the above-mentioned first removal process further includes over-etching the first metal material layer, so as to form an undercut recess at the side edge of the gate.

In an embodiment of the present invention, when forming the gate, a scan line and a common line electrically connected to the gate are also formed.

In an embodiment of the present invention, when forming the above-mentioned source/drain, it also includes forming a storage capacitor electrode above the common wiring.

In an embodiment of the present invention, when forming the above-mentioned gate, it also includes forming a plurality of first sub-data line segments together.

In an embodiment of the present invention, when forming the above-mentioned pixel electrode on the protective layer, it also includes forming a plurality of second sub-data line segments along the extending direction of the first sub-data line segments. One of the second sub-data line segments is electrically connected to the source via the corresponding contact window opening, and the second sub-data line segments are electrically connected to the first sub-data line segments to form a data line.

In an embodiment of the present invention, the above-mentioned second sub-data line segment is electrically connected between the two first sub-data line segments through the contact window openings in the protective layer.

In an embodiment of the present invention, the above-mentioned first removal process includes a wet etching process.

In an embodiment of the present invention, the above-mentioned second removal process includes a dry etching process.

In an embodiment of the present invention, after forming the above-mentioned channel material layer, further comprising forming an ohmic contact material layer on the channel material layer.

In an embodiment of the present invention, the above-mentioned second removal process further includes removing part of the ohmic contact material layer to form an ohmic contact layer.

The invention also proposes a method for manufacturing an active element array substrate, which includes the following steps: firstly, providing a substrate and a multi-transmission photomask. Then, a first metal material layer is formed on the substrate. Next, a gate insulating material layer is formed on the first metal material layer. Afterwards, a channel material layer is formed on the gate insulating material layer. Then, a second metal material layer is formed on the channel material layer. Then, a first photoresist layer is formed on the second metal material layer, and the first photoresist layer is patterned by using a multiple transmission photomask to form a first patterned photoresist layer. Wherein, the first patterned photoresist layer has a concave pattern, and part of the second metal material layer is exposed outside the first patterned photoresist layer. Afterwards, a first removal process is performed using the first patterned photoresist layer as a mask to remove the second metal material layer, channel material layer, and gate insulating material layer not covered by the first patterned photoresist layer and the first metal material layer to further form a gate, a gate insulating layer and a channel layer. Then, a second removal process is performed to remove the recessed pattern of the first patterned photoresist layer and the second metal material layer under the corresponding recessed pattern, thereby forming a source/drain and exposing part of the trench road layer. Next, the first patterned photoresist layer is removed. After that, a protection layer is formed on the substrate to cover part of the substrate, source/drain and part of the channel layer. Then, a second patterned photoresist layer is formed on the passivation layer. Wherein, the protection layer corresponding to the top of the source/drain is exposed outside the second patterned photoresist layer. Then, a third removal process is performed using the second patterned photoresist layer as a mask to remove part of the protective layer and form a plurality of contact openings to expose the source/drain. Afterwards, the second patterned photoresist layer is removed. Then, a pixel electrode is formed on the protection layer, fills in these contact openings, and is electrically connected with the drain.

In an embodiment of the present invention, the above-mentioned multiple transmission photomask includes a half-tone photomask.

In an embodiment of the present invention, when forming the above-mentioned gate, a scanning line and a common wiring electrically connected to the gate are also formed.

In an embodiment of the present invention, when forming the above-mentioned source/drain, it also includes forming a storage capacitor electrode above the common wiring.

In an embodiment of the present invention, when forming the above-mentioned source/drain, it also includes forming a plurality of first sub-data line segments together.

In an embodiment of the present invention, when forming the above-mentioned pixel electrode on the protective layer, it also includes forming a plurality of second sub-data line segments along the extending direction of the first sub-data line segments. One of the second sub-data line segments is electrically connected to the source via the corresponding contact window opening, and the second sub-data line segments are electrically connected to the first sub-data line segments to form a data line.

In an embodiment of the present invention, the above-mentioned second sub-data line segment is electrically connected between the two first sub-data line segments through the contact window openings in the protective layer.

In an embodiment of the present invention, the above-mentioned first removal process includes a wet etching process.

In an embodiment of the present invention, the above-mentioned second removal process includes a dry etching process.

In an embodiment of the present invention, after forming the above-mentioned channel material layer, further comprising forming an ohmic contact material layer on the channel material layer.

In an embodiment of the present invention, the above-mentioned second removal process further includes removing part of the ohmic contact material layer to form an ohmic contact layer.

In an embodiment of the present invention, the step of forming the pixel electrode includes: firstly, forming a pixel electrode material layer on the protective layer to cover the protective layer and the exposed source/drain. Then, a third patterned photoresist layer is formed on the passivation layer. Next, the pixel electrode material layer is patterned by using the third patterned photoresist layer as a mask to form a pixel electrode.

The present invention also proposes an active element array substrate, including a substrate, a scanning line, an active element, a protection layer, a pixel electrode, multiple first sub-data line segments and multiple second sub-data line segments. Both the scanning line and the active element are arranged on the substrate, wherein the active element includes a gate, a gate insulating layer, a channel layer and a source/drain. The gate is arranged on the substrate and is electrically connected with the scanning line, and the side edge of the gate has an undercut recess. The gate insulating layer is arranged on the gate, the channel layer is arranged on the gate insulating layer, and the source/drain are respectively arranged on both sides of the channel layer. The protection layer covers the active elements and the scan lines, and has a plurality of contact window openings. Some of these contact openings expose the source/drain. The pixel electrode is disposed on the protective layer and is electrically connected to the drain through part of the openings of the contact windows. These first sub-data line segments are located in the same film layer as the source/drain electrodes, and the second sub-data line segments are located in the same film layer as the pixel electrodes. The second sub-data line segments are electrically connected between the two first sub-data line segments through part of the contact window openings to form a data line, and one of the second sub-data line segments is electrically connected through the corresponding contact window opening. connected to source.

In an embodiment of the present invention, the above-mentioned active device array substrate further includes a common wiring disposed on the substrate, and the common wiring and the gate are located in the same film layer.

In an embodiment of the present invention, the above-mentioned active device array substrate further includes a storage capacitor electrode disposed above the common wiring, and the protective layer is located between the storage capacitor electrode and the pixel electrode. The pixel electrode is electrically connected to the storage capacitor electrode through one of the corresponding contact window openings.

The manufacturing method of the active element array substrate of the present invention adopts a multi-transmission photomask to pattern the photoresist layer, which enables the patterned photoresist layer to have two different thicknesses. Using the patterned photoresist layer as a mask for patterning each film layer can make the manufacturing method of the active element array substrate of the present invention need at least two photomask processes to complete. Therefore, both the manufacturing cost and the process time can be effectively reduced, and thus the production capacity can be greatly increased.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

1A to 1H are schematic cross-sectional flowcharts of a method for manufacturing an active device array substrate according to a first embodiment of the present invention.

2A to 2B are partial top views of the manufacturing process of the active device array substrate according to the first embodiment of the present invention.

3A to 3H are schematic cross-sectional flowcharts of a method for manufacturing an active device array substrate according to a second embodiment of the present invention.

4A to 4C are partial top views of the manufacturing process of the active device array substrate according to the second embodiment of the present invention.

Description of main component symbols:

100a, 100b: active element array substrate

110: Substrate

112: Predetermined area for data lines

120: first metal material layer

122: grid

124: Side erosion depression

130: gate insulating material layer

132: Gate insulating layer

140: channel material layer

142: channel layer

150: Ohmic contact material layer

152: Ohmic contact layer

160: second metal material layer

162: The first sub-data segment

164a: source

164b: drain

166: storage capacitor electrode

170: protective layer

172: Contact window opening

180: pixel electrode material layer

182: pixel electrode

184: The second sub-data segment

210: the first photoresist layer

212: the first patterned photoresist layer

214: Debossed pattern

220a, 220b: second patterned photoresist layer

222: opening

230: the third patterned photoresist layer

CL: common wiring

DL: data line

M1: Multiple pass-through photomask

SL: scan line

T1, T2, T3: Translucent area

Detailed ways

first embodiment

1A to FIG. 1H are schematic cross-sectional flow diagrams of the manufacturing method of the active element array substrate according to the first embodiment of the present invention, and FIGS. 2A to 2B are part of the manufacturing process of the active element array substrate according to the first embodiment of the present invention. top view. Please refer to FIG. 1A first. First, a substrate 110 is provided. Then, a first metal material layer 120 , a gate insulating material layer 130 , a channel material layer 140 , a second metal material layer 160 and a first photoresist layer 210 are sequentially formed on the substrate 110 .

In detail, the first metal material layer 120 is deposited on the substrate 210 by physical vapor deposition (Physical Vapor Deposition, PVD), and its material is, for example, aluminum, gold, copper, molybdenum, chromium, titanium, aluminum alloy Or low-resistance materials such as molybdenum alloys. The gate insulating material layer 130 is, for example, deposited on the first metal material layer 120 by chemical vapor deposition (chemical vapor deposition, CVD), and its material is, for example, silicon nitride (SiN) or tetraethoxysilane ( Tetra-ethyl-ortho-silicate, TEOS) is a silicon oxide (SiO) formed as a reactive gas source.

In addition, the channel material layer 140 is, for example, deposited amorphous silicon (a-Si) on the gate insulating material layer 130 by chemical vapor deposition, and the second metal material layer 160 is, for example, deposited a metal material by physical vapor deposition. On the channel material layer 140 , the second metal material layer 160 may be the same or similar conductive material as that of the first metal material layer 120 . In addition, the first photoresist layer 210 in this embodiment is, for example, a positive photoresist.

It should be noted that, in order to reduce the contact resistance between the channel material layer 140 and the second metal material layer 160, an ohm resistance can also be selected to be formed between the channel material layer 140 and the second metal material layer 160 in practice. The material of the contact material layer 150 is, for example, N-type doped amorphous silicon. The ohmic contact material layer 150 is, for example, subjected to an ion doping step after the channel material layer 140 is formed. Wherein, the material of the ohmic contact material layer 150 is, for example, N-type doped amorphous silicon.

Next, a multi-tone mask M1 is provided, such as a half tone mask. Wherein, the multiple transmission photomask M1 has a first light transmission area T1 , a second light transmission area T2 and a third light transmission area T3 . In detail, the transmittance of the first transmittance region T1 is greater than the transmittance of the second transmittance region T2, and the transmittance of the second transmittance region T2 is greater than the transmittance of the third transmittance region T3 Rate. In this embodiment, the third light-transmitting region T3 may be an opaque region.

Referring to FIG. 1B , the first photoresist layer 210 is patterned by the multiple pass-through photomask M1 to form a first patterned photoresist layer 212 . It should be noted that since the multiple transmission photomask M1 has three different light transmittances, the first patterned photoresist layer 212 formed after the patterning of the first photoresist layer 210 will also have two different transmittances. different residual thicknesses. Since the light transmittance of the first light transmission region T1 is the strongest. Therefore, the first photoresist layer 210 corresponding to the first light-transmitting region T1 will be removed after being patterned, and the second metal material layer 160 corresponding to the first light-transmitting region T1 will be exposed to the first patterned light. outside the resistance layer 212.

In addition, since the third light-transmitting region T3 is an opaque region in this embodiment. Therefore, the first photoresist layer 210 corresponding to the third light-transmitting region T3 will not be removed. In addition, since the light transmittance of the second light transmission region T2 is between the light transmittance of the first light transmission region T1 and the light transmittance of the third light transmission region T3 . Therefore, the thickness of the first photoresist layer 210 corresponding to the second light transmission region T2 is smaller than the thickness of the first photoresist layer 210 corresponding to the third light transmission region T3 to form a concave pattern 214 .

1C, a first removal process is performed using the first patterned photoresist layer 212 as a mask to remove the second metal material layer 160 and ohmic contacts not covered by the first patterned photoresist layer 212. The material layer 150 , the channel material layer 140 , the gate insulating material layer 130 and the first metal material layer 120 further form a gate 122 , a gate insulating layer 132 and a channel layer 142 . Generally speaking, the first removal process is, for example, an anisotropic wet etching process.

In this embodiment, the first removal process may further include over-etching the first metal material layer 120 to form an undercut recess 124 at the side edge of the gate 122 as shown in FIG. 1C . Similarly, the side edge of the first metal material layer 120 located below the first sub-data line segment 162 can also form the undercut recess 124 as shown in FIG. 1C . Wherein, the function of the undercut recess 124 will be described in detail later.

Referring to FIG. 1D, a second removal process is performed to remove the recessed pattern 214 of the first patterned photoresist layer 212 shown in FIG. 1C and the corresponding ohmic contact material layer below the recessed pattern 214 shown in FIG. 1C. 150 and the second metal material layer 160 , further forming a source 164 a and a drain 164 b, and exposing part of the channel layer 142 . Wherein, the second removal process is, for example, an isotropic dry etching process. Next, the first patterned photoresist layer 212 is removed.

In addition, please refer to FIG. 2A , in the first removal process, a scan line SL and a common wiring CL (both are formed by the first metal material layer 120 ) can also be formed together, and on the substrate 110 A plurality of first sub-data line segments 162 (formed by the second metal material layer 160 ) are formed in a data line predetermined area 112 . Wherein, the scan line SL is electrically connected to the gate 122 , and the common wiring CL is, for example, parallel to the scan line SL. In addition, the extending direction of the first sub-data line segments 162 intersects, for example, the extending directions of the scan lines SL and the common wiring CL. It should be noted that the first metal material layer 120 below the first sub-data line segments 162 is not electrically connected to the scan lines SL and the common wiring CL.

In addition, a storage capacitor electrode 166 may also be formed above the common wiring CL in the first removal process. Wherein, the gate 122, the scan line SL and the common wiring CL are formed by, for example, the first metal material layer 120, and the first sub-data line segment 162, the source electrode 164a, the drain electrode 164b, and the storage capacitor electrode 166 are, for example, formed by the first metal material layer. Two metal material layers 160 are formed.

Then referring to FIG. 1E , a protective layer 170 and a second patterned photoresist layer 220 a are sequentially formed on the substrate 110 . The passivation layer 132 is formed on the substrate 110 by, for example, chemical vapor deposition, and its material is, for example, silicon oxide, silicon nitride or silicon oxynitride. In addition, the second patterned photoresist layer 220a is formed by patterning with a photomask. Specifically, the protection layer 170 covers part of the substrate 110, part of the channel layer 142, the first sub-data line segment 162, the source electrode 164a, the drain electrode 164b and the storage capacitor electrode 166, while the second patterned photoresist layer 220a has A plurality of openings 222 . Wherein, the openings 222 expose portions corresponding to the protection layer 170 above the first sub-data line segments 162 , the source electrode 164 a , the drain electrode 164 b and the storage capacitor electrode 166 .

1F, a third removal process is performed using the second patterned photoresist layer 220a as a mask to remove part of the protective layer 170 and form a plurality of contact openings 172 to expose the first sub-layers. The data line segment 162 , the source electrode 164 a , the drain electrode 164 b and the storage capacitor electrode 166 .

1G, a pixel electrode material layer 180 is formed on the protective layer 170 and the second patterned photoresist layer 220a to cover the second patterned photoresist layer 180 and the exposed first sub-data line segment 162, source pole 164a, drain 164b and storage capacitor electrode 166. Wherein, the pixel electrode material layer 180 is formed on the substrate 110 by, for example, chemical vapor deposition, and its material is, for example, indium tin oxide (indium tin oxide, ITO), indium zinc oxide (indium zinc oxide, IZO) or aluminum Zinc oxide (aluminum zinc oxide, AZO).

It should be noted that, since the second patterned photoresist layer 220a has a considerable thickness, and the sidewalls of the openings 222 tend to be vertical. Therefore, the pixel electrode material layer 180 is not easily formed on the sidewall of the opening 222 . In particular, because the side edge of the gate 122 and the side edge of the first metal material layer 120 located below the first sub-data line segment 162 have side etching recesses 124 . Therefore, the pixel electrode material layer 180 formed on the substrate 110 is not electrically connected to the gate 122 and the first metal material layer 120 located below the first sub-data line segment 162 .

1H, a lift off process is performed to lift off the second patterned photoresist layer 220a, and remove the pixel electrode material layer 180 on the second patterned photoresist layer 220a to form a pixel. Electrode 182. In addition, the pixel electrode 182 can be electrically connected to the storage capacitor electrode 166 through the contact window opening 172, and a part of the common line CL and the storage capacitor electrode 166 can form a storage capacitor.

Referring to FIG. 2B later, when the pixel electrode 182 is formed, a plurality of second sub-data line segments 184 can also be formed along the extension direction of the first sub-data line segment 162 (in the data line predetermined area 112 ). Wherein, the pixel electrode 182 and the second sub-data line segment 184 are both formed by the pixel electrode material layer 180 . Specifically, the second sub-data line segment 184 is electrically connected between two first sub-data line segments 162 to form a data line DL.

So far, the active device array substrate manufacturing method of the present invention can complete the active device array substrate 100a of the present invention only through two photomask processes and an appropriate removal process. Therefore, the manufacturing method of the active element array substrate of the present invention can greatly reduce the manufacturing cost.

second embodiment

3A to 3H are schematic cross-sectional flow diagrams of the manufacturing method of the active element array substrate according to the second embodiment of the present invention, and FIGS. 4A to 4C are part of the manufacturing process of the active element array substrate according to the second embodiment of the present invention top view. The second embodiment is substantially the same as the first embodiment, and the main difference between the two is that the second embodiment uses a third patterned photoresist layer 230 as a patterned mask to form a pixel electrode 182 and A plurality of second sub-data line segments 184 .

Please refer to FIG. 3A to FIG. 3D and FIG. 4A. First, a first metal material layer 120, a gate insulating material layer 130, a channel material layer 140, and a second metal material layer 160 are sequentially formed on the substrate 110. and a first photoresist layer 210 . Then, the first photoresist layer 210 is patterned by a multiple pass-through photomask M1 to form a first patterned photoresist layer 212 . Next, a first removal process and a second removal process are sequentially performed using the first patterned photoresist layer 212 as a mask to form a gate 122, a gate insulating layer 132, and a trench on the substrate 110. The track layer 142 , a scan line SL, a common line CL, a plurality of first sub-data line segments 162 , a source 164 a , a drain 164 b , a storage capacitor electrode 166 and an ohmic contact layer 152 . The steps and materials for forming the above film layers are similar to those shown in FIGS. 1A to 1D and FIG. 2A in the first embodiment, and will not be repeated here.

Then referring to FIG. 3E , a protection layer 170 and a second patterned photoresist layer 220 b are sequentially formed on the substrate 110 . Wherein, the steps and materials for forming the protection layer 170 are similar to those of the first embodiment, and will not be repeated here. Next, a third removal process is performed using the second patterned photoresist layer 220b as a mask to remove part of the protection layer 170 . Next, please refer to FIG. 3F and FIG. 4B , the protective layer 170 will form a plurality of contact openings 172 to expose part of the first sub-data line segment 162, part of the source 164a, part of the drain 164b and part part of the storage capacitor electrode 166. Then, the second patterned photoresist layer 220b is removed.

It should be noted that, compared with the first embodiment, the opening 222 of the second patterned photoresist layer 220b in the second embodiment only exposes a lesser portion of the protection layer 170 . Therefore, after the third removal process, the contact window opening 172 of the protection layer 170 only exposes a small portion of the second metal material layer 160 . Moreover, since the protective layer 170 can completely cover the substrate 110 exposed after the first removal process. Therefore, in the first removal process, there is no need to over-etch the first metal material layer 120 to form the undercut recess 124 .

Next, referring to FIG. 3G , a pixel electrode material layer 180 and a third patterned photoresist layer 230 are sequentially formed on the substrate 110 . Wherein, the steps and materials for forming the pixel electrode material layer 180 are similar to those of the first embodiment, and will not be repeated here. Then, referring to FIG. 3H , the pixel electrode material layer 180 is patterned by using the third patterned photoresist layer 230 as a mask to form a pixel electrode 182 . At this time, a storage capacitor is formed between the common line CL and the pixel electrode 182 . Next, the third patterned photoresist layer 230 is removed.

In addition, referring to FIG. 4C , when patterning the pixel electrode material layer 180 , a plurality of second sub-data line segments 162 can also be formed in the predetermined data line area 112 on the substrate 110 along the extending direction of the first sub-data line segments 162 . Sub-data line segment 184 . Wherein, the pixel electrode 182 and the second sub-data line segments 184 are, for example, formed by the pixel electrode material layer 180, and the pixel electrode 182 is electrically connected to the drain electrode 164b, and one of the second sub-data line segments 184 is electrically connected to source 164a. Furthermore, the second sub-data line segments 184 are electrically connected between two first sub-data line segments 162 to form a data line DL. From the above so far, the manufacturing method of the active device array substrate of the present invention can complete the manufacturing of the active device array substrate 100b of the present invention only through three photomask processes and appropriate removal processes. Therefore, the manufacturing method of the active element array substrate of the present invention can effectively reduce the manufacturing cost.

To sum up, since the method for manufacturing the active element array substrate of the present invention uses a multi-transmission photomask to pattern the first photoresist layer, the first patterned photoresist layer can have two types of different thicknesses. Therefore, the gate, the gate insulating layer, the channel layer and the source/drain can be fabricated through a photomask process as long as an appropriate removal process is matched. Therefore, the manufacturing method of the active element array substrate of the present invention only needs two or three photomask processes to complete. This can not only effectively reduce the process time, but also effectively reduce the manufacturing cost, thereby achieving the purpose of increasing production capacity.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (27)

1. A method for manufacturing an active element array substrate, comprising: providing a substrate and a multiple pass-through photomask; forming a first metal material layer on the substrate; forming a gate insulating material layer on the first metal material layer; forming a channel material layer on the gate insulating material layer; forming a second metal material layer on the channel material layer; forming a first photoresist layer on the second metal material layer, and patterning the first photoresist layer by means of the multiple transmission photomask to form a first patterned photoresist layer, wherein The first patterned photoresist layer has a concave pattern, and part of the second metal material layer is exposed outside the first patterned photoresist layer; Using the first patterned photoresist layer as a mask to perform a first removal process to remove the second metal material layer, the channel material layer, and the gate not covered by the first patterned photoresist layer The insulating material layer and the first metal material layer further form a gate, a gate insulating layer and a channel layer; performing a second removal process to remove the recessed pattern of the first patterned photoresist layer and the second metal material layer corresponding to the recessed pattern, thereby forming a source/drain and exposing part of the the channel layer; removing the first patterned photoresist layer; forming a protective layer on the substrate to cover part of the substrate, the source/drain and part of the channel layer; forming a second patterned photoresist layer on the protection layer, wherein the protection layer corresponding to the source/drain is exposed outside the second patterned photoresist layer; performing a third removal process using the second patterned photoresist layer as a mask to remove part of the protective layer and form a plurality of contact openings to expose the source/drain; forming a pixel electrode material layer on the protective layer to cover the second patterned photoresist layer and the exposed source/drain; and peeling off the second patterned photoresist layer to remove the pixel electrode material layer on the second patterned photoresist layer to form a pixel electrode. 2 . The method for manufacturing an active device array substrate as claimed in claim 1 , wherein the multiple transmission photomask comprises a half-tone photomask. 3 . 3. The method for manufacturing an active device array substrate according to claim 1, wherein the first removal process further comprises over-etching the first metal material layer to form a side edge of the gate. Side erosion depression. 4. The method for manufacturing an active element array substrate according to claim 1, further comprising forming a scanning line electrically connected to the gate and a common wiring when forming the gate . 5 . The method for manufacturing an active device array substrate as claimed in claim 4 , further comprising forming a storage capacitor electrode above the common wiring when forming the source/drain. 5 . 6 . The method for manufacturing an active device array substrate according to claim 1 , further comprising forming a plurality of first sub-data line segments when forming the gate. 6 . 7. The method for manufacturing an active element array substrate as claimed in claim 6, wherein when forming the pixel electrode on the protection layer, it further comprises forming along the extending direction of the first sub-data line segments A plurality of second sub-data line segments, one of the second sub-data line segments is electrically connected to the source through the corresponding contact window opening, and the second sub-data line segments are electrically connected to the first sub-data line segments connected to form a data line. 8. The method of manufacturing an active element array substrate as claimed in claim 7, wherein the second sub-data line segments are electrically connected to the two first sub-data lines through the openings of the contact windows in the protective layer. between line segments. 9. The method of manufacturing an active device array substrate as claimed in claim 1, wherein the first removal process comprises a wet etching process. 10. The method of manufacturing an active device array substrate as claimed in claim 1, wherein the second removal process comprises a dry etching process. 11. The method for manufacturing an active device array substrate as claimed in claim 1, further comprising forming an ohmic contact material layer on the channel material layer after forming the channel material layer. 12 . The method for manufacturing an active device array substrate as claimed in claim 11 , wherein the second removal process further comprises removing part of the ohmic contact material layer to form an ohmic contact layer. 13 . 13. A method for manufacturing an active element array substrate, comprising: providing a substrate and a multiple pass-through photomask; forming a first metal material layer on the substrate; forming a gate insulating material layer on the first metal material layer; forming a channel material layer on the gate insulating material layer; forming a second metal material layer on the channel material layer; forming a first photoresist layer on the second metal material layer, and patterning the first photoresist layer by means of the multiple transmission photomask to form a first patterned photoresist layer, wherein The first patterned photoresist layer has a concave pattern, and part of the second metal material layer is exposed outside the first patterned photoresist layer; Using the first patterned photoresist layer as a mask to perform a first removal process to remove the second metal material layer, the channel material layer, and the gate not covered by the first patterned photoresist layer The insulating material layer and the first metal material layer further form a gate, a gate insulating layer and a channel layer; performing a second removal process to remove the recessed pattern of the first patterned photoresist layer and the second metal material layer corresponding to the recessed pattern, thereby forming a source/drain and exposing part of the the channel layer; removing the first patterned photoresist layer; forming a protective layer on the substrate to cover part of the substrate, the source/drain and part of the channel layer; forming a second patterned photoresist layer on the protection layer, wherein the protection layer corresponding to the source/drain is exposed outside the second patterned photoresist layer; performing a third removal process using the second patterned photoresist layer as a mask to remove part of the protective layer and form a plurality of contact openings to expose the source/drain; removing the second patterned photoresist layer; and A pixel electrode is formed on the protective layer, filled in the contact openings, and electrically connected with the drain. 14 . The method for manufacturing an active device array substrate as claimed in claim 13 , wherein the multiple transmission photomask comprises a half-tone photomask. 15. The method for manufacturing an active element array substrate as claimed in claim 13, further comprising forming a scan line electrically connected to the gate and a common wiring when forming the gate . 16 . The method for manufacturing an active device array substrate as claimed in claim 15 , further comprising forming a storage capacitor electrode above the common wiring when forming the source/drain. 17 . 17. The method for manufacturing an active device array substrate according to claim 13, further comprising forming a plurality of first sub-data line segments when forming the gate. 18. The method for manufacturing an active element array substrate according to claim 17, wherein when forming the pixel electrode on the protective layer, it further comprises forming a pixel electrode along the extending direction of the first sub-data line segments. A plurality of second sub-data line segments, one of the second sub-data line segments is electrically connected to the source through the corresponding contact window opening, and the second sub-data line segments are electrically connected to the first sub-data line segments connected to form a data line. 19. The method of manufacturing an active element array substrate according to claim 18, wherein the second sub-data line segments are electrically connected to the two first sub-data lines through the contact window openings of the protective layer. between line segments. 20. The method of manufacturing an active device array substrate as claimed in claim 13, wherein the first removal process comprises a wet etching process. 21. The method of manufacturing an active device array substrate as claimed in claim 13, wherein the second removal process comprises a dry etching process. 22. The method for manufacturing an active device array substrate as claimed in claim 13, further comprising forming an ohmic contact material layer on the channel material layer after forming the channel material layer. 23. The method for manufacturing an active device array substrate as claimed in claim 22, wherein the first removal process further comprises removing a portion of the ohmic contact material layer to form an ohmic contact layer. 24. The method for manufacturing an active element array substrate as claimed in claim 13, wherein the step of forming the pixel electrode comprises: forming a pixel electrode material layer on the protection layer to cover the protection layer and the exposed source/drain; forming a third patterned photoresist layer on the passivation layer; and The pixel electrode material layer is patterned by using the third patterned photoresist layer as a mask to form the pixel electrode. 25. An active element array substrate, comprising: a substrate; a scanning line configured on the substrate; An active element is configured on the substrate, and the active element includes: a grid, configured on the substrate, and electrically connected to the scanning line, and the side edge of the grid With a side erosion depression; a gate insulating layer configured on the gate; a channel layer configured on the gate insulating layer; a source/drain, respectively arranged on both sides of the channel layer; a protective layer covering the active element and the scanning line, and the protective layer has a plurality of contact window openings, part of the contact window openings expose the source/drain; a pixel electrode, disposed on the protective layer, and electrically connected to the drain through part of the contact window openings; a plurality of first sub-data line segments; and A plurality of second sub-data line segments, the first sub-data line segments are located in the same film layer as the source/drain electrodes, and the second sub-data line segments are located in the same film layer as the pixel electrode, wherein the second sub-data line segments and electrically connected between two first sub-data line segments through part of the contact window openings to form a data line, and one of the second sub-data line segments is electrically connected to the corresponding contact window openings. the source. 26 . The active device array substrate as claimed in claim 25 , further comprising a common wiring disposed on the substrate, and the common wiring is located in the same film layer as the gate. 27. The active device array substrate according to claim 25, further comprising a storage capacitor electrode disposed above the common wiring, and the protection layer is located between the storage capacitor electrode and the pixel electrode, The pixel electrode is electrically connected to the storage capacitor electrode through one of the corresponding contact window openings.

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