CN101521189B - Multilayer printed wiring board - Google Patents

Abstract

The present invention provides a multilayer printed circuit board and a package substrate in which malfunction or error does not occur in IC chips in a high-frequency region, especially over 3 GHz. The conductive layer ( 34P) on the core substrate ( 30 ) is formed to have a thickness of 30 μm, and the conductive circuit ( 58 ) on the interlaminar resin insulating layer ( 50 ) is formed to have a thickness of 15 μm. The resistance can be reduced by increasing the volume of the conductor itself by making the conductor layer (34P) thicker. Furthermore, by using the conductor layer (34) as a power supply layer, it is possible to improve the ability to supply power to the IC chip.

Description

multilayer printed circuit board

This application is a divisional application with the filing date of February 3, 2005, the national application number of 200580000229.4, and the title of the invention being multilayer printed circuit board.

technical field

The present invention relates to a multi-layer printed circuit board; it is proposed that even if a high-frequency IC chip is installed, especially an IC chip in a high-frequency region of 3 GHz or above 3 GHz does not cause malfunction or error, etc. and can improve Multilayer printed circuit boards for electrical characteristics or reliability.

Background technique

In a build-up multilayer printed circuit board that constitutes a package for an IC chip, an interlayer insulating resin is formed on both sides or one side of a core substrate that forms a through hole, and the layers are separated by laser or photoetching. The hole for interlayer conduction for interlayer conduction is used to open and form an interlayer resin insulating layer. On the inner wall of the hole for interlayer conduction and the interlayer resin insulating layer, a conductor layer is formed by plating or the like, and patterned by etching or the like to produce a conductor circuit. In addition, a build-up multilayer printed circuit board is obtained by repeatedly forming interlayer insulating layers and conductor layers. According to needs, by forming tin-lead bumps and external terminals (PGA/BGA, etc.) on the surface layer, it becomes a substrate or package substrate on which IC chips can be mounted. The IC chip is electrically connected between the IC chip and the substrate by performing C4 (flip chip) mounting.

As the prior art of a build-up type multilayer printed circuit board, there are JP-A-6-260756, JP-A-6-275959, and the like. They all form a land on a core substrate filled with a filling resin, form an interlayer insulating layer with an interlayer conduction hole on both sides, and implement a conductive layer by an additive method. A multilayer printed circuit board with high density and fine wiring can be obtained by connecting the pads.

However, as the frequency of IC chips increases, the frequency of malfunctions and errors increases. Especially when the frequency exceeds 3 GHz, the degree increases. When it exceeds 5GHz, sometimes it will not work at all. Therefore, in a computer including the IC chip as a CPU, required functions or operations such as image recognition, switch switching, and external data transmission cannot be performed.

When performing non-destructive inspection or disassembly of these IC chips and substrates, there will be no problems such as short circuit or open circuit in the IC chips and substrates themselves. When installing IC chips with low frequency (especially less than 1GHz), there will be no malfunction or failure. mistake.

In order to solve the above-mentioned problems, the present inventors proposed to make the thickness of the conductor layer on the core substrate larger than the thickness of the conductor layer on the interlayer insulating layer as described in Japanese Patent Application No. 2002-233775. However, in the above invention, when producing a core substrate having fine wiring patterns, the insulation interval between the wiring patterns is narrowed, resulting in a printed wiring board having poor insulation reliability.

Contents of the invention

The present invention was made in order to solve the above-mentioned problems, and its object is to provide a multilayer printed circuit board that can constitute an IC chip in a high-frequency region, especially a printed circuit board or a package substrate that does not cause malfunction or error even if it exceeds 3 GHz. .

Furthermore, it is an object to provide a multilayer printed circuit board having high insulation reliability and connection reliability.

The inventors of the present invention have earnestly studied to achieve the above-mentioned object, and as a result, came up with the invention constituted as the gist of the following. Right now,

A multilayer printed circuit board according to the first technical aspect of the present invention is formed on a core substrate with an interlayer insulating layer and a conductor layer, and is electrically connected through a hole for interlayer conduction, and is characterized in that the conductor layer of the core substrate Thickness is greater than the thickness of the conductor layer on the interlayer insulating layer, the side surface of the conductor layer on the described core substrate becomes taper shape, suppose the included angle between the straight line connecting the upper end and the lower end of the side surface of the conductor layer and the horizontal plane of the core substrate to be Θ, said Θ satisfies the relational expression of 2.8<tanΘ<55.

The second technical solution of the present invention is a multilayer printed circuit board in which an interlayer insulating layer and a conductor layer are formed on a core substrate, and are electrically connected through holes for interlayer conduction, wherein the core substrate is formed on A multilayer core substrate having three or more layers of conductor layers on the front and back and a thick conductor layer on the inner layer, at least one of the conductor layers on the inner layer and the conductor layers on the front and back of the core substrate is a power supply Layer conductor layer or ground conductor layer.

In addition, when the angle Θ formed between the straight line connecting the upper end and the lower end of the side surface of the conductor layer of the inner layer and the horizontal plane of the core substrate is Θ, the Θ may satisfy the relational expression of 2.8<tanΘ<55.

As a first effect, the strength of the core substrate can be increased by making the conductor layer of the power supply layer of the core substrate thicker, so that even if the core substrate itself is thinned, the substrate itself can relax bending or generated stress.

As a second effect, the volume of the conductor itself can be increased by making the conductor layer thick. The resistance in a conductor can be lowered by increasing its volume. Therefore, electrical transmission or the like of a flowing signal line or the like is not hindered. Therefore, no loss occurs in transmitted signals or the like. This is achieved by only thickening the substrate to be the core portion. The thick conductor layer is preferably disposed on the inner layer of the core substrate. The interlayer insulating layer formed on the core substrate or the conductor layer on the interlayer insulating layer becomes flat. In addition, the mutual inductance is reduced.

As a third effect, the ability to supply power to the IC chip can be improved by using the conductor layer as the power supply layer. In addition, noise superimposed on signals and power supplied to the IC chip can be reduced by using the conductor layer as the ground layer. This is based on the fact that the reduction in conductor resistance described in the second effect does not hinder the supply of power. Therefore, when the IC chip is mounted on the multilayer printed circuit board, the loop inductance from the IC chip to the substrate to the power supply can be reduced. Therefore, the power shortage of the initial operation is reduced, so it is less likely to cause a power shortage, so even if an IC chip in the high-frequency region is mounted, there will be no malfunction or error in the initial startup.

As a fourth effect, since the side surface of the conductor layer of the core substrate is tapered, the angle formed between the straight line connecting the upper end and the lower end of the side surface of the conductor layer and the horizontal plane of the core substrate (hereinafter sometimes simply referred to as the conductor layer When the angle of the side surface of ) is Θ, the Θ satisfies the relational expression of 2.8<tanΘ<55, therefore, miniaturization, prevention of power shortage, and high-speed signal transmission can be realized at the same time. Since tanΘ>2.8, even if the upper ends of the conductive layers are arranged close to each other, the space between the lower ends of the conductive layers can be ensured. Thereby, it becomes a printed circuit board with high density and high insulation reliability. In addition, since the through-holes with opposite potentials and the inner layer conductor of the core substrate can be arranged close to each other, the inductance is reduced. Thereby, it becomes a multilayer printed wiring board which can prevent power shortage easily. As a method of bringing the two closer together, there may be a through hole without a dummy land to be described later. On the other hand, since tanΘ<55, the side walls of the conductor layer are not at right angles. Therefore, in order to perform impedance matching, it is not necessary to reduce or reduce the conductor thickness or diameter of the signal via hole (via hole electrically connected to the IC signal circuit). As a result, the conductor resistance of the signal via hole can be reduced, which is advantageous for high-speed signal transmission. In addition, when the side surface of the conductor layer is tapered, it is also possible to prevent power shortage and signal degradation at the same time. Because of the tapered shape, the attenuation of the signal can be reduced at the signal via hole that penetrates the multilayer core, so it is less likely to cause signal degradation. Furthermore, since the angle of the side surface of the conductor layer is equal to or larger than the predetermined angle, the conductor resistance can be reduced, thereby suppressing power shortage. In addition, in the case of a multilayer core, when the angle between the front and back conductor layer sides is Θ1 and the angle between the inner layer conductor layer sides is Θ2, it is preferable that Θ1>Θ2. The reason for forming a build-up layer composed of an interlayer insulating layer and a conductor layer on the core substrate is that impedance matching can be easily performed on signal lines in the build-up layer. When a signal line having a buildup layer is formed on a tapered shape with small Θ1, it is because there are many regions where the thickness of the interlayer insulating layer under the signal line is different. Also, since the via pitch cannot be narrowed, the inductance cannot be reduced.

As a result of earnest research by the present inventors to achieve the above-mentioned objects, they came up with the invention which consists of the following summary. That is, in the multilayer printed circuit board of the present invention, an interlayer insulating layer and a conductor layer are formed on a core substrate, and are electrically connected through holes for interlayer conduction. At least one sum of the thicknesses of the conductor layer is greater than the thickness of the conductor layer on the interlayer insulating layer.

That is, when the core substrate is used as a multilayer core substrate, the thickness of the conductor layers on the front and back surfaces of the core substrate is not increased, but the sum of the thicknesses of the respective conductor layers is increased. In the case of a multilayer core substrate, the thickness of the conductor layers on the front and back surfaces of the core substrate and the thickness of the conductor layer on the inner layer are added to contribute to the power supply or stabilization of the IC. In this case, the conductor layers on the front and back layers are electrically connected to the conductor layers on the inner layer, and are suitable for the electrical connection through two or more locations. That is, by multilayering, the sum of the thicknesses of the conductor layers of the multilayer core substrate can be increased, and the conductor layer of the core can be used as the conductor layer for the power supply, thereby improving the ability to supply power to the IC chip. In addition, by using the conductor layer of the core as a ground layer, the noise superimposed on the signal and power supply to the IC chip can be reduced, and the power supply to the IC can be stably supplied. Therefore, when the IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the substrate to the power supply can be reduced. Therefore, the power shortage of the initial operation is reduced, so it is less likely to cause a power shortage, and even if an IC chip in the high-frequency region is mounted, there will be no malfunction or error in the initial startup. Also, since the noise is reduced, it does not cause erroneous actions or errors.

Furthermore, by making the multilayer core substrate, the thickness of each conductor layer of the multilayer core substrate can be reduced while ensuring the sum of the thicknesses of the conductor layers of the multilayer core substrate. That is, in this way, even if a fine wiring pattern is formed, the insulation interval between the wiring patterns can be ensured reliably, and therefore, a printed wiring board with high insulation reliability can also be provided.

As another effect, the strength of the core substrate can be increased by increasing the thickness of the conductor layer for power supply or grounding of the core substrate, so that even if the core substrate itself becomes thinner, the substrate itself can relieve bending or stress.

In addition, the same effect is also produced when power is supplied to the IC chip via the IC chip-substrate-capacitor or the power supply layer-power supply. The loop inductance can be reduced. Therefore, there is no loss of power supply to the capacitor or the dielectric layer. Originally, IC chips consume power instantaneously to perform complex arithmetic processing or operations. By supplying power to the IC chip from the power supply layer, even if the IC chip in the high-frequency region is mounted, the power supply can be supplied without mounting a large number of capacitors when the power supply for the initial operation is insufficient (a situation called a voltage drop occurs). . Originally, the use of an IC chip in a high-frequency region causes insufficient power supply (voltage drop) at the time of initial operation, but in the case of a conventional IC chip, the capacity of the supplied capacitor or dielectric layer is sufficient.

In particular, when the thickness of the conductor layer used as the power supply layer of the core substrate is greater than the thickness of the conductor layer formed on the interlayer insulating layer formed on one or both surfaces of the core substrate, the above three effects can be exhibited to the maximum. The conductor layer on the interlayer insulating layer in this state is the conductor layer on the interlayer insulating layer of the buildup part of the so-called build-up printed wiring board (in the present invention, it is 58, 158 in FIG. 27).

The power supply layer of the core substrate may be disposed on at least one or more layers of the front surface, the back surface, and the inner layer of the substrate. In the state of the inner layer, it is possible to form a multilayer covering two or more layers. It is possible to make the residue layer a ground plane. Basically, if the sum of the power supply layer of the core substrate is thicker than the conductor layer of the interlayer insulating layer, it will have its effect. It is preferable to alternately arrange the conductor layers for power supply and the conductor layers for grounding to improve electrical characteristics.

However, it is preferably formed in the inner layer. When formed in the inner layer, the power supply layer is arranged between the IC chip and the external terminal or capacitor. As a result, the distance between both sides becomes uniform, the cause of obstruction is reduced, and power shortage can be suppressed.

In addition, in a multilayer printed circuit board of the present invention, an interlayer insulating layer and a conductor layer are formed on a core substrate, and are electrically connected through holes for interlayer conduction, and it is characterized in that the thickness of the conductor layer on the core substrate is set to is α1, and the thickness of the conductor layer on the interlayer insulating layer is α2, and α2<α1≤40α2.

When α1≤α2, there is no effect on power shortage at all. That is, in other words, with respect to the voltage drop occurring at the initial operation, the degree of the drop cannot be clearly suppressed.

When the state exceeding α1>40α2 is also considered, since the substrate thickness becomes thicker, the wiring length becomes longer and the amount of voltage drop becomes larger. That is, it can be understood as the critical point of the effect of the present invention. Even if it is such a thickness or more, improvement of an electrical effect cannot be expected. In addition, when the thickness exceeds this thickness, it becomes difficult to form lands for connection to the core substrate with the conductive layer formed on the surface layer of the core substrate. In addition, when the upper interlayer insulating layer is formed, the unevenness becomes large, and fluctuations are generated in the interlayer insulating layer, so impedance matching may not be possible. However, even in this range (α1>40α2), there are cases where no problem occurs.

The thickness α1 of the conductor layer is more preferably 1.2α2≤α1≤40α2. It was confirmed that if it is within this range, malfunction or error of the IC chip due to power shortage (voltage drop) does not occur.

The core substrate in this case refers to a composite core substrate using a resin substrate impregnated with a core material such as glass epoxy resin, ceramic substrate, metal substrate, composite resin, ceramics, and metal. , a metal substrate, a substrate in which a conductor layer is provided in an inner layer of a composite core substrate, a multilayer core substrate in which three or more multilayered conductor layers are formed, and the like.

In order to increase the conductor thickness of the power supply layer, a printed circuit board formed by a method in which a conductor layer is generally formed by electroplating, sputtering, etc. on a metal-embedded substrate can be used.

In the case of a multilayer core substrate, the above-mentioned α1 is the thickness obtained by increasing the conductor layer for power supply in the conductor layer of the surface layer and the conductor layer of the inner layer of the core substrate to be used as the conductor layer for power supply of the core substrate. thickness. In this case, the conductor layer on the surface layer is electrically connected to the conductor layer on the inner layer, and is suitable for electrical connection at two or more locations. That is, even if multilayering is performed, the essence is to increase the thickness of the conductor layer of the core substrate, and the effect itself does not change at all. In addition, as long as the area is about the size of a pad or a land, the thickness of the conductor layer in the area does not become an increased thickness. In this case, a core substrate composed of three layers (surface layer+inner layer) may be used. A multilayer core substrate of three or more layers may also be used.

Electronic component housing core substrates in which components such as capacitors, dielectric layers, and resistors are embedded in the inner layer of the core substrate can be used according to needs.

In addition, when the conductor layer of the inner layer of the core substrate is thickened, it is preferable to arrange the conductor layer directly under the IC chip. By arranging it directly under the IC chip, the distance between the IC chip and the power supply layer can be minimized, thereby further reducing the loop inductance. Therefore, power supply can be performed more efficiently, and voltage shortage can be eliminated. Also at this time, it is preferable to set the sum of the thicknesses of the conductor layers for the power supply of the core substrate to α1, and to set the thickness of the conductor layer on the interlayer insulating layer to α2, and α2<α1≦40α2.

In addition, in the case of a multilayer printed circuit board formed of materials of the same thickness and laminated, the layer or substrate having a power supply layer as a conductor layer in the printed circuit board is defined as a core substrate.

In addition, the multilayer core substrate has a relatively thick conductor layer on its inner layer and a relatively thin conductor layer on its surface layer, and it is preferable that the conductor layer on the inner layer is mainly a conductor layer for a power supply layer or a conductor layer for grounding. (The term "relatively thick" and "relatively thin" means that the thickness of the entire conductor layer has this tendency. In this case, it means that the inner layer is relatively thick compared to other conductor layers, and the surface layer is the opposite.) However, , the surface conductor layer may be used as a conductor layer for power supply or ground, or one side may be used as a conductor layer for power supply and the other surface may be used as a conductor layer for ground.

That is, by arranging a thick conductor layer on the inner layer side, even if its thickness is changed arbitrarily, a resin layer can be formed to cover the conductor layer of the inner layer, so flatness as the core can be obtained. Therefore, no waviness occurs in the conductor layer of the interlayer insulating layer. Even if a thin conductor layer is disposed on the surface layer of the multilayer core substrate, a sufficient thickness of the conductor layer can be ensured by adding the thickness of the core conductor layer to that of the inner conductor layer. By using these as a conductor layer for a power supply layer or a conductor layer for a ground, the electrical characteristics of a multilayer printed wiring board can be improved.

The thickness of the conductor layer on the inner layer of the core substrate is made larger than the thickness of the conductor layer on the interlayer insulating layer. Accordingly, even if a thin conductor layer is disposed on the surface of the multilayer core substrate, the conductor layer as the core can secure a sufficient thickness by adding to the thick conductor layer of the inner layer. In other words, even if a large-capacity power supply is supplied, it can be started without any problem, so that malfunction or malfunction will not occur. Also at this time, it is preferable to set the sum of the thicknesses of the conductive layers for the power supply of the core substrate to α1, and to set the thickness of the conductive layer on the interlayer insulating layer to α2, and α2<α1≦40α2.

In addition, in a multilayer printed circuit board of the present invention, an interlayer insulating layer and a conductor layer are formed on a core substrate, and are electrically connected through holes for interlayer conduction, and is characterized in that a conductor for grounding of the multilayer core substrate is provided. When the layer thickness sum is α3 and the thickness of the conductor layer on the interlayer insulating layer is α2, α3 and α2 satisfy α2<α3≦40α2. By setting it in this range, noise superimposed on the signal power supplied to the IC chip can be reduced. In addition, it is possible to stably supply power to the IC. In addition, when it is in the range of 1.2α1<α3≦40α2, the effect increases.

It is also preferable to form the multilayer core substrate in such a state that the conductor layer of the inner layer is relatively thickened and used as a power supply layer, and the conductor layers of the surface layer are formed so as to sandwich the conductor layer of the inner layer. And it is used as a signal line. With this structure, the aforementioned power supply reinforcement can be achieved.

In addition, since a microstrip structure can be formed by arranging signal lines between conductor layers in the core substrate, inductance can be reduced and impedance matching can be obtained. Therefore, electrical characteristics can also be stabilized. In addition, it is more desirable to make the conductor layer of the surface layer relatively thin. The core substrate can make the via hole pitch ≤ 600μm.

The multi-layer core substrate is preferably constructed in such a way that an inner conductor layer is formed on both sides of an electrically insulating metal plate via a resin layer, and a surface conductor is formed outside the inner conductor layer via a resin layer. layer. Sufficient mechanical strength can be ensured by arranging an electrically insulating metal plate in the center. In addition, by interposing resin layers on both sides of the metal plate,

The inner conductor layer is formed, and the surface conductor layer is formed on the outer side of the inner conductor layer via the resin layer, so that both sides of the metal plate have symmetry, and bending and undulation are prevented during thermal cycles and the like.

The multilayer core substrate can be formed by forming an inner conductor layer on both sides of a metal plate with a low thermal expansion coefficient such as 36 alloy or 42 alloy with an insulating layer interposed therebetween, and an insulating layer is interposed outside the inner conductor layer. And form the conductor layer on the surface. By arranging an electrically insulating metal plate in the center, the thermal expansion coefficient of the X-Y direction of the multilayer printed circuit board can be made close to that of the IC, thereby improving the local thermal cycle of the resin layer at the junction of the IC and the multilayer printed circuit board sex. In addition, by forming an inner conductor layer on both sides of the metal plate with an insulating layer interposed therebetween, and forming a surface conductor layer on the outside of the inner conductor layer with an insulating layer interposed therebetween, there is symmetry on both sides of the metal plate. , In thermal cycling, etc., to prevent bending, undulation.

In FIG. 22 , the voltage of the IC chip is shown on the vertical axis, and the passage of time is shown on the horizontal axis. FIG. 22 is a model of a printed circuit board on which a high-frequency IC chip of 1 GHz or higher is mounted and does not include a capacitor for power supply. Line A is a line showing the voltage of an IC chip of 1 GHz changing with time, and line B is a line showing the voltage of an IC chip of 3 GHz changing with time. This figure shows the third voltage drop out of multiple voltage drops that occur when simultaneous switching is performed. This change over time requires a large amount of power in an instant when the IC chip starts to be activated. When the power supply is insufficient, the voltage drops (point X, point X'). Then, since the supplied power is gradually sufficient, the voltage drop is eliminated. However, when the voltage drops, it is easy to cause malfunction or error of the IC chip. That is, the problem is caused by the insufficient function of the IC chip due to the insufficient supply of the power supply and the non-activation of the IC chip. This power shortage (voltage drop) becomes larger as the frequency of the IC chip increases. Therefore, it takes time to eliminate the voltage drop, and as a result, a time lag occurs in order to perform a desired function or start.

In order to make up for the lack of power (voltage drop), connect an external capacitor to release the power stored in the capacitor, so that the power shortage or voltage drop can be reduced.

In FIG. 23 , a printed circuit board provided with capacitors is used as a model. Line C is a line showing the time-dependent change in voltage of a 1 GHz IC chip with a capacitor of small capacitance mounted thereon. The degree of voltage drop becomes smaller than that of line A without a capacitor. In addition, the line D shows that a capacitor with a larger capacity is installed than that performed by the line C, and the change with time is shown similarly to the line C. In addition, even compared with line C, the degree of the voltage drop becomes smaller. Accordingly, desired IC chips can also function and be activated. However, as shown in Fig. 22, making the IC chip in a higher frequency range requires more capacitor capacity, so it is necessary to set the area where the capacitor is mounted, so it is not easy to secure the voltage, and the operation and function cannot be improved. In addition, It is also difficult to increase the density.

The state of the voltage drop when α1/α2 is changed is shown in the graph of FIG. In Fig. 24, line C is the line that represents the voltage change with time at α1=α2 of the IC chip that installs the capacitor of small electric capacity, 1GHz. In addition, the line F is a line showing the voltage change with time at α1=1.5α2 with a capacitor with a small capacitance installed and a 1GHz IC chip, and line E is a line with a capacitor with a small capacitance installed and a 1GHz IC chip with a voltage of α1=2.0α2 The voltage of the line varies with time. Power starvation or voltage drops are reduced as the conductor layers of the core are thicker and thicker. Therefore, it can be said that there are fewer problems with the function and operation of the IC chip. The volume of the conductor layer is increased by increasing the thickness of the conductor layer for the power supply of the core substrate. When the volume increases, the resistance of the conductor is reduced, so that the voltage and current loss of the transmitted power supply disappears. Accordingly, the transmission loss between the IC chip and the power source is reduced, and the power source can be supplied without causing malfunctions, errors, and the like. In this case, the thickness of the conductor layer for the power supply and the cause thereof are particularly large, and the thickness of the conductor layer for the power supply of the core substrate is greater than the thickness of the conductor layer on the interlayer insulating layer. Effect.

In addition, it has been found that not only when the conductive layer for power supply formed on one or both surfaces of the core substrate is thickened, but also in a core substrate with three or more layers in which the conductive layer is formed , also produces the same effect. That is, there is an effect of reducing power shortage or voltage drop. In addition, in the case of a multilayer core substrate, even if the thickness of the conductor layer for power supply in all layers of the core substrate is greater than the thickness of the conductor layer on the interlayer insulating layer, the thickness of the conductor layer for power supply in all layers of the core substrate When it is less than or equal to the thickness of the conductor layer on the interlayer insulating layer, as long as the sum of the thicknesses obtained by adding the thicknesses of the conductor layers for the power supply of all layers is greater than the thickness of the conductor layer on the interlayer insulating layer, it can be achieved its effect. In this case, there is no difference in the area of each conductor layer. That is, the effect is achieved in a state where the area ratio is almost the same. For example, in a two-layer conductor layer, the large area of the entire layer (beta) of one layer offsets the other layer when the other layer is a hole for interlayer conduction and its land level. The effect of the conductor layer.

In addition, a remarkable effect is exhibited even in a substrate in which electronic components such as capacitors, dielectric layers, and resistors are provided in a core substrate. The distance between IC chip and capacitor or dielectric layer can be shortened by built-in. Therefore, loop inductance can be reduced. Can make power shortage or voltage drop smaller. For example, even in a core substrate with built-in capacitors or dielectric layers, the thickness of the conductive layer for the power supply of the core substrate can be made larger than the thickness of the conductive layer on the interlayer insulating layer, thereby reducing the number of main power supplies and built-in capacitors or dielectric layers. Therefore, the transmission loss can be reduced, and the effect of the substrate with built-in capacitors can be more exerted.

The material of the core substrate was verified with a resin substrate, but it is known that ceramic and metal core substrates can achieve the same effect. In addition, although the material of the conductor layer is made of a metal composed of copper, it cannot be confirmed that using other metals will offset the effect and increase the occurrence of malfunctions or errors. Therefore, it is considered that the material of the core substrate is different or the formation of the conductor The material of the layer is different and has no effect on its effect. It is more desirable that the conductor layer of the core substrate and the conductor layer of the interlayer insulating layer be formed of the same metal. There is no change in characteristics or physical properties such as electrical characteristics and thermal expansion coefficients, thereby producing the effects of the present invention.

According to the present invention, the resistance on the conductors of IC chip-substrate-power supply can be reduced, and the transmission loss can be reduced. The signal or power thus transmitted can exhibit the desired capability. As a result, since the functions, operations, etc. of the IC chip are normally operated, erroneous operations or errors do not occur. It can reduce the resistance of conductors from IC chip to substrate to ground, reduce noise superimposed on signal lines and power lines, and prevent malfunctions or errors.

In addition, it was also found that the degree of power shortage (voltage drop) that occurs at the initial start-up of the IC chip is reduced by the present invention; chip, also boots without problems. Therefore, electrical characteristics or electrical connectivity can also be improved.

Next, by multilayering the core substrate, the thickness and sum of the conductor layers can be increased, whereby a printed circuit board having good insulation reliability can be produced.

In addition, the resistance in the circuit of the printed circuit board can be reduced compared with the conventional printed circuit board. Therefore, even if a reliability test (high-temperature and high-humidity bias test) is performed under high temperature and high humidity with a bias applied, the destruction time becomes longer, so that reliability can be improved.

In addition, since the electrical resistance of the conductor layer for power supply is lowered, heat generation can be suppressed even when a large amount of electricity flows. The same applies to the ground plane. This point also makes it difficult for malfunction to occur, and the reliability of the printed circuit board after IC mounting becomes high.

In addition, it is preferable that the side surface of the conductor layer of the core substrate is tapered (a linear taper as shown in FIG. 27(B) or an R-shaped taper as shown in FIG. 27(C)), and it is provided to connect the conductor layer. When the angle formed between the upper end and the lower end of the side surface and the horizontal plane of the core substrate is Θ, use the multilayer printed circuit board of the multilayer core substrate as shown in Figure 27 (A) as an example, as shown in Figure 27 (B ), as shown in FIG. 27(C), when the straight line connecting the upper end and the lower end of the side surface of the conductor layer 16E of the inner layer of the core substrate and the core substrate forms an angle Θ, Θ preferably satisfies the relational expression 2.8<tanΘ< 55. The same goes for 16P. By forming the conductive layer in this way, even if the conductive layer is formed with a large thickness, the reliability will not be lowered. In addition, IC malfunctions due to signal delay or insufficient signal strength are less likely to occur. When tanΘ becomes smaller, the volume of the conductor layer decreases, and a delay in power supply to the IC tends to occur. On the other hand, when tanΘ becomes large, the signal strength tends to deteriorate at the via hole. The reasons for the deterioration of the signal strength will be described by taking a four-layer core with a thick inner conductor layer as an example. Pay attention to the signal via hole (via hole electrically connected to the IC signal circuit) that penetrates the multilayer core. As shown in FIG. 31 , the signal via hole penetrates the insulating layer 1 , the ground layer, the insulating layer 2 , the power supply layer, and the insulating layer 3 from the top. Since the impedance of the signal wiring varies depending on the presence or absence of a ground or a power supply, etc. around the signal wiring, the impedance value varies with the interface X1 between the insulating layer 1 and the ground layer as a boundary. This causes reflection of the signal at the interface. The same phenomenon occurs at X2, X3, and X4. Such impedance variation increases as the distance between the signal via hole and the ground layer and the power layer gets closer, and the thickness of the ground layer and the power layer becomes thicker and larger. Therefore, the multi-layer core of the present invention having a thick conductor layer in the inner layer tends to cause signal degradation at via holes. In order to prevent this signal from deteriorating, it is preferable to reduce the value of tanΘ. By reducing the tanΘ value, even if the minimum distance between the signal via hole and the inner layer conductor layer is the same, that is, even if the density is the same, since the distance between the signal via hole and the inner layer conductor layer gradually increases in the cross-sectional direction. The ground expands, and the amount of change in impedance becomes smaller. Since this problem tends to occur when an IC with a higher driving frequency is mounted, tanΘ≤11.4 is preferable, and tanΘ≤5.7 is more preferable.

Description of drawings

1(A) to (D) are process diagrams showing a method of manufacturing a multilayer printed circuit board according to a first embodiment of the present invention.

2(A) to (E) are process diagrams showing the method of manufacturing the multilayer printed wiring board of the first embodiment.

3(A) to (D) are process diagrams showing the method of manufacturing the multilayer printed wiring board of the first embodiment.

4(A) to (C) are process diagrams showing the method of manufacturing the multilayer printed wiring board of the first embodiment.

5(A) to (B) are process diagrams showing the method of manufacturing the multilayer printed wiring board of the first embodiment.

Fig. 6 is a cross-sectional view of the multilayer printed circuit board of the first embodiment.

7 is a cross-sectional view showing a state in which an IC chip is mounted on the multilayer printed circuit board of the first embodiment.

8(A) is a cross-sectional view of a multilayer printed circuit board according to a modification of the first embodiment; FIG. 8(B) and FIG. 8(C) are explanatory diagrams showing enlarged conductor layers surrounded by a circle b.

Fig. 9 is a cross-sectional view of a multilayer printed circuit board of a third embodiment.

10 is a cross-sectional view showing a state in which an IC chip is mounted on the multilayer printed circuit board of the third embodiment.

Fig. 11 is a cross-sectional view of a multilayer printed circuit board of a fourth embodiment.

Fig. 12 is a cross-sectional view showing a state in which an IC chip is mounted on the multilayer printed circuit board of the fourth embodiment.

13(A) to (F) are process diagrams showing a method of manufacturing a multilayer printed wiring board according to a fifth embodiment of the present invention.

14(A) to (E) are process diagrams showing a method of manufacturing a multilayer printed wiring board according to the fifth embodiment.

15(A) to (C) are process diagrams showing a method of manufacturing a multilayer printed wiring board according to the fifth embodiment.

16(A) to (C) are process diagrams showing a method of manufacturing a multilayer printed wiring board according to the fifth embodiment.

Fig. 17 is a cross-sectional view of a multilayer printed circuit board of a fifth embodiment.

Fig. 18 is a cross-sectional view showing a state in which an IC chip is mounted on a multilayer printed circuit board according to the fifth embodiment.

19 is a cross-sectional view showing a state in which an IC chip is mounted on a multilayer printed circuit board according to a modification example of the fifth embodiment.

Fig. 20 is a cross-sectional view of a multilayer printed circuit board of a sixth embodiment.

Fig. 21 is a cross-sectional view showing a state in which an IC chip is mounted on a multilayer printed circuit board according to the sixth embodiment.

FIG. 22 is a graph showing voltage changes during the operation of the IC chip.

FIG. 23 is a graph showing voltage changes during the operation of the IC chip.

FIG. 24 is a graph showing voltage changes during the operation of the IC chip.

Fig. 25 is a graph showing test results of Examples.

Fig. 26 is a graph showing test results of Examples and Comparative Examples.

27(A) is a cross-sectional view of a multilayer printed circuit board of the seventh embodiment, and FIGS. 27(B) and 27(C) are explanatory diagrams showing enlarged passages through a conductor layer surrounded by a circle b.

Fig. 28 is a graph showing the test results of the seventh example.

29 is a graph showing changes in insulation resistance and resistivity with respect to tanΘ when the angle between the straight line connecting the upper end and the lower end of the conductor layer and the horizontal plane of the core substrate is Θ.

Fig. 30 is a graph showing the test results of the eighth example.

Fig. 31 is a schematic diagram of signal via holes penetrating the multilayer core.

Fig. 32 is a graph showing the test results of the ninth example.

Fig. 33 is a graph showing the test results of the ninth example.

Fig. 34 is a graph showing the test results of the ninth example.

Fig. 35 is a graph showing the amount of voltage drop with respect to α1/α2.

Fig. 36 is a graph showing the test results of the ninth example.

Fig. 37 is a graph showing the test results of the tenth example.

38(A) shows a state where the cross section of the inner layer of the multilayer core substrate does not have dummy lands, and FIG. 38(B) shows a state where the cross section of the inner layer of the multilayer core substrate has dummy lands.

Detailed ways

[First Example] Glass epoxy substrate

First, the structure of a multilayer printed circuit board 10 according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 7 . 6 is a cross-sectional view showing the multilayer printed circuit board 10, and FIG. 7 shows a state in which an IC chip 90 is mounted on the multilayer printed circuit board 10 shown in FIG. 6 and placed on a daughter board 94. As shown in FIG. 6 , in multilayer printed wiring board 10 , conductive circuit 34 and conductive layer 34P are formed on the front surface of core substrate 30 , and conductive circuit 34 and conductive layer 34E are formed on the back surface thereof. The conductive layer 34P on both sides is formed as a plane layer for power supply, and the conductor layer 34E on the lower side is formed as a plane layer for ground. The front and back surfaces of the core substrate 30 are connected by via holes 36 . In addition, the interlayer resin insulating layer 50 formed with the interlayer conduction hole 60 and the conductor circuit 58 and the interlayer resin insulation layer 150 formed with the interlayer conduction hole 160 and the conductor circuit 158 are arranged on the conductor layers 34P and 34E. . The solder resist layer 70 is formed on the upper layer of the interlayer conduction hole 160 and the conductor circuit 158 , and the bumps 76U, 76D are formed on the interlayer conduction hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70 . .

As shown in FIG. 7 , the solder bumps 76U on the upper side of the multilayer printed circuit board 10 are connected to the lands 92 of the IC chip 90 . In addition, a chip capacitor 98 is mounted. On the other hand, the solder bump 76D on the lower side is connected to the land 96 of the sub-board 94 .

Here, the conductive layers 34P and 34E on the core substrate 30 are formed to have a thickness of 5 to 250 μm, and the conductive circuit 58 on the interlayer resin insulating layer 50 and the conductive circuit 158 on the interlayer resin insulating layer 150 are formed to have a thickness of 5 to 25 μm (ideally The range is 10-20 μm).

In the multilayer printed circuit board of the first embodiment, the strength of the core substrate is increased by increasing the thickness of the power supply layer (conductor layer) 34P and the conductor layer 34E of the core substrate 30, so that even if the thickness of the core substrate itself is reduced, It is also possible to relax warping or generated stress by the substrate itself.

Furthermore, the volume of the conductor itself can be increased by making the conductor layers 34P, 34E thick. By increasing this volume the resistance on the conductor can be reduced.

In addition, by using the conductor layer 34P as a power supply layer, the ability to supply power to the IC chip 90 can be improved. Therefore, when IC chips are mounted on the multilayer printed board, the loop inductance from the IC chip to the substrate to the power supply can be reduced. Therefore, since the power shortage at the time of the initial operation is reduced, it is less likely to cause a power shortage, and thus, even if an IC chip in a higher frequency range is mounted, erroneous operation or errors in the initial startup will not be caused. In addition, by using the conductor layer 34E as a ground layer, there is no overlap of noise in the signal and power supply of the IC chip, and malfunctions and errors can be prevented.

Next, a method of manufacturing the multilayer printed wiring board 10 described with reference to FIG. 6 will be described with reference to FIGS. 1 to 5 .

(first embodiment-1)

A. Manufacture of resin film for interlayer resin insulating layer

Bisphenol A type epoxy resin (455 epoxy equivalents, Epikote 1001 manufactured by (油化エルエポキシ company)) 29 parts by weight, cresol-novolak type epoxy resin (215 epoxy equivalents, Dainippon Ink Chemical Industry Co., Ltd. 39 parts by weight of Epikuron (Epikuron) N-673), 30 parts by weight of phenol novolac resin (phenolic hydrocarbon group equivalent 120, Dainippon Ink Chemical Industry Co., Ltd. phenate KA-7052) containing a triazine structure, heated and melted while stirring To 20 parts by weight of diethylene glycol ethyl ether acetate and 20 parts by weight of mineral spirits, 15 parts by weight of terminally epoxidized polybutadiene rubber (Tenarekkusu R-45EPT manufactured by Nagase Chemical Industry Co., Ltd.) and 2 parts by weight were added. - 1.5 parts by weight of pulverized phenyl-4,5-bis(hydroxymethyl)imidazole, 2.5 parts by weight of finely ground silica, and 0.5 parts by weight of silicon-based antifoaming agent to prepare an epoxy resin composition.

After applying the above-obtained epoxy resin composition on a PET film with a thickness of 38 μm using a roll coater so that the thickness after drying becomes 50 μm, it is subjected to 10-minute drying at 80 to 120° C. After drying, a resin film for an interlaminar resin insulating layer was prepared.

B. Preparation of resin filler

By using 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuhua Shiel Co., Ltd., molecular weight: 310, YL983U), the average particle diameter of the silane coupling agent on the surface is 1.6 μm and the diameter of the largest particle is less than or 170 parts by weight of SiO2 spherical particles equal to 15 μm (manufactured by Adotec, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (manufactured by Sannopuko, Perenoru (ペレノル) S4) were placed in a container and stirred And mix, and prepare the resin filler whose viscosity is 44～49Pa·s at 23±1℃. In addition, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Chemicals, Inc., 2E4MZ-CN) was used as a curing agent. As the filler resin, thermosetting resins such as other epoxy resins (for example, bisphenol A type, novolak type, etc.), polyimide resins, and phenolic resins can be used.

C. Manufacture of multilayer printed circuit boards

(1) Copper foil 32 of 5 to 250 μm is laminated on both sides of an insulating substrate 30 made of glass epoxy resin or BT (bismaleic anhydride imide triazine) resin with a thickness of 0.2 to 0.8 mm. A copper foil substrate 30A was used as a starting material (FIG. 1(A)). First, by drilling the copper foil substrate with a drill, performing electroless plating treatment and electrolytic plating treatment, and etching into a pattern shape, the conductive circuit 34, the conductive layers 34P, 34E, and the conductive circuit 34 are formed on both sides of the substrate. hole 36 (Fig. 1(B)).

(2) After washing and drying the substrate 30 on which the through hole 36 and the lower conductor circuit 34 have been formed, a mixture containing NaOH (10g/l), NaClO ₂ (40g/l) and Na ₃ PO ₄ (6g/l) is carried out. ) aqueous solution as a blackening bath (oxidation bath) and reduction treatment using an aqueous solution containing NaOH (10g/l) and NaBH ₄ (6g/l) as a reduction bath, a coarse At the same time, roughened surface 34α is formed on the entire surface of conductive circuit 34 and conductive layers 34P and 34E ( FIG. 1(C) ).

(3) After preparing the resin filling material described in B above, a layer of the resin filling material 40 is formed in the through hole 36 and the non-conductive circuit portion of the substrate by the following method within 24 hours after the preparation (FIG. 1( D)).

That is, a resin-filled mask having a plate having a partial opening corresponding to a through-hole and a non-conductive circuit formation portion is placed on a substrate, and a squeegee is used to form a lower layer non-conductive circuit formation portion that becomes a recess in the through hole. And the outer edge of the lower conductor circuit was filled with a resin filler, and dried at 100° C./20 minutes.

(4) Grinding with a belt grinder using #600 belt grinding paper (manufactured by Sankyo Chemical Co., Ltd.) to polish one side of the substrate after the above (3) treatment, so that the outer edges of the conductor layers 34P, 34E or The resin filler 40 does not remain on the outer edge of the land of the through hole 36. Next, in order to remove the damage caused by the above-mentioned grinding with the belt grinder, the entire surface of the conductor layers 34P, 34E (including the through hole) The surface of the connection plate) is polished and ground. Such a series of polishing is similarly performed on other surfaces of the substrate. Next, heat treatment was performed at 100° C. for 1 hour, and then at 150° C. for 1 hour to cure the resin filler 40 ( FIG. 2(A) ).

In this way, it is possible to obtain a substrate in which the surface portion of the resin filler 40 formed in the through hole 36 and the portion where the conductor circuit is not formed and the surfaces of the conductor layers 34P, 34E are flattened, and the resin filler 40 and the conductor layers 34P, 34E are flattened. The side surface of the substrate is firmly in close contact with the roughened surface, and the inner wall surface of the through hole 36 and the resin filler are firmly in close contact with the roughened surface. That is, through this step, the surface of the resin filler and the surface of the lower conductor circuit become substantially the same plane.

The thickness of the conductive layer of the core substrate is formed in the range of 1 to 250 μm, and the thickness of the conductive layer of the power supply layer formed on the core substrate is formed in the range of 1 to 250 μm. At this time, in Example 1-1, copper foil with a thickness of 40 μm was used, the thickness of the conductor layer of the core substrate was 30 μm, and the thickness of the conductor layer of the power supply layer formed on the core substrate was 30 μm. However, the thickness of the conductor layer may exceed the above thickness range.

(5) After the above-mentioned substrate is washed with water and acid degreasing, light etching is carried out, and then, the etching solution is blown on both sides of the substrate with a sprayer to etch the connection of the conductor circuit 34, the surface of the conductor layer 34P, 34E and the through hole 36. The surface of the disk, thereby forming a roughened surface 366 on the entire surface of the conductor circuit (FIG. 2(B)). As an etchant, an etchant (manufactured by Mekku, Mekkuetchbond, Mekkuetchbond) composed of 10 parts by weight of an imidazolium copper (II) complex, 7.3 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used. )).

(6) On both sides of the substrate, the interlayer resin insulating layer resin film 50Y slightly larger than the substrate produced in A is placed on the substrate, and the pressure is 0.45MPa, the temperature is 80°C, and the bonding time is 10 seconds. Under the conditions, after performing temporary lamination and cutting, and also using the following method, using a vacuum laminator to attach to form an interlayer resin insulating layer (FIG. 2(C)). That is, under the conditions of vacuum degree of 67Pa, pressure of 0.47MPa, temperature of 85°C, and bonding time of 60 seconds, the resin film for the interlayer resin insulating layer is fully bonded on the substrate, and then the resin film is bonded at 170°C for 40 minutes. heat curing.

(7) Next, by a CO ₂ gas laser with a wavelength of 10.4 μm, the beam diameter is 4.0 mm, the tophat mode, the pulse width is 3.0 to 8.1 μ seconds, and the diameter of the through hole of the mask is 1.0 to 5.0 mm. , Under the condition of 1 to 3 shots, an opening 50a for an interlayer conduction hole with a diameter of 60 to 100 μm is formed on the interlayer resin insulating layer ( FIG. 2(D) ). This time the formation diameters were 60 μm and 75 μm.

(8) By immersing the substrate having the openings 50a for interlayer conduction holes in a solution at 80°C containing 60 g/l of permanganic acid for 10 minutes, the resin existing on the surface of the interlayer resin insulating layer 2 is dissolved and removed. epoxy resin particles, a roughened surface 50α is formed on the surface of the interlayer resin insulating layer 50 including the inner wall of the opening 50a for the interlayer conduction hole (FIG. 2(E)).

(9) Next, after immersing the above-mentioned substrate in a neutralization solution (manufactured by Sibuley Co., Ltd.), water was washed.

In addition, by applying a palladium catalyst to the surface of the substrate after roughening treatment (roughening depth: 3 μm), catalyst nuclei adhered to the surface of the interlayer resin insulating layer and the inner wall surface of the opening for the interlayer conduction hole. That is, the catalyst is imparted by immersing the above-mentioned substrate in a catalyst solution containing palladium chloride (PdCl2) and stannous chloride (SnCl2) to deposit palladium metal.

(10) Next, immerse the catalyst-applied substrate in an electroless copper plating aqueous solution of the following composition to form an electroless copper plating film with a thickness of 0.3 to 3.0 μm on the entire rough surface, thereby obtaining A substrate in which an electroless copper plating film 52 is formed on the surface of the interlaminar resin insulating layer 50 on the inner wall of the opening 50a ( FIG. 3(A) ).

[Electroless plating aqueous solution]

NiSO4 0.003mol/l

Tartaric acid 0.200mol/l

Copper sulfate 0.032mol/l

HCHO 0.050mol/l

NaOH 0.100mol/l

α,α'-bipyridine 100mg/l

Polyethylene glycol (PEG) 0.10g/l

[Electroless plating conditions]

45 minutes at a liquid temperature of 34°C

(11) By affixing a commercially available photosensitive dry film on the substrate on which the electroless copper plating film 52 is formed, ^exposing at 110 mJ/cm after placing a mask, and developing with 0.8% sodium carbonate aqueous solution , thereby providing a plating resist 54 having a thickness of 25 μm (FIG. 3(B)).

(12) Next, the substrate was washed with water at 50°C, degreased, washed with water at 25°C, and washed with sulfuric acid, and electrolytic plating was performed under the following conditions. The electrolytic copper plating film 56 is formed in the non-formation part (FIG. 3(C)).

[Electrolytic plating solution]

Sulfuric acid 2.24mol/l

Copper sulfate 0.26mol/l

Additives 19.5ml/l

(Atoteck-Japan (アトテツクジヤパン) Co., Ltd., Kaparashido (カパラシド) GL)

[Electrolytic plating conditions]

Current density 1A/dm2

Time 65 minutes

Temperature 22±2℃

(13) In addition, after the plating resist 3 was removed by stripping with 5% KOH, the electroless plating film under the plating resist was dissolved and removed by etching treatment with a mixture of sulfuric acid and hydrogen peroxide. coating to form an independent conductor circuit 58 and an interlayer conduction hole 60 ( FIG. 3(D)).

(14) Next, the same process as in (5) above is performed to form roughened surfaces 58α, 60α on the surfaces of the conductive circuit 58 and the interlayer via hole 60 . The thickness of the conductor circuit 58 in the upper layer was 15 μm ( FIG. 4(A) ). However, the thickness of the conductor circuit in the upper layer can be formed within a range of 5 to 25 μm.

(15) By repeatedly performing the above-mentioned steps (6) to (14), and also forming an upper layer conductor circuit, a multilayer circuit board is obtained ( FIG. 4(B) ).

(16) Next, by dissolving in diethylene glycol dimethyl ether (DMD G) to a concentration of 60% by weight, 50% of epoxy groups of p-cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) were acrylic 45.67 parts by weight of a photosensitive oligomer (molecular weight: 4000) and 80% by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuhua Shell Co., Ltd., Product name: Epikote (エピコ-ド) 1001) 16.0 parts by weight, imidazole curing agent (manufactured by Shikoku Chemicals Co., Ltd., product name: 2E4MZ-CN) 1.6 parts by weight, bifunctional acryl monomer (acryl monomer) as a photosensitive monomer (manufactured by Nippon Kayaku Co., Ltd., trade name: R604) 4.5 parts by weight, the same polyvalent propylene-based monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: DPE6A) 1.5 parts by weight, and a dispersion defoamer (Sannopuko (サンノプコ) Made by the company, S-65) 0.71 parts by weight were placed in a container, stirred and mixed to prepare a mixed composition, and benzophenone (manufactured by Kanto Chemical Co., Ltd.) was added as a photopolymerization initiator to the mixed composition. 1.8 parts by weight and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Chemical Co., Ltd.) as a photosensitizer were used to obtain a solder resist composition whose viscosity at 25° C. was adjusted to 2.0 Pa·s.

In addition, the viscosity measurement was performed with a B-type viscometer (DVL-B type manufactured by Tokyo Keiki Co., Ltd.) at 60 min ⁻¹ with roll No. 4 and at 6 min ⁻¹ with roll No. 3.

(17) Next, on both surfaces of the multilayer circuit board, the above-mentioned solder resist composition 70 was applied to a thickness of 20 μm, and dried at 70° C. for 20 minutes and 70° C. for 30 minutes ( 4(C)), a photomask with a thickness of 5 mm and a solder resist opening pattern drawn thereon is closely contacted to the solder resist layer 70, exposed to ultraviolet rays of 1000 mJ/cm ² , and developed with a DMTG solution to form Opening 71 with a diameter of 200 μm ( FIG. 5(A) ).

Next, heat treatment was performed at 80° C. for 1 hour, at 100° C. for 1 hour, at 120° C. for 1 hour, and at 150° C. for 3 hours. The solder layer was cured to form a solder resist pattern layer having openings and a thickness of 15-25 μm. A commercially available solder resist composition can also be used as the said solder resist composition.

(18) Next, dip the substrate on which the solder resist layer 70 was formed in a solution containing nickel chloride (2.3×10 ^-1 mol/l), sodium hypophosphite (2.8×10 ^-1 mol/l) and sodium citrate (1.6 ×10 ⁻¹ mol/l) in an electroless nickel plating solution of pH=4.5 for 20 minutes, a nickel plating layer 72 with a thickness of 5 μm was formed on the opening 71 . In addition, the substrate was immersed in a solution containing potassium gold cyanide (7.6×10 ^-3 mol/l), ammonium chloride (1.9×10 ^-1 mol/l), sodium citrate (1.2×10 ^-1 mol/l) and sodium hypophosphite (1.7×10 ^-1 mol/l) in an electroless gold plating solution for 7.5 minutes, a 0.03 μm gold-plated layer 74 with a thickness of 0.03 μm was formed on the nickel-plated layer 72 (Fig. 5(B)) . In addition to nickel metals, single layers of tin, noble metal layers (gold, silver, palladium, platinum, etc.) can also be formed.

(19) Then, on the opening 71 of the solder resist layer 70 on the surface of the IC chip on which the substrate is placed, print the solder paste containing tin-lead, and print the solder paste containing tin-antimony on the opening of the solder resist layer on the other side. After soldering the paste, remelting was performed at 200° C. to form solder bumps (solder body), and a multilayer printed wiring board having solder bumps 76U and 76D was manufactured ( FIG. 6 ).

IC chip 90 is mounted through solder bump 76U, and chip capacitor 98 is mounted. Next, it is mounted on the daughter board 94 via the solder bump 76D (FIG. 7).

(first embodiment-2)

Although it is the same as the first embodiment-1 described with reference to FIG. 6 , it is manufactured as follows.

Thickness of conductor layer of core substrate: 55 μm

Thickness of the power supply layer of the core substrate: 55 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(first embodiment-3)

Although it is the same as the first embodiment-1, it is manufactured as follows.

The thickness of the conductor layer of the core substrate: 75 μm

Thickness of the power supply layer of the core substrate: 75 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(first embodiment-4)

Although it is the same as the first embodiment, it is manufactured as follows.

The thickness of the conductor layer of the core substrate: 180 μm

Thickness of the power supply layer of the core substrate: 180 μm

Thickness of the conductor layer of the interlayer insulating layer: 6 μm

(first embodiment-5)

Although it is the same as the first embodiment, it is manufactured as follows.

Conductor layer thickness of core substrate: 18 μm

Thickness of the power supply layer of the core substrate: 18 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

In addition, in the first embodiment, 1<(thickness of the conductor layer of the power supply layer of the core substrate/thickness of the conductor layer of the interlayer insulating layer)≤40 is taken as a suitable example, and (the conductor of the power supply layer of the core substrate Layer thickness/conductor layer thickness of interlayer insulating layer) ≤ 1 was taken as a comparative example. In addition, take (thickness of conductor layer of power supply layer of core substrate/thickness of conductor layer of interlayer insulating layer)>40 as a reference example.

Fig. 8(A) shows a modified example of the first embodiment. The side surfaces of the conductor layers 34P, 34E of the core substrate 30 are tapered (straight-line tapered as shown in FIG. 10(B) or R-shaped tapered as shown in FIG. When the angle between the upper end and lower end of the side surface of 34E and the horizontal plane of the core substrate is Θ, the straight line connecting the upper and lower ends of the side surfaces of the inner conductor layers 34P and 34E of the core substrate and the core substrate When the angle of Θ is Θ, Θ is configured to satisfy the relational expression of 2.8<tanΘ<55.

Corresponding to the first embodiment-1 to the first embodiment-5, the first embodiments-6 to 10 in which the side surfaces of the conductor layers 34P and 34E of the core substrate 30 are formed into an R-plane tapered shape satisfying the above-mentioned relational expression are fabricated. . In addition, the etching method for forming a tapered shape will be described later.

[Second embodiment] Ceramic substrate

The multilayer printed circuit board of the second embodiment will be described.

In the first embodiment described with reference to FIG. 6, the core substrate is formed of insulating resin. In contrast, in the second embodiment, the core substrate is an inorganic hard substrate made of ceramics, glass, ALN, mullite, etc. Since they are the same, illustration and description are omitted.

Even in the multilayer printed circuit board of the second embodiment, the conductive layers 34P, 34E, and 34 on the core substrate 30 are formed of metals such as copper and tungsten, and the conductive circuits 58 on the interlayer resin insulating layer 50 and the interlayer resin Conductor circuit 158 on insulating layer 150 is formed of copper. Also in this second embodiment, the same effect as that of the first embodiment is obtained. At this time, the thickness of the conductor of the core substrate, the thickness of the power supply layer of the core substrate, and the thickness of the interlayer insulating layer are formed to be the same as those of the first embodiment. In addition, in the second embodiment, 1<(thickness of the conductor layer of the power supply layer of the core substrate/thickness of the conductor layer of the interlayer insulating layer)≤40 is taken as a suitable example, and (the conductor of the power supply layer of the core substrate Layer thickness/conductor layer thickness of interlayer insulating layer) ≤ 1 was taken as a comparative example. In addition, take (thickness of conductor layer of power supply layer of core substrate/thickness of conductor layer of interlayer insulating layer)>40 as a reference example.

(Second Embodiment-1)

Although it is the same as the above-mentioned second embodiment, it is manufactured as follows.

Conductor layer thickness of core substrate: 30 μm

Thickness of the power supply layer of the core substrate: 30 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(Second Embodiment-2)

Although it is the same as the above-mentioned second embodiment, it is manufactured as follows.

Conductor layer thickness of core substrate: 50 μm

Thickness of the power supply layer of the core substrate: 50 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(Second Embodiment-3)

Although it is the same as the above-mentioned second embodiment, it is manufactured as follows.

The thickness of the conductor layer of the core substrate: 75 μm

Thickness of the power supply layer of the core substrate: 75 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(Second Embodiment-4)

Although it is the same as the above-mentioned second embodiment, it is manufactured as follows.

The thickness of the conductor layer of the core substrate: 180 μm

Thickness of the power supply layer of the core substrate: 180 μm

Thickness of the conductor layer of the interlayer insulating layer: 6 μm

[Third embodiment] Metal core substrate

A multilayer printed circuit board according to a third embodiment will be described with reference to FIGS. 9 and 10 .

In the first embodiment described with reference to FIG. 6, the core substrate is formed of a resin plate. On the other hand, in the third embodiment, the core substrate is made of a metal plate.

9 is a cross-sectional view showing a multilayer printed circuit board 10 according to the third embodiment, and FIG. 10 shows a state in which an IC chip 90 is mounted on the multilayer printed circuit board 10 shown in FIG. 9 and placed on a daughter board 94 . As shown in FIG. 9 , in the multilayer printed wiring board 10 , the core substrate 30 is formed of a metal plate and used as a power supply layer. On both sides of the core substrate 30, an interlayer resin insulating layer 50 having interlayer conduction holes 60 and conductive circuits 58 is formed, and an interlayer resin insulating layer 50 having interlayer conduction holes 160 and conductor circuits 158 is formed. Interlaminar resin insulating layer 150 . Through holes 36 are formed in the through holes 33 of the core substrate 30 , and cover plating layers 37 are disposed on both ends of the holes for interlayer conduction. A solder resist layer 70 is formed on the interlayer via hole 160 and the conductive circuit 158 , and bumps 76U, 76D are formed on the interlayer via hole 160 and the conductive circuit 158 through the opening 71 of the solder resist layer 70 .

As shown in FIG. 10 , the solder bumps 76U on the upper surface side of the multilayer printed circuit board 10 are connected to the lands 92 of the IC chip 90 . In addition, a chip capacitor 98 is installed. On the other hand, the lower solder bumps 76D are connected to the lands 96 of the sub-board 94 .

Here, the core substrate 30 is formed to have a thickness of 200 to 600 μm. The thickness of the metal plate is formed between 15-300 μm. The thickness of the conductive layer of the interlayer insulating layer may be formed between 5 and 25 μm. However, the thickness of the metal layer may exceed the above range.

In this third embodiment, the same effect as that of the first embodiment can be obtained.

(third embodiment-1)

Although it is the same as the third embodiment described with reference to FIG. 9 , it is set as follows.

Thickness of core substrate: 550 μm

Thickness of the power supply layer of the core substrate: 35 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(third embodiment-2)

Although it is the same as the third embodiment, it is set as follows.

Thickness of core substrate: 600 μm

Thickness of the power supply layer of the core substrate: 55 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(third embodiment-3)

Although it is the same as the third embodiment, it is set as follows.

Thickness of core substrate: 550 μm

Thickness of the power supply layer of the core substrate: 100 μm

Thickness of the conductor layer of the interlayer insulating layer: 10 μm

(third embodiment-4)

Although it is the same as the third embodiment, it is set as follows.

Thickness of core substrate: 550 μm

Thickness of the power supply layer of the core substrate: 180 μm

Thickness of the conductor layer of the interlayer insulating layer: 6 μm

(third embodiment-5)

Although it is the same as the third embodiment, it is set as follows.

Thickness of core substrate: 550 μm

Thickness of the power supply layer of the core substrate: 240 μm

Thickness of the conductor layer of the interlayer insulating layer: 6 μm

In addition, in the third embodiment, 1<(thickness of the conductor layer of the power supply layer of the core substrate/thickness of the conductor layer of the interlayer insulating layer)≤40 is taken as a suitable example, and (the conductor of the power supply layer of the core substrate Layer thickness/conductor layer thickness of interlayer insulating layer) ≤ 1 was taken as a comparative example. In addition, take (thickness of conductor layer of power supply layer of core substrate/thickness of conductor layer of interlayer insulating layer)>40 as a reference example.

[Fourth embodiment] 3-layer core substrate

A multilayer printed circuit board according to a fourth embodiment will be described with reference to FIG. 11 and FIG. 1 .

In the first embodiment described with reference to FIG. 6, the core substrate is formed of a single plate. On the other hand, in the fourth embodiment, the core substrate is composed of a laminate, and the conductor layer is provided in the laminate.

11 is a cross-sectional view showing a multilayer printed circuit board 10 according to the fourth embodiment, and FIG. 12 shows a state in which an IC chip 90 is mounted on the multilayer printed circuit board 10 shown in FIG. 11 and mounted on a daughter board 94 . As shown in FIG. 11 , in multilayer printed wiring board 10 , conductive circuit 34 and conductive layer 34P are formed on the front and back surfaces of core substrate 30 , and conductive layer 24 is formed in core substrate 30 . The conductor layer 34P and the conductor layer 24 are formed as a plane layer for power supply. The conductor layer 34P and the conductor layer 24 are connected by the conductive column 26 (the conductive column in this state refers to a hole for interlayer conduction such as a through hole, a non-through hole (including a blind via hole, a blind interlayer conduction hole) The vias or interlayer vias are filled with the conductive material of the hole.). Further, interlayer resin insulating layer 50 formed with interlayer conduction hole 60 and conductor circuit 58 and interlayer resin insulation layer 150 formed with interlayer conduction hole 160 and conductor circuit 158 are disposed on the upper surface of conductor layer 34P. A solder resist layer 70 is formed on the interlayer via hole 160 and the conductor circuit 158 , and bumps 76U, 76D are formed on the interlayer via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70 .

As shown in FIG. 12 , the solder bumps 76U on the upper surface side of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90 . In addition, a chip capacitor 98 is installed. On the other hand, the lower solder bumps 76D are connected to the lands 96 of the sub-board 94 .

Here, the conductive circuit 34 on the core substrate 30, the conductive layers 34P, 34P, and the conductive layer 24 in the core substrate are formed, and the conductive circuit 58 on the interlayer resin insulating layer 50 and the conductive circuit on the interlayer resin insulating layer 150 are formed. 158. The thickness of the conductive layer 34P and the conductive layer 24 of the core substrate, that is, the thickness of the conductive layer of the core substrate is formed between 1 and 250 μm, and the thickness of the conductive layer that can function as a power supply layer formed on the core substrate is formed within 1 μm. ~250μm. The thickness of the conductor layer in this state is the sum of the thicknesses of the power supply layers of the core substrate. It shows the thickness obtained by adding both the conductor layer 34 which becomes an inner layer, and the conductor layer 24 which becomes a surface layer. Instead of adding a conductor layer that functions as a signal line. In this fourth embodiment, the same effect as that of the first embodiment is obtained by combining the thicknesses of the three conductor layers 34P, 34P, and 24 . The thickness of the power supply layer may exceed the above range.

In addition, in the fourth embodiment, 1<(the sum of the thicknesses of the conductor layers of the power supply layer of the core substrate/the thickness of the conductor layers of the interlayer insulating layer)≤40 is taken as a suitable example, and (the conductor of the power supply layer of the core substrate The total thickness of the layers/thickness of the conductor layer of the interlayer insulating layer) ≤ 1 was taken as a comparative example. Take (the sum of the thicknesses of the conductor layers of the power supply layer of the core substrate/the thickness of the conductor layers of the interlayer insulating layer)>40 as a reference example.

(fourth embodiment-1)

Although it is the same as the fourth embodiment described with reference to FIG. 11 , it is set as follows.

Thickness of conductor layer (power supply layer) of core substrate: 15 μm

Thickness of intermediate conductor layer (power supply layer): 20μm

Thickness of the power supply layer of the core substrate: 50 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(fourth embodiment-2)

Although it is the same as the fourth embodiment, it is manufactured as follows.

Thickness of conductor layer (power supply layer) of core substrate: 20 μm

Thickness of intermediate conductor layer (power supply layer): 20μm

Thickness of the power supply layer of the core substrate: 60 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(4th embodiment-3)

Although it is the same as the fourth embodiment, it is manufactured as follows.

Thickness of conductor layer (power supply layer) of core substrate: 25 μm

The thickness of the intermediate conductor layer (power supply layer): 25 μm

Thickness of the power supply layer of the core substrate: 75 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(4th embodiment-4)

Although it is the same as the fourth embodiment, it is manufactured as follows.

Thickness of conductor layer (power supply layer) of core substrate: 50 μm

Thickness of intermediate conductor layer (power supply layer): 100μm

The thickness of the power supply layer of the core substrate: 200μm

Thickness of the conductor layer of the interlayer insulating layer: 10 μm

(4th embodiment-5)

Although it is the same as the fourth embodiment, it is manufactured as follows.

Thickness of conductor layer (power supply layer) of core substrate: 55 μm

The thickness of the intermediate conductor layer (power supply layer): 250 μm

The sum of the thicknesses of the power supply layer of the core substrate: 360 μm

Thickness of the conductor layer of the interlayer insulating layer: 12 μm

(4th embodiment-6)

Although it is the same as the fourth embodiment, it is manufactured as follows.

Thickness of conductor layer (power supply layer) of core substrate: 55 μm

The thickness of the intermediate conductor layer (power supply layer): 250 μm

The sum of the thicknesses of the power supply layer of the core substrate: 360 μm

Thickness of the conductor layer of the interlayer insulating layer: 9 μm

[Fifth Embodiment] Multilayer Core Substrate

A multilayer printed wiring board according to a fifth embodiment of the present invention will be described with reference to FIGS. 13 to 18 .

First, the structure of the multilayer printed circuit board 10 of the fifth embodiment will be described with reference to FIGS. 17 and 18 . FIG. 17 is a cross-sectional view showing the multilayer printed circuit board 10 , and FIG. 18 shows a state in which the IC chip 90 is mounted on the multilayer printed circuit board 10 shown in FIG. 17 and mounted on the daughter board 94 . As shown in FIG. 17 , a multilayer core substrate 30 is used on the multilayer printed circuit board 10 . The conductive circuit 34 and the conductive layer 34P are formed on the front side of the multilayer core substrate 30 , and the conductive circuit 34 and the conductive layer 34E are formed on the back surface thereof. The upper conductor layer 34P is formed as a power supply plane layer, and the lower conductor layer 34E is formed as a ground plane layer. In addition, the conductive circuit 16 and the conductive layer 16E of the inner layer are formed on the front side inside the multilayer core substrate 30 , and the conductive circuit 16 and the conductive layer 16P are formed on the back surface thereof. The upper conductor layer 16E is formed as a ground plane layer, and the lower conductor layer 16P is formed as a power supply plane layer. The connection between the plane layers for the power supply is made by through holes or holes for interlayer conduction. The flat layer may be a single layer on only one side, or may be arranged in two or more layers. Preferably, it is formed in 2 to 4 layers. Since improvement in electrical characteristics was not confirmed with 5 or more layers, even if it is formed as a multilayer with 5 or more layers, the effect is equivalent to that of 4 layers. In particular, when formed in two layers, in terms of rigidity matching of the multilayer core substrate, the elongation rate of the substrate is made uniform, so that bending is less likely to occur. In addition, since the thickness of the core substrate can be reduced, the wiring length of the via hole can be shortened. The electrically insulating metal plate 12 is housed in the center of the multilayer core substrate 30 . (Although the metal plate 12 also functions as a core material, it is not electrically connected to a through hole or a hole for interlayer conduction. It mainly improves the rigidity against bending of the substrate.) The metal plate 12 is separated by insulating Resin layer 14 forms the conductor circuit 16 of inner layer, conductor layer 16E on its surface side, forms conductor circuit 16, conductor layer 16P on its back side, and, also interposes insulating resin layer 18, and forms conductor circuit 16 on its surface side. The circuit 34 and the conductive layer 34P are formed on the back surface of the conductive circuit 34 and the conductive layer 34E. The multilayer core substrate 30 realizes the connection between the inner layer and the front side and the back side through the through hole 36 .

On the conductor layers 34P, 34E on the surface of the multilayer core substrate 30, the interlayer resin insulating layer 50 formed with the interlayer conduction hole 60 and the conductor circuit 58 and the interlayer resin insulating layer 50 formed with the interlayer conduction hole 160 and the conductor circuit 158 are disposed. Interlaminar resin insulating layer 150 . The solder resist layer 70 is formed on the upper layer of the interlayer conduction hole 160 and the conductor circuit 158, and the bumps 76U and 76D are formed on the interlayer conduction hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. .

As shown in FIG. 18 , the solder bumps 76U on the upper surface side of the multilayer printed circuit board 10 are connected to the lands 92 of the IC chip 90 . In addition, a chip capacitor 98 is installed. On the other hand, the lower external terminal 76D is connected to the land 96 of the sub-board 94 . The external terminals in this case refer to PGA, BGA, solder bumps, and the like.

Here, the conductor layers 34P and 34E on the surface layer of the core substrate 30 are formed to have a thickness of 10 to 60 μm, the conductor layers 16P and 16E on the inner layer are formed to have a thickness of 10 to 250 μm, and the conductor circuits 58 and layers on the interlayer resin insulating layer 50 The conductive circuit 158 on the inter-resin insulating layer 150 is formed to have a thickness of 5 to 25 μm.

In the multilayer printed circuit board of the fifth embodiment, the power supply layer (conductor layer) 34P on the surface layer of the core substrate 30, the conductor layer 34, the power supply layer (conductor layer) 16P on the inner layer, the conductor layer 16E, and the metal plate 12 Thickened to increase the strength of the core substrate. Thereby, even if the core substrate itself is thinned, the substrate itself can relax warpage or stress generated therefrom.

In addition, the volume of the conductor itself can be increased by making the conductor layers 34P, 34E, and the conductor layers 16P, 16E thick. Increasing its volume reduces the resistance on the conductor.

In addition, by using the conductor layers 34P and 16P as power supply layers, the ability to supply power to the IC chip 90 can be improved. Therefore, it is possible to reduce the loop inductance from the IC chip to the substrate to the power supply when the IC chip is mounted on the multilayer printed circuit board. Thereby, the power shortage in the initial operation is reduced, and the power shortage is less likely to occur. Therefore, even if an IC chip in a high-frequency region is mounted, erroneous operation or error in the initial startup does not occur. In addition, by using the conductor layers 34E and 16E as ground layers, noise is not superimposed on the signal and power supply of the IC chip, and malfunctions and errors can be prevented. Since the power stored in the capacitor can be auxiliary used by installing the capacitor, it is difficult to cause a power shortage. In particular, the effect (difficult to cause power shortage) is remarkably improved by disposing it directly under the IC chip. The reason for this is that if it is directly under the IC chip, the wiring length on the multilayer printed wiring board can be shortened.

In the fifth embodiment, the multilayer core substrate 30 has thick conductor layers 16P, 16E on its inner layer and thin conductor layers 34P, 34E on its surface, and the conductor layers 16P, 16E on the inner layer and the conductor layer 34P on the surface , 34E is used as the conductor layer for the power supply layer and the conductor layer for grounding. That is, even if the thick conductor layers 16P, 16E are arranged on the inner layer side, a resin layer covering the conductor layers is formed. This makes it possible to make the surface of the multilayer core substrate 30 flat by offsetting unevenness due to the conductor layer. Therefore, even if thin conductor layers 34P, 34E are disposed on the surface of multilayer core substrate 30, the conductive layers 58, 158 of the interlayer insulating layers 50, 150 will not be undulated. , 16E to ensure a sufficient thickness as the core conductor layer. Since waviness does not occur, there is no problem in the impedance of the conductor layer on the interlayer insulating layer. By using the conductor layers 16P and 34P as the conductor layers for the power supply layer and the conductor layers 16E and 34E as the conductor layers for the ground, the electrical characteristics of the multilayer printed wiring board can be improved.

In addition, a microstrip structure can be formed by arranging the signal line 16 between the conductor layer 34P and the conductor layer 16P (on the same layer as the conductor layer 16E) in the core substrate. Similarly, by arranging the signal line 16 (on the same layer as the conductor layer 16P) between the conductor layer 16E and the conductor layer 34E, a microstrip structure can be formed. By adopting a microstrip structure, inductance can be reduced and impedance matching can be obtained. Therefore, electrical characteristics can be stabilized.

That is, the thickness of the conductor layers 16P, 16E on the inner layer of the core substrate is made greater than the thickness of the conductor layers 58 , 158 on the interlayer insulating layers 50 , 150 . Thus, even if the thin conductor layers 34E, 34P are arranged on the surface of the multilayer core substrate 30 , they can be added to the inner thick conductor layers 16P, 16E to ensure sufficient thickness as the core conductor layer. Its ratio is preferably 1<(conductor layer of core inner layer/conductor layer of interlayer insulating layer)≦40. More desirably, 1.2≤(conductor layer of core inner layer/conductor layer of interlayer insulating layer)≤30.

The multilayer core substrate 30 is formed in such a state that the inner conductor layers 16P, 16E are formed on both sides of the electrically insulating metal plate 12 with the resin layer 14 interposed therebetween, and the outer conductor layers 16P, 16E of the inner layer are further separated. The surface conductor layers 34P, 34E are formed in contact with the resin layer 18 . Sufficient mechanical strength can be ensured by arranging the electrically insulating metal plate 12 at the center. In addition, the inner conductor layers 16P, 16E are formed on both surfaces of the metal plate 12 via the resin layer 14, and the surface conductor layer 34P is formed outside the inner conductor layers 16P, 16E via the resin layer 18. , 34E, so that both sides of the metal plate 12 have symmetry, and prevent bending and undulation during thermal cycles and the like.

Fig. 19 shows a modified example of the fifth embodiment. In this modified example, the capacitor 98 is arranged directly under the IC chip 90 . Thereby, the distance between the IC chip 90 and the capacitor 98 is shortened, and the voltage drop of the power supply to the IC chip 90 can be prevented.

Next, a method of manufacturing the multilayer printed wiring board 10 shown in FIG. 17 will be described with reference to FIGS. 13 to 18 .

(1) <Formation process of metal layer>

An opening 12a penetrating the front and back is provided in the inner metal layer (metal plate) 12 having a thickness of 20 to 400 μm shown in FIG. 13(A) ( FIG. 13(B) ). In the fifth embodiment, a 20 μm metal plate is used. As the material of the metal layer, a material obtained by mixing metals such as copper, nickel, zinc, aluminum, and iron can be used. Here, when 36 alloy or 42 alloy with a low thermal expansion coefficient is used, since the thermal expansion coefficient of the core substrate can be made close to that of the IC, thermal stress can be reduced. The opening 12a is formed by perforation, etching, drilling, laser and the like. Depending on the situation, the entire surface of the metal layer 12 where the opening 12a is formed may be covered with the metal film 13 by electrolytic plating, electroless plating, displacement plating, sputtering, or the like (FIG. 13(C)). In addition, the metal plate 12 may be a single layer or a multilayer of two or more layers. In addition, the metal film 13 preferably forms a curved surface at the corner of the opening 12a. Thereby, the point of stress concentration can be eliminated, and problems such as cracks in the periphery thereof are less likely to occur. In addition, the metal plate 12 may not be built in the core substrate.

(2) <Formation process of inner insulating layer and conductive layer>

Insulating resin is used to cover the entire metal layer 12 and fill the opening 12a. As a forming method, for example, a B semi-cured resin film-like resin film with a thickness of about 30 to 200 μm is sandwiched between metal plates 12 (FIG. 13(D)), and a copper foil of 12 to 275 μm is laminated on the outside. , heat-pressed and cured to form the insulating resin layer 14 and the conductor layer 16 (FIG. 13(E)). Depending on the situation, coating, mixing of coating and film lamination, or coating of only the opening portion and then formation of the film may be performed.

As the material, it is preferable to use a prepreg made by impregnating thermosetting resins such as polyimide resins, epoxy resins, phenol resins, and BT resins into core materials such as glass fiber cloth and polyimide non-woven fabrics. Resin cloth. Other than these, resins can also be used. In the fifth example, a 50 μm prepreg cloth was used.

The method of forming the conductor layer 16 may be to form by electroplating or the like on a metal foil.

(3) <Circuit Formation Process of Inner Metal Layer>

It may be formed in two or more layers. The metal layer can be formed by an additive method.

The inner layer conductor layers 16, 16P, 16E are formed from the inner layer metal layer 16 through a bumping method, an etching process, etc. (FIG. 13(F)). At this time, the thickness of the inner conductor layer is formed to be 10 to 250 μm. However, the stated range can be exceeded. In addition, in the fifth embodiment, the thickness of the conductor layer for power supply in the inner layer is 25 μm. In this circuit forming process, in order to be able to evaluate the insulation reliability of the core substrate, a test pattern (pattern for evaluating the insulation resistance of the core substrate) for measuring the insulation resistance with conductor width/distance between conductors = 150 μm/150 μm is formed as a test pattern. zigzag pattern. At this time, as shown in FIG. 17 , when the power supply through hole 36PTH electrically connected to the IC power supply penetrates through the ground layer 16E of the inner layer circuit, there may be no wiring pattern extending from the power supply through hole. Hereinafter, such a through hole is referred to as a power supply through hole not having a dummy land. Similarly, the ground via hole 36ETH electrically connected to the IC ground does not have a wiring pattern extending from the ground via hole when penetrating through the power supply layer 16P of the inner layer circuit. Hereinafter, such a via hole is referred to as a ground via hole not having a dummy land. Also, merging the two simply calls it a via without a dummy land. With this configuration, the via hole pitch can be narrowed. In addition, mutual inductance is reduced due to the narrow pitch between the via hole and the inner layer circuit. Here, a cross section of the X3-X3 portion in a state where there is no through hole of the dummy land is shown in FIG. 38(A). For reference, the cross-section of the X3-X3 portion in the state with dummy lands is shown in FIG. 38(B). It is found that the pitch of the via hole or the distance between the via hole 36PTH and the ground layer 16E becomes narrow due to the via hole having no dummy land. In addition, it is also known that the formation area of the ground layer 16E is increased. Here, reference numeral 35 is a space for securing insulation between the through hole 36PTH and the ground layer 16E, and reference numeral 36L is a via land (dummy land).

(4) <Formation process of outer insulating layer and conductor layer>

Insulating resin is used to cover the entire inner conductor layers 16 , 16P, and 16E and to fill gaps between the circuits. As a forming method, on both sides of the substrate formed in the process up to (3), for example, a resin film in the form of a B semi-cured resin film with a thickness of about 30 to 400 μm ( FIG. 14(A) ) with a thickness of 10 to 275 μm The metal foils are laminated in the order of metal foils, and then cured by thermocompression bonding to form the outer insulating resin layer 18 of the core substrate and the outermost conductor layer 34α of the core substrate ( FIG. 14(B) ). Depending on the situation, coating, mixing of coating and film bonding, or coating of only the opening portion and then formation of a thin film may be performed. The surface can be flattened by applying pressure. In addition, a prepreg cloth in the form of a resin film in a B semi-cured state using glass fiber cloth or polyamide nonwoven fabric as a core material can be used. In the fifth example, a prepreg cloth with a thickness of 200 μm was used. As a method other than forming metal foils, single-sided copper-clad laminates are laminated. Two or more layers may be formed on the metal foil by electroplating or the like. The metal layer can be formed by an additive method.

(5) <Through hole formation process>

Through holes 36α for through holes having an opening diameter of 50 to 400 μm penetrating the front and back of the substrate are formed ( FIG. 14(C) ). As the forming method, it is formed by drilling, laser, or a combination of laser and drilling (laser is used to open the outermost insulating layer, and according to the situation, the opening opened by the laser is used as a target mark, Then, use a drill to open and penetrate.). Its shape preferably has straight side walls. Depending on the situation, it can be tapered.

In order to ensure the conductivity of the through hole, it is preferable to form a plated film 22 in the through hole 36α for the through hole, and after roughening the surface ( FIG. 14(D) ), fill it with a filling resin 23 ( FIG. 14(E)). As the filling resin, an electrically insulated resin material (such as a resin material containing a resin component, a curing agent, particles, etc.), an electrically conductive material electrically connected by metal particles (such as a metal particle containing gold, copper, etc., Conductive materials such as resin materials, curing agents, etc.) any of them. After filling, pre-drying is performed to remove excess filling resin adhering to the electrolytic copper plating film 22 on the surface of the substrate by grinding, and then drying is performed at 150° C. for 1 hour to be completely cured.

As the plating, electrolytic plating, electroless plating, panel plating (electroless plating and electrolytic plating) and the like can be used. The metal is formed by containing copper, nickel, cobalt, phosphorus, etc. The thickness of the plated metal is preferably 5 to 30 μm.

The filling resin 23 filled in the through hole 36α for the through hole is preferably an insulating material composed of a resin material, a curing agent, particles, and the like. The particles are inorganic particles such as silica and alumina, metal particles such as gold, silver, copper, and resin particles, and are blended alone or in combination. Particles having the same particle diameter or mixed particle diameters of 0.1 to 5 μm can be used. As the resin material, single resins such as epoxy resins (such as bisphenol-type epoxy resins, novolak-type epoxy resins, etc.), thermosetting resins such as phenolic resins, photosensitive UV-curable resins, and thermoplastic resins can be used. Or a resin material made by mixing them. As the curing agent, an imidazole-based curing agent, an amine-based curing agent, or the like can be used. In addition to this, a curing stabilizer, a reaction stabilizer, particles, and the like may also be contained. Conductive materials may also be used. In this case, what consists of metal particles, a resin component, a hardening|curing agent, etc. becomes a conductive paste of a conductive material. Depending on the case, a conductive material in which a conductive metal film is formed on a surface layer of an insulating material such as solder or insulating resin, or the like can be used. The inside of the through-hole 36α for through-hole may be filled by plating. As the conductive paste cures and shrinks, recesses are formed on the surface layer.

(6) <Formation process of the outermost conductor circuit>

Cover plating 25 can be formed directly above through hole 36 by coating the entirety with a plating film ( FIG. 15(A) ). Then, outer layer conductor circuits 34, 34P, 34E are formed through a bumping method, an etching process, etc. (FIG. 15(B)). Thus, the multilayer core substrate 30 is completed. In addition, in the fifth embodiment, the thickness of the conductor layer for power supply on the surface of the multilayer core substrate is 15 μm.

In this case, though not shown, electrical connection to the conductor layer 16 and the like in the inner layer of the multilayer core substrate can be made through interlayer conduction holes, blind through holes, or blind interlayer conduction holes.

(7) The multilayer core substrate 30 on which the conductive circuit 34 is formed is blackened and reduced to form a roughened surface 346 on the entire surface of the conductive circuit 34 and conductive layers 34P and 34E ( FIG. 15(C) ).

(8) A layer of the resin filler 40 is formed on the non-conductive circuit formation portion of the multilayer core substrate 30 ( FIG. 16(A) ).

(9) Grinding with a belt grinder or the like to grind one side of the substrate after the above-mentioned processing so that the resin filler 40 does not remain on the outer edge portions of the conductor layers 34P, 34E, and then, in order to remove the For the damage caused by the above-mentioned polishing, the entire surfaces of the conductor layers 34P, 34E (surfaces of the lands including the through-holes) are also polished with a polisher or the like. Such a series of polishing is similarly performed on the other surfaces of the substrate. Next, heat treatment was performed at 100° C. for 1 hour, and then at 150° C. for 1 hour to cure resin filler 40 ( FIG. 16(B) ), thereby completing a four-layer multilayer core substrate.

In addition, resin filling between conductor circuits may not be performed. In this case, the formation of the insulating layer and the filling between the conductor circuits are performed with a resin layer such as an interlayer insulating layer.

(10) On the above-mentioned multilayer core substrate 30, spray the etchant on both sides of the substrate to etch the conductive circuit 34, the surface of the conductive layer 34P, 34E and the land surface of the through hole 36 by etching etc. A roughened surface 368 is formed on the entire surface of (FIG. 16(C)). Subsequent steps are the same as those of the first embodiment described with reference to FIGS. 3 to 7 , and thus description thereof will be omitted. In addition, in FIG. 3(B), in order to evaluate the influence of the fluctuation of the interlayer insulating layer due to the conductor thickness of the multilayer core substrate on a part of the interlayer insulating layer (50), a plating resist is formed. (54) So that the wiring pattern after electroplating (minimum line space, line width formability evaluation pattern) becomes conductor width/space between conductors = 5/5 μm, 7.5/7.5 μm, 10/10 μm, 12.5/12.5 μm , 15/15μm. As for the thickness of the plating resist, a value between 10 and 30 μm is used.

In addition, in the fifth embodiment, 1<(thickness of the conductor layer for power supply of the core substrate and/thickness of the conductor layer of the interlayer insulating layer)≤40 is taken as a suitable example, and (the conductor layer for power supply of the core substrate Thickness and/thickness of the conductor layer of the interlayer insulating layer) ≤ 1 as a comparative example. The case where (the thickness of the conductor layer for power supply of the core substrate and/the thickness of the conductor layer of the interlayer insulating layer)>40 is taken as a reference example.

(fifth embodiment-1)

Although it is the same as the fifth embodiment described with reference to FIG. 17, it is set as follows.

Thickness of the conductor layer of the inner layer of the core substrate: 50 μm

The thickness of the conductor layer on the surface layer: 20μm

The sum of the thickness of the conductor circuit of the core substrate: 100μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

In FIG. 17, the conductor layers of the core substrate are alternately arranged with power supply layers and ground layers. However, in the fifth embodiment-1, the inner conductor layer and the surface conductor layer function as the power supply layer. However, since the area of the conductor layer on the surface is about the area of the land, it is smaller than the conductor layer on the inner layer, so the effect of restoring the power supply voltage is cancelled. Thus, the sum of the thicknesses of the conductor layers of the core substrate is the thickness obtained by adding the conductor layers of the two inner layers.

(fifth embodiment-2)

The conductor layer of the inner layer and the conductor layer of the surface layer play the role of the power supply layer. Electrical connections are made through through holes in each layer of the surface layer and the inner layer.

Thickness of the conductor layer of the inner layer of the core substrate: 60 μm

The thickness of the conductor layer of the outer layer: 20 μm

The sum of the thickness of the conductor circuit of the core substrate: 80 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

The conductor layer of the inner layer and the conductor layer of the surface layer function as a power supply layer of each layer. The area of the conductor layer of the surface layer is the same as the area of the conductor layer of the inner layer. Has the effect of restoring the power supply voltage. Accordingly, the sum of the thicknesses of the conductor layers of the core substrate is the thickness obtained by adding the conductor layers of the inner layer and the conductor layers of the surface layer.

(fifth embodiment-3)

The conductor layer of the inner layer and the conductor layer of the surface layer play the role of the power supply layer. Electrical connections are made through through holes in each layer of the surface layer and the inner layer.

Thickness of the conductor layer of the inner layer of the core substrate: 150 μm

The thickness of the conductor layer of the outer layer: 20 μm

The sum of the thickness of the conductor circuit of the core substrate: 150 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

The conductor layer of the inner layer and the conductor layer of the surface layer play the role of the power supply layer. However, since the area of the conductor layer on the surface is about the area of the land, it is smaller than the conductor layer on the inner layer, so the effect of restoring the power supply voltage is cancelled. Accordingly, the thickness of the conductor layer of the core substrate is equal to the thickness of the conductor layer of the inner layer 1.

(fifth embodiment-4)

Although it is the same as the fifth embodiment-1, it is manufactured as follows.

Thickness of the conductor layer (power supply layer) of the inner layer of the core substrate: 100 μm

The thickness of the conductor layer (power supply layer) on the surface layer: 20μm

The sum of the thickness of the conductor circuit of the core substrate: 200μm

Thickness of the conductor layer of the interlayer insulating layer: 10 μm

The sum of the thicknesses of the conductive circuits of the core substrate is obtained by adding the conductive layers of the inner layers.

(Fifth embodiment-5)

Although it is the same as the fifth embodiment-1, it is manufactured as follows.

The thickness of the conductor layer (power supply layer) of the inner layer of the core substrate: 120 μm

The thickness of the conductor layer (power supply layer) on the surface layer: 20μm

The sum of the thickness of the conductor circuit of the core substrate: 240μm

Thickness of the conductor layer of the interlayer insulating layer: 8 μm

The sum of the thicknesses of the conductive circuits of the core substrate is obtained by adding the conductive layers of the inner layers.

(Fifth embodiment-6)

Although it is the same as the fifth embodiment-2, it is manufactured as follows.

The thickness of the conductor layer (power supply layer) of the inner layer of the core substrate: 250 μm

The thickness of the conductor layer (power supply layer) on the surface layer: 50 μm

Thickness sum of conductor circuit of core substrate: 300μm

Thickness of the conductor layer of the interlayer insulating layer: 7.5 μm

[Sixth embodiment] Core substrate with built-in capacitor

A multilayer printed circuit board according to a sixth embodiment will be described with reference to FIGS. 20 and 21 .

In the multilayer printed circuit board of the sixth embodiment, the chip capacitor 20 is incorporated in the core substrate 30 .

FIG. 20 is a cross-sectional view showing a multilayer printed circuit board 10 according to the sixth embodiment, and FIG. 21 shows a state in which an IC chip 90 is mounted on the multilayer printed circuit board 10 shown in FIG. 20 . As shown in FIG. 20 , in the multilayer printed wiring board 10 , the core substrate 30 is composed of a resin substrate 30A and a resin layer 30B. An opening 31 a for accommodating the capacitor 20 is provided in the resin substrate 30A. The electrodes of the capacitor 20 are connected through the interlayer conduction holes 33 provided in the resin layer 30B. On the upper surface of the core substrate 30, a conductor circuit 34 and a conductor layer 34P for forming a power supply layer are formed. In addition, an interlayer resin insulating layer having interlayer conduction holes 60 and conductor circuits 58 is formed on both sides of the core substrate 30. Layer 50. Through holes 36 are formed in the core substrate 30 . A solder resist layer 70 is formed on the upper layer of the interlayer resin insulating layer 50 , and bumps 76U, 76D are formed on the interlayer conduction holes 60 and the conductor circuits 58 through the openings 71 of the solder resist layer 70 .

As shown in FIG. 21 , the solder bumps 76U on the upper surface side of the multilayer printed circuit board 10 are connected to the lands 92 of the IC chip 90 . In addition, a chip capacitor 98 is installed. On the other hand, conductive connection pins 99 for solder bump connection on the lower side are attached.

Here, the conductor layer 34E is formed to have a thickness of 30 μm. In the sixth embodiment, since the capacitor 20 is built in the core substrate 30, effects exceeding those of the first embodiment can be obtained.

(Sixth embodiment-1)

Although it is the same as the sixth embodiment described with reference to FIG. 20 , it is set as follows.

Conductor layer thickness of core substrate: 30 μm

Thickness of the power supply layer of the core substrate: 30 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(Sixth Embodiment-2)

Although it is the same as the sixth embodiment, it is set as follows.

Thickness of conductor layer of core substrate: 55 μm

Thickness of the power supply layer of the core substrate: 55 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(Sixth Embodiment-3)

The thickness of the conductor layer of the core substrate: 75 μm

Thickness of the power supply layer of the core substrate: 75 μm

Thickness of the conductor layer of the interlayer insulating layer: 15 μm

(Sixth Embodiment-4)

Although it is the same as the sixth embodiment-1, it is set as follows.

Thickness of conductor layer (power supply layer) of core substrate: 180 μm

Thickness of the conductor layer of the interlayer insulating layer: 6.0 μm

(comparative example)

In the first to fifth examples, (thickness of the conductor layer for power supply of the core substrate and/thickness of the conductor layer of the interlayer insulating layer)≦1 is defined as the first to fifth comparative examples. As an example, the thickness of the conductive layer for power supply of the core substrate: 15 μm, and the thickness of the conductive layer of the interlayer insulating layer: 15 μm.

(reference example)

In the first to fifth examples, those with (thickness of the conductor layer for power supply of the core substrate and/thickness of the conductor layer of the interlayer insulating layer)>40 are taken as the first to fifth reference examples. As an example, the sum of the thicknesses of the conductor layers for power supply of the core substrate: 415 μm, and the thickness of the conductor layers of the interlayer insulating layer: 10 μm.

IC chips with a frequency of 3.1 GHz were mounted on the substrates of the respective examples, comparative examples, and reference examples, and the same amount of power was supplied, and the amount of voltage drop at startup was measured. The drop value of the voltage at this time is displayed. This is the value of the amount of voltage drop that fluctuates when the power supply voltage is 1.0V. The voltage of the IC chip is carried out so that a circuit capable of measuring the voltage is formed on a printed circuit board.

In addition, a reliability test was performed under high-temperature and high-humidity conditions (temperature 130° C., humidity 85%, application of 2 V) in each of the Examples, Comparative Examples, and Reference Examples. The test time was 100 hr, 300 hr, 500 hr, and 1000 hr, and the presence or absence of malfunction of the IC and the presence or absence of open connection of the core conductor layer were verified for each of the examples and comparative examples. The results are shown in graphs in FIGS. 25 and 26 . In addition, when the power supply voltage is 1.0V, if the variation allowable range is ±10% (the third voltage drop amount), the behavior of the voltage is stable and does not cause malfunction of the IC chip or the like. That is, in this case, if the amount of the voltage drop is 0.1 V or less, malfunction of the IC chip or the like due to the voltage drop does not occur.

From Fig. 25 and Fig. 26, it can be seen that the multilayer printed circuit board produced by the suitable example is less prone to malfunction or opening of the IC chip. That is, electrical connectivity and reliability can be ensured.

In the comparative example, a problem with the electrical connectivity occurred due to malfunction of the IC chip, and as a result, the stress generated under the reliability test could not be buffered due to the thinning of the conductor, and peeling occurred at the conductive connection portion. . Therefore, reliability is lowered. However, this effect occurs when the ratio of the thickness of the power supply layer of the core substrate to the thickness of the conductor layer of the interlayer insulating layer exceeds 1.2.

When the ratio of the thickness of the power supply layer of the core substrate to the thickness of the conductor layer of the interlayer insulating layer exceeds 40 (reference example), due to problems on the conductor circuit of the upper layer (for example, stress to the conductor circuit of the upper layer occurs or The reduction of close contact caused by fluctuations, etc.), therefore, the reliability is reduced.

According to the test results, the factors satisfying the electrical characteristics and reliability are 1<(the thickness of the conductor layer of the core substrate and/the thickness of the conductor layer of the interlayer insulating layer)≤40.

25 and 26 do not show the results of the first examples -6 to 10, but they are the same as the first examples -1 to 5.

[Seventh embodiment]

FIG. 27 shows a cross-sectional view of a multilayer printed circuit board of a seventh embodiment. In the seventh embodiment, in FIG. When, by changing the etching conditions such as injection pressure, etching time, etc., or in the injection etching device, only use the lower surface to etch, so that the side surfaces of the conductor layers 16E, 16P become linear tapered or R surface tapered, adjust The angle Θ formed between the straight line connecting the upper end and the lower end of the side surface of the conductor layer and the core substrate (refer to FIG. Conical shape, Fig. 27(C): R-plane conical shape) are the following 7th embodiment-1 to 7th embodiment-9. In addition, the Θ and the shape (linear taper or R-plane taper) of each cross-section of the seventh embodiment-1 to the seventh embodiment-6 are ground so that the longitudinal section of the inner layer conductor can be observed, and are marked with × 100 to × 1000 microscope to observe the actual measurement value of the cross-section.

[Seventh Embodiment-1]

Adjust tanΘ by 2, and adjust the shape to an R-face-like cone.

[Seventh Embodiment-2]

Adjust tanΘ to 2.8, and adjust the shape to an R-face-like cone.

[Seventh Embodiment-3]

Adjust tanΘ to 3.5, and adjust the shape to an R-face-like cone.

[Seventh Embodiment-4]

Adjust tanΘ to 53, and adjust the shape to an R-face-like cone.

[Embodiment 7-5]

Adjust tanΘ to 55, and adjust the shape to an R-face-like cone.

[Seventh Embodiment-6]

Adjust tanΘ to 53, and adjust the shape to an R-face-like cone.

[Seventh Embodiment-7]

Adjust tanΘ to 2.8, and adjust the shape to a linear cone.

[Embodiment 7-8]

Adjust the tanΘ to 57, and the shape to a linear cone.

[Embodiment 7-9]

Adjust the tanΘ to 57, and the shape to a linear cone.

Next, with respect to the multilayer printed wiring boards of the seventh example-1 to the seventh example-6, a HAST test and a thermal cycle test were performed for a time (number of times) under the following conditions. For the multilayer printed circuit boards of the seventh embodiment - 7, 8, and 9, only thermal cycle tests were performed. The results are shown in the graph in FIG. 28 . In addition, FIG. 29 shows a graph in which tanΘ is plotted on the horizontal axis and changes in insulation resistance and resistivity are plotted on the vertical axis.

Conditions and time of HAST test

Condition: 85℃×85%×3.3V

Time: 115hr

^If the insulation resistance after the test is 10 ⁷ Ω or more, it is acceptable.

thermal cycle test

Condition: -55℃×5 minutes 125℃×5 minutes

Times: 1000 times

The change of resistivity after the test is ±10% or within ±10% is qualified. In addition, the measurement is the same as that of the eighth example described later.

From the results in Fig. 28 and Fig. 29, it can be seen that when Θ satisfies the relational expression of 2.8<tanΘ<55, the insulation reliability and connection reliability are satisfied at the same time.

The multilayer printed circuit board of Example 7-1 after the HAST test and the multilayer printed circuit board of Example 7-6 after the heat cycle test were analyzed.

In Example 7-6, it was found that resistance increased due to cracks starting from the interface between the side wall of the conductor layer of the inner layer of the multilayer core substrate and the insulating resin, or interface peeling.

In Example 7-1, it was found that the insulation resistance was lowered due to etching residual copper scattered between the conductor layers (on the insulating layer) of the conductor layer of the inner layer of the multilayer core substrate and the conductor layer of the base. Furthermore, when Θ satisfies 2.8<tanΘ<55, insulation reliability or connection reliability is improved.

In addition, through the 7th embodiment-2, 4, 6 of FIG. 28 (FIG. 27(C): R plane taper) and the 7th embodiment-7 to the 7th embodiment-9 (FIG. 27(B): A comparison between the linear tapered shape and the straight tapered shape shows that, regarding the shape of the side surface of the conductor layer, the connection reliability of the R surface tapered shape is better than that of the linear tapered shape. This is presumed to be because the R-plane shape increases the adhesion strength between the side surface of the conductor layer and the insulating resin, and disperses the stress, making cracking or peeling less likely to occur.

[Eighth embodiment]

The eighth embodiment is based on the fifth embodiment. In FIG. 13(F), the circuit formation of the inner layer conductor layers 16E, 16P of the core substrate is performed as follows. Cuprous chloride is sprayed and sprayed with the etching solution on the substrate conveyed to the etching area by the conveyor through nozzles (installed up and down at a certain distance from the substrate). Change the etching method or etching conditions, or add an inhibitor to the main component, and adjust the tapered shape or the angle of the side surface of the conductor layer as in the following Eighth Example-1 to Eighth Example-30. In addition, Θ and its shape (straight taper or R-plane taper) of the eighth embodiment-1 to the eighth embodiment-30 are ground for observation of the longitudinal section of the inner layer conductor, and are measured by ×100～ The actual measured value of cross-section observation was carried out with a graduated microscope of ×1000. In addition, the cross-sectional observation was performed using a substrate for observation of the side shape of the conductor layer produced under the same conditions other than the product. As for the number of measurements, one product was divided into 4 parts, and 2 points were randomly measured for each part (a total of 8 pieces of data).

In addition, in each embodiment, only the thickness of the copper foil is changed to change the thickness of the inner layer conductor layer in FIG. 13(E) when manufacturing the multilayer core.

The above-mentioned inhibitor is an additive that is adsorbed on copper to suppress etching in the horizontal direction between copper and the substrate (side etching), and can increase the above-mentioned Θ. Such an inhibitor includes benzotriazole and the like, and the degree of inhibition of side etching can be controlled by changing its concentration. In order to add benzotriazole at a high concentration, it is possible to add a surfactant (amphoteric surfactant: alkyldimethylaminoacetic acid betaine and nonionic surfactant: polyoxyethylene alkyl ether) at the same time, The side surface of the conductor layer becomes a shape closer to vertical.

"Eighth Embodiment-1"

Thickness of inner conductor layer: 30μm

Conductor thickness of 34, 34P, 34E in FIG. 15(B): 20 μm.

Addition of inhibitors to etchant

Inhibitors: not added

etching method

Nozzles used: Full cone nozzles (nozzles that spray radially)

The shaking (shaking) of the nozzle: Existence

Nozzle used: Below only

In the eighth embodiment-1, the etchant without additives is sprayed radially with a full conical nozzle in the state of shaking the head, so that the side surface of the conductor layer becomes an R-plane tapered shape, and tan Θ is 1.6 to 2.5 (8 the minimum value to the maximum value in the data).

"Eighth Embodiment-2"

In the eighth embodiment-1, the thickness of the inner layer conductor was changed from 30 µm to 45 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 1.4 to 2.1 (minimum value to maximum value among 8 data)

"Eighth Embodiment-3"

In the eighth embodiment-1, the thickness of the inner layer conductor was changed from 30 µm to 60 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 1.4 to 2.1 (minimum value to maximum value among 8 data)

"Eighth Embodiment-4"

In the eighth embodiment-1, the thickness of the inner layer conductor was changed from 30 µm to 100 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 1.3 to 1.9 (minimum value to maximum value among 8 data)

"Eighth Embodiment-5"

In the eighth embodiment-1, the thickness of the inner layer conductor was changed from 30 μm to 125 μm, so that the thickness of the prepreg in FIG. 14(A) was 225 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 1.3 to 1.9 (minimum value to maximum value among 8 data)

"Eighth Embodiment-6"

In the eighth embodiment-1, the thickness of the inner layer conductor was changed from 30 μm to 150 μm, so that the thickness of the prepreg in FIG. 14(A) was 250 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 1.2 to 1.7 (minimum value to maximum value among 8 data)

"Eighth Embodiment-7"

Thickness of inner conductor layer: 30μm

Conductor thickness of 34, 34P, 34E in FIG. 15(B): 20 μm.

Addition of inhibitors to etchant

Inhibitor: add benzotriazole (BTA) 1200ppm, surfactant 450ppm.

etching method

Nozzles used: Slit nozzles (nozzles that spray in a straight line)

Shaking (shaking) of the nozzle: None

Nozzle used: top only

In the eighth embodiment-7, the inhibitor is added to the etchant and sprayed linearly through the slit nozzle, so its tanΘ is larger than that in the eighth embodiment-1 to the eighth embodiment-6.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.0 to 10.8 (minimum value to maximum value among 8 data)

"Eighth Embodiment-8"

In the eighth embodiment-7, the thickness of the inner layer conductor was changed from 30 µm to 45 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.0 to 11.0 (minimum value to maximum value among 8 data)

"Eighth Embodiment-9"

In the eighth embodiment-7, the thickness of the inner layer conductor was changed from 30 µm to 60 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.0 to 11.2 (minimum value to maximum value among 8 data)

"Eighth Embodiment-10"

In the eighth embodiment-7, the thickness of the inner layer conductor was changed from 30 µm to 100 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 2.8 to 11.2 (minimum value to maximum value among 8 data)

"Eighth Embodiment-11"

In the eighth embodiment-7, the thickness of the inner layer conductor was changed from 30 μm to 125 μm, so that the thickness of the prepreg in FIG. 14(A) was 225 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 2.7 to 11.0 (minimum value to maximum value among 8 data)

"Eighth Embodiment-12"

In the eighth embodiment-7, the thickness of the inner layer conductor was changed from 30 μm to 150 μm, so that the thickness of the prepreg in FIG. 14(A) was 250 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 2.7 to 11.4 (minimum value to maximum value among 8 data)

"Eighth Embodiment-13"

Thickness of inner conductor layer: 30μm

Conductor thickness of 34, 34P, 34E in FIG. 15(B): 20 μm.

Addition of inhibitors to etchant

Inhibitor: 1000 ppm of benzotriazole (BTA) and 450 ppm of surfactant were added.

etching method

Nozzle to use: Slit nozzle (nozzle spraying spray linearly)

Shaking (shaking) of the nozzle: None

Nozzle used: Below only

In the eighth embodiment-13, the amount of inhibitor added to the etching solution is less than that of the eighth embodiment-7, and only the lower slit nozzle is used for spraying. Therefore, when compared with the eighth embodiment-7 , tanΘ is equal to the following values but its range becomes smaller.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.0 to 5.3 (minimum value to maximum value among 8 data)

"Eighth Embodiment-14"

In Embodiment 8-13, the thickness of the inner layer conductor was changed from 30 µm to 45 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.1 to 5.4 (minimum value to maximum value among 8 data)

"Eighth Embodiment-15"

In Embodiment 8-13, the thickness of the inner layer conductor was changed from 30 µm to 60 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.1 to 5.4 (minimum value to maximum value among 8 data)

"Eighth Embodiment-16"

In Embodiment 8-13, the thickness of the inner layer conductor was changed from 30 µm to 100 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 2.7 to 5.5 (minimum value to maximum value among 8 data)

"Eighth Embodiment-17"

In Example 8-13, the thickness of the inner layer conductor was changed from 30 μm to 125 μm, so that the thickness of the prepreg in FIG. 14(A) was 225 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 2.9 to 5.7 (minimum value to maximum value among 8 data)

"Eighth Embodiment-18"

In Example 8-13, the thickness of the inner layer conductor was changed from 30 μm to 150 μm, so that the thickness of the prepreg in FIG. 14(A) became 250 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 2.75.7 (minimum value to maximum value among 8 data)

"Eighth Embodiment-19"

In the eighth embodiment-7, etching is performed using only the lower slit nozzle. As a result, the range of tanΘ becomes smaller compared to the eighth embodiment-7.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 4.2 to 10.8 (minimum value to maximum value among 8 data)

"Eighth Embodiment-20"

In Embodiment 8-19, the thickness of the inner layer conductor was changed from 30 µm to 45 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 4.0 to 11.0 (minimum value to maximum value among 8 data)

"Eighth Embodiment-21"

In Embodiment 8-19, the thickness of the inner layer conductor was changed from 30 µm to 60 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.8 to 11.0 (minimum value to maximum value among 8 data)

"Eighth Embodiment-22"

In Embodiment 8-19, the thickness of the inner layer conductor was changed from 30 µm to 100 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.7 to 11.2 (minimum value to maximum value among 8 data)

"Eighth Embodiment-23"

In Example 8-19, the thickness of the inner layer conductor was changed from 30 μm to 125 μm, so that the thickness of the prepreg in FIG. 14(A) was 225 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.7 to 11.4 (minimum value to maximum value among 8 data)

"Eighth Embodiment-24"

In Example 8-19, the thickness of the inner layer conductor was changed from 30 μm to 150 μm, so that the thickness of the prepreg in FIG. 14(A) became 250 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Conical shape: R surface

tanΘ: 3.7 to 11.3 (minimum value to maximum value among 8 data)

"Eighth Embodiment-25"

In Example 8-19, the concentration of benzotriazole was made 1800 ppm. As a result, the side surface of the conductor layer is tapered linearly.

Measurement results of the side shape and Θ of the conductor layer

Tapered shape: straight

tanΘ: 4.0 to 10.8 (minimum value to maximum value among 8 data)

"Eighth Embodiment-26"

In Embodiment 8-25, the thickness of the inner layer conductor was changed from 30 µm to 45 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Tapered shape: straight

tanΘ: 4.0 to 10.8 (minimum value to maximum value among 8 data)

"Eighth Embodiment-27"

In the eighth embodiment-25, the thickness of the inner layer conductor was changed from 30 µm to 60 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Tapered shape: straight

tanΘ: 4.0 to 11.0 (minimum value to maximum value among 8 data)

"Eighth Embodiment-28"

In the eighth embodiment-25, the thickness of the inner layer conductor was changed from 30 µm to 100 µm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Tapered shape: straight

tanΘ: 3.7 to 11.2 (minimum value to maximum value among 8 data)

"Eighth Embodiment-29"

In Example 8-25, the thickness of the inner layer conductor was changed from 30 μm to 125 μm, so that the thickness of the prepreg in FIG. 14(A) was 225 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Tapered shape: straight

tanΘ: 3.8 to 11.4 (minimum value to maximum value among 8 data)

"Eighth Embodiment-30"

In Example 8-25, the thickness of the inner layer conductor was changed from 30 μm to 150 μm, so that the thickness of the prepreg in FIG. 14(A) was 250 μm. Otherwise the same.

Measurement results of the side shape and Θ of the conductor layer

Tapered shape: straight

tanΘ: 3.7 to 11.4 (minimum value to maximum value among 8 data)

(8th comparative example-1)

In the eighth comparative example-1, the thickness of the copper foil in FIG. 13(E) was 7.5 μm, and the thickness of the conductors 34, 34P, and 34E in FIG. 15(B) was 7.5 μm. That is, the thickness of the conductor layer for power supply of the core substrate is equal to the thickness of the conductor circuit 58 on the interlayer insulating layer.

(8th comparative example-2)

In the eighth comparative example-7, the thickness of the copper foil in FIG. 13(E) was 7.5 μm, and the thickness of the conductors 34, 34P, and 34E in FIG. 15(B) was 7.5 μm. That is, the thickness of the conductor layer for power supply of the core substrate is equal to the thickness of the conductor circuit 58 on the interlayer insulating layer.

(8th comparative example-3)

In Comparative Example 8-13, the thickness of the copper foil in FIG. 13(E) was 7.5 μm, and the thickness of the conductors 34, 34P, and 34E in FIG. 15(B) was 7.5 μm. That is, the thickness of the conductor layer for power supply of the core substrate is equal to the thickness of the conductor circuit 58 on the interlayer insulating layer.

(8th comparative example-4)

In Comparative Example 8-19, the thickness of the copper foil in FIG. 13(E) was 7.5 μm, and the thickness of the conductors 34, 34P, and 34E in FIG. 15(B) was 7.5 μm. That is, the thickness of the conductor layer for power supply of the core substrate is equal to the thickness of the conductor circuit 58 on the interlayer insulating layer.

The tapered shape and tanΘ of the multilayer printed circuit boards of the eighth example and the eighth comparative example are shown in FIG. 30 . In addition, it was confirmed whether or not the IC chips mounted on the multilayer printed circuit boards of the eighth example and the eighth comparative example malfunctioned by the method described below.

As the IC chip, any IC chip selected from the following Nos. 1 to 4 was mounted on each multilayer printed circuit board, and the simultaneous switching was performed 100 times, and the presence or absence of malfunction was evaluated.

The results of each multilayer printed circuit board and simultaneous switching test are shown in FIG. 30 .

No.1: Drive frequency: 3.06GHz, bus frequency (FS B): 533MHz

No.2: Drive frequency: 3.2GHz, bus frequency (FS B): 800MHz

No.3: Drive Frequency: 3.4GHz, Bus Frequency (FSB): 800MHz

No.4: Drive frequency: 3.46GHz, bus frequency (FSB): 1066MHz

In addition, the same heat cycle test as that of the seventh example was performed 1000 times and 2000 times on the multilayer printed wiring boards of the eighth examples 19-30 on which ICs were mounted, and the connection resistance was evaluated. The connection resistance was measured by measuring the connection resistance of a closed circuit connected from the measurement terminal 1 on the back surface of the multilayer printed wiring board to the measurement terminal 2 on the back surface of the multilayer printed wiring board through the IC. If (connection resistance after heat cycle−connection resistance of initial value)/connection resistance of initial value×100 was within ±10%, it was rated as ○, and otherwise as ×.

From the results of mounting the No. 1 IC chip, it was found that according to the multilayer printed circuit board of the present invention, no malfunction occurred. In addition, from the comparison of the eighth embodiment-1 and the eighth embodiment-7, 13, 19, and 25 on which No. 2 IC chips are mounted, it is known that if the thickness of the conductor layer on the core substrate is greater than If the thickness of the conductive circuit and the value of tanΘ≥2.7, it is not easy to malfunction. In the eighth embodiment-1, since the conductor volume of the conductor layer of the inner layer is small, the resistance of the power supply layer becomes high, so it is presumed that a delay occurs in the supply of power supply and a malfunction occurs. In addition, according to the multilayer printed circuit board on which the No. 3 IC chip is mounted, if the thickness of the inner layer conductor layer is 60 to 100 μm, no malfunction occurs. However, in the eighth embodiment-1 where the value of tanΘ is small , 2, and tanΘ have large ranges in the eighth embodiment-11, 12, erroneous operation occurs. It is presumed that the erroneous operation in Embodiments 8-11 and 12 is due to the fact that the impedance of the signal via-hole penetrating the multilayer core varies greatly among the via-holes, resulting in a difference in signal arrival. When comparing the multilayer printed circuit boards of No. 4 IC chips mounted on No. 8 Examples - 19 to 24 and Eighth Examples - 25 to 30, it is found that when the tapered shape is the R surface, it is less likely to occur. wrong action. This is presumed to be because when the side surface of the inner conductor layer is linear, the sensed impedance difference (see Fig. 31) of the signal via hole becomes larger than that of the R-side multilayer printed circuit board. The reflection becomes more, or it is due to the influence of the tight junction between the side of the conductor layer and the insulating layer.

In addition, it is known from the eighth embodiment-13-24 that when tanΘ is 2.7-5.7 or 3.7-11.4, the thickness of the inner layer conductor is preferably 45-150 μm.

Place the multilayer printed circuit boards of the eighth embodiment-14～18, 20～24 under high temperature and high humidity (85 degrees 85%) for 100 hours, after installing No.4 IC chip, perform simultaneous switching . In the eighth examples-15-18, 21-24 in which the thickness of the inner conductor layer was 60-150 μm, no malfunction occurred, but in the eighth examples-14, 20, malfunction was observed. This is presumed to be due to an increase in the resistance value of the conductor due to the high temperature and high humidity test. From this result, it is found that ta nΘ is 2.7 to 5.7 or 3.7 to 11.4, and the thickness of the inner layer conductor is more preferably 60 to 150 μm.

"Ninth embodiment"

The multilayer printed wiring boards of the ninth example-1 to the ninth example-28 and the ninth comparative example-1 to the ninth comparative example-3 were produced according to the fifth example. However, in each of the Examples and Comparative Examples, the thickness of the conductor layer of the core substrate, the number of layers of the conductor layer of the core substrate, the number of via holes without dummy lands, the area without dummy lands, and the interlayer thickness were changed. The thickness of a conductor layer over an insulating layer. When changing the thickness of the conductor layer of the inner layer, in FIG. 13(E), the thickness of the copper foil is changed. When the thickness of the conductor layer on the front and back of the core substrate is changed, the copper foil thickness in FIG. 14(B) and the plating thickness in FIG. 14(D) and FIG. 15(A) are changed. When changing the number of conductor layers of the core substrate, after the step of FIG. 14B , circuit formation, roughening of the circuit surface, and lamination of prepreg and copper foil are repeated a predetermined number of times. When changing the number of via holes without dummy lands or the area without dummy lands, when forming (adding) the circuit in FIG. mask. When changing the thickness of the conductor layer on the interlayer insulating layer, it is performed by changing the plating thickness in FIG. 3(C).

In the following, the number of core layers, the thickness of the conductor layer for power supply, the thickness of the conductor layer on the interlayer insulating layer, the number of via holes without dummy lands and their areas, etc. are shown in the respective examples and comparative examples.

(Ninth embodiment-1)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 25 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 40 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Ninth embodiment-2)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 15 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 9 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 24 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Ninth embodiment-3)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 45 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 60 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Ninth embodiment-4)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 60 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 75 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Ninth embodiment-5)

Thickness of conductor layer for power supply in each inner layer of 14-layer core substrate: 100 μm

The thickness of the conductor layer for power supply on the surface layer of the 14-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 615 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Ninth embodiment-6)

The thickness of the conductor layer for power supply in each inner layer of the 18-layer core substrate: 100 μm

The thickness of the conductor layer for power supply on the surface layer of the 18-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 815 μm

Thickness of the conductor layer on the interlayer insulating layer: 20 μm

(Ninth embodiment-7)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 15 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 45 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 60 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Ninth embodiment-8)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 15 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 60 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 75 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Ninth embodiment-9)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 50 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 65 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Embodiment 9-10)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 150 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 165 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

In addition, in the step (4) <formation of outer layer insulating layer and conductor layer> of the above-mentioned fifth embodiment, a prepreg cloth with a thickness of 300 μm was used.

(Embodiments 9-11)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 175 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 190 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

In addition, in the step (4) <formation of outer layer insulating layer and conductor layer> of the above-mentioned fifth embodiment, a prepreg cloth with a thickness of 300 μm was used.

(Embodiment 9-12)

Thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 200 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 215 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

In addition, in the step (4) <formation of outer layer insulating layer and conductor layer> of the above-mentioned fifth embodiment, a prepreg cloth with a thickness of 300 μm was used.

(Embodiment 9-13)

In the ninth embodiment-3, a part of the through holes for power supply and the through holes for grounding are made without the dummy connections shown in (5) <Circuit Formation Process of Inner Metal Layer> in the above-mentioned fifth embodiment plate through holes. This area is directly below the IC, and the number of via holes for power supply without dummy lands is 50% of the total via holes for power supply, and the number of via holes for ground without dummy lands is 50% of the total via holes for ground. 50%.

(Embodiment 9-14)

In the ninth embodiment-3, all the through-holes for power supply and all the through-holes for grounding directly under the IC are made to be as shown in (5) <Circuit formation process of the inner layer metal layer> in the above-mentioned fifth embodiment. of vias that do not have dummy lands.

(9th embodiment-15)

In the ninth embodiment-9, a part of the through holes for power supply and the through holes for grounding are made without the dummy connection shown in (5) <Circuit formation process of inner layer metal layer> in the above-mentioned fifth embodiment. plate through holes. This area is directly below the IC, and the number of via holes for power supply without dummy lands is 50% of the total via holes for power supply, and the number of via holes for ground without dummy lands is 50% of the total via holes for ground. .

(9th embodiment-16)

In the ninth embodiment-9, all the through-holes for power supply and all the through-holes for grounding directly under the IC are made as in (5) <Circuit Formation Process of Inner Metal Layer> in the above-mentioned fifth embodiment. vias without dummy lands are shown.

(9th embodiment-17)

In the ninth embodiment-4, a part of the through holes for power supply and the through holes for grounding are made without the dummy connection shown in (5) <Circuit formation process of the inner layer metal layer> in the above-mentioned fifth embodiment. plate through holes. This area is directly below the IC, and the number of via holes for power supply without dummy lands is 50% of the total via holes for power supply, and the number of via holes for ground without dummy lands is 50% of the total via holes for ground. .

(9th embodiment-18)

In the ninth embodiment-4, all the through-holes for power supply and all the through-holes for grounding directly under the IC are made as shown in (5) <Circuit formation process of the inner layer metal layer> in the above-mentioned fifth embodiment. of vias that do not have dummy lands.

(9th embodiment-19)

In Embodiment 9-10, some of the through holes for power supply and the through holes for ground are made without the dummy connection shown in (5) <Circuit Formation Process of Inner Metal Layer> in the fifth embodiment above. plate through holes. This area is directly below the IC, and the number of via holes for power supply without dummy lands is 50% of all via holes for power supply, and the number of via holes for ground without dummy lands is 50% of the via holes for full ground. .

(9th embodiment-20)

In Embodiment 9-10, all the through holes for power supply and all the through holes for ground directly under the IC are made as shown in (5) <Circuit Formation Process of Inner Metal Layer> in the above-mentioned fifth embodiment. of vias that do not have dummy lands.

(9th embodiment-21)

In the ninth embodiment to the eleventh embodiment, a part of the through hole for power supply and the through hole for ground are made without the dummy connection shown in (5) <Circuit formation process of inner layer metal layer> in the fifth embodiment above. plate through holes. This area is directly below the IC, and the number of via holes for power supply without dummy lands is 50% of the total via holes for power supply, and the number of via holes for ground without dummy lands is 50% of the total via holes for ground. .

(9th embodiment-22)

In Embodiment 9-11, all the through holes for power supply and all the through holes for ground directly under the IC are made as shown in (5) <Circuit Formation Process of Inner Metal Layer> in the above-mentioned fifth embodiment. of vias that do not have dummy lands.

(9th embodiment-23)

In Embodiment 9-12, some of the through holes for power supply and the through holes for ground are made without the dummy connections shown in (5) <Circuit Formation Process of Inner Metal Layer> in the fifth embodiment above. plate through holes. This area is directly below the IC, and the number of via holes for power supply without dummy lands is 50% of the total via holes for power supply, and the number of via holes for ground without dummy lands is 50% of the total via holes for ground. .

(9th embodiment-24)

In Embodiment 9-12, all the through holes for power supply and all the through holes for ground directly under the IC are made as shown in (5) <Circuit Formation Process of Inner Metal Layer> in the above-mentioned fifth embodiment. of vias that do not have dummy lands.

(9th embodiment-25)

In the ninth embodiment-7, a part of the through holes for power supply and the through holes for grounding are made without the dummy connection shown in (5) <Circuit Formation Process of Inner Metal Layer> in the fifth embodiment above. plate through holes. This area is directly under the IC, and the number of via holes for power supply without dummy lands is 50% of the total via holes for power supply, and the number of via holes for ground without dummy lands is 50% of the total via holes for ground. %.

(9th embodiment-26)

In the ninth embodiment-7, all the through-holes for power supply and all the through-holes for grounding directly under the IC are made as shown in (5) <Circuit formation process of the inner layer metal layer> in the above-mentioned fifth embodiment. of vias that do not have dummy lands.

(9th embodiment-27)

Thickness of conductor layer for power supply in each inner layer of 6-layer core substrate: 32.5 μm

The thickness of the conductor layer for power supply on the surface layer of the 6-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 80 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(Ninth embodiment-28)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 125 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 140 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(9th comparative example-1)

The thickness of the conductor layer for power supply in the inner layer of the 4-layer core substrate: 10 μm

The thickness of the conductor layer for power supply on the surface layer of the 4-layer core substrate: 10 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 20 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(9th comparative example-2)

The thickness of the conductor layer for power supply in each inner layer of the 18-layer core substrate: 100 μm

The thickness of the conductor layer for power supply on the surface layer of the 18-layer core substrate: 40 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 840 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

(9th comparative example-3)

The thickness of the conductor layer for power supply in each inner layer of the 22-layer core substrate: 100 μm

The thickness of the conductor layer for power supply on the surface layer of the 22-layer core substrate: 15 μm

The sum of the thicknesses of the conductor layers for power supply of the core substrate: 1015 μm

Thickness of conductor layer on interlayer insulating layer: 20 μm

In addition, in the multilayer printed wiring boards of the ninth example and the ninth comparative example, there is no description about the dummy lands, but all the through holes have dummy lands.

On the multilayer printed circuit boards of the 9th comparative example-1 to the 9th comparative example-12, the 9th embodiment-27, 28 and the 9th comparative example-1 to the 9th comparative example-3, the frequency 3.1GHz The IC chip was supplied with the same amount of power, and the amount of voltage drop at the time of startup was measured (corresponding to the third drop amount among the voltage drops that occurred multiple times). In addition, since the IC voltage cannot be directly measured on the IC, a measurable circuit is formed on a printed circuit board to measure the IC voltage. The value of the amount of voltage drop at this time is shown in FIGS. 32 and 33 , and is a value of the amount of voltage drop that fluctuates when the power supply voltage is 1.0V.

In addition, the HAST test (85°C, humidity 85° C. %, apply 3.3V). In addition, the pattern to be evaluated is a test pattern for evaluating insulation resistance formed on the core substrate. The results are shown in FIG. 32 . The test time is 115 hrs. After 115 hours, the insulation resistance value ≥ 10 ⁷ Ω is considered acceptable, and the value less than 10 ⁷ Ω is considered unfavorable.

In addition, in the ninth embodiment-3, 4, 7, and 8, the evaluation of the minimum line space and line width forming ability evaluation pattern (refer to (10) process of the fifth embodiment) is performed in the production of the printed circuit board. The results are shown in FIG. 34 as forming ability. In the figure, ○ indicates that there is no short circuit, and × indicates that there is a short circuit in the adjacent wiring.

The results of the amount of voltage drop and the insulation resistance after HAST for various α1/α2 are shown in FIGS. 32 and 33 . The results after the HAST test are described as ○ for pass and × for failure. In addition, FIG. 35 shows graphically the voltage drop amounts for various α1/α2.

In the results of Fig. 32 and Fig. 33, when the power supply voltage is 1.0V, if the variation allowable range is ±10% (the third voltage drop), the behavior of the voltage is stable and does not cause malfunction of the IC chip. That is, in this case, if the amount of voltage drop≦0.1V, malfunction of the IC chip or the like due to the voltage drop does not occur. Thus, stability is increased if the voltage drop is < 0.09V. Therefore, the ratio (thickness of the conductor layer for power supply of the multilayer core substrate/thickness of the conductor layer on the interlayer insulating layer) may exceed 1.0. Also, if the range of 1.2≦(thickness of the conductor layer for power supply of the multilayer core substrate and/the thickness of the conductor layer on the interlayer insulating layer)≦40, it is within the range of variation tolerance.

However, when this value exceeds 8.25, it starts to increase, and when it exceeds 40, the amount of voltage drop exceeds 0.1V. This is presumed to be due to the increase in the conductor layer of the multilayer core substrate or the increase in the number of inner layers, resulting in a longer via hole length, which takes time to supply power to the IC.

However, even if (the thickness of the conductor layer for power supply of the multilayer core substrate and/or the thickness of the conductor layer on the interlayer insulating layer) is within the above-mentioned range, the ninth embodiments-11 and 12 in which only one conductor layer is thickened, The insulation reliability of the core substrate is also poorer than that of other examples and is defective (see FIG. 32 ). From this, it can be seen that not only one layer is thickened, but also by multi-layering the core so that the sum of the thicknesses of the conductor layers for power supply falls within the above range, even if a high-frequency IC is mounted, it is possible to obtain an insulated A printed circuit board with good reliability.

In addition, when analyzing the test patterns for evaluating the insulation properties of the core substrates of the ninth examples-11 and 12, the intervals between the lines were narrowed. It is presumed that the insulation resistance is lower than the specification because of this. In addition, it is also known from the comparison of the ninth embodiment-3, 4 and the ninth embodiment-7, 8 in Fig. 34 that the thickness of the conductor layers on the front and back surfaces of the multilayer core substrate is preferably thicker than that of the conductor layers on the inner layer. Thin. This is because when the thick conductor layers are formed on the front and back surfaces, the interlayer agent becomes undulated under the influence of the conductor layer, and fine wiring cannot be formed on the interlayer insulating layer.

For the multilayer printed circuit board manufactured according to the ninth embodiment-1～12, 27, 28, and the ninth comparative example-1～3, it is confirmed whether there is an error on the mounted IC chip by the method described below action.

As the IC chip, any IC chip selected from the following Nos. 1 to 3 was mounted on each multilayer printed circuit board, and the simultaneous switching was performed 100 times, and the presence or absence of malfunction was evaluated.

These results are shown in FIG. 33 .

No.1: Drive frequency: 3.06GHz, bus frequency (FSB): 533MHz

No.2: Drive frequency: 3.2GHz, bus frequency (FSB): 800MHz

No.3: Drive frequency: 3.46GHz, bus frequency (FSB): 1066MHz

From the results of mounting the No. 1 IC chip, it was found that if the ratio of 1.0<α1/α2≦40, no malfunction was observed in the IC. This is presumably because the power supply to the IC is instantaneously supplied because the conductor resistance of the power supply layer is low. As a result of mounting the No. 2 IC chip, it was found that when the driving frequency of the IC becomes higher, the IC needs to be supplied with power in a shorter period of time, so there is a more appropriate range. The reason why the malfunction occurs in the ninth embodiment-11, 12 in which the conductor layer of the inner layer of the multilayer core is thicker or in the ninth embodiment-5, 6 in which the number of inner layers is increased is presumed to be that the In addition to the time required for power supply due to thickening of the core substrate, deterioration may occur when signals are transmitted to signal via holes (via holes to which IC signal circuits are electrically connected). In the state where the signal via hole penetrates the 4-layer core, the via hole penetrates the insulating layer (the insulating layer between the power supply layer of the surface layer and the ground layer of the inner layer in FIG. 18 ), the ground layer, and the insulating layer ( The insulating layer between the ground layer of the inner layer and the power layer of the inner layer in FIG. Signal wiring changes impedance depending on the surrounding ground or the presence or absence of a power supply. Therefore, for example, the impedance value varies with the boundary between the insulating layer between the power supply layer and the ground layer on the surface and the interface between the ground layers. Therefore, a reflection of the signal occurs on this interface. The same phenomenon occurs even in other interfaces. It is speculated that the change in impedance is that as the distance between the signal via hole and the ground layer and power layer gets closer, the thickness of the ground layer and power layer becomes thicker, and the number of interfaces increases, and becomes larger. , In the ninth embodiment-5, 6, 11, 12, erroneous actions occurred. In addition, it is presumed that in the ninth embodiment-1, 2, it is due to the thickness and smallness of the power supply layer.

In addition, as a result of mounting IC No. 3, it was found that a four-layer core with α1/α2 of 3 to 7 is effective when the speed of the IC is further increased. This is presumably because it is possible to simultaneously supply power in a short time and prevent signal deterioration. In addition, it is found from the comparison of the ninth embodiment-3, 4 and the ninth embodiment-7, 8 that it is also advantageous to arrange a thick conductor layer in the inner layer from the electrical point of view. This is presumed to be due to the fact that the inner layer has a thick conductor layer, so the inductance is reduced due to the interaction between the power supply via hole and the inner layer ground layer, and between the ground via hole and the inner layer power supply layer.

For the multilayer printed circuit boards manufactured in accordance with the ninth embodiment-13 to 26, it was confirmed whether or not there was any malfunction of the IC chip mounted thereon by the method described below.

For the IC chip, any one of the IC chips selected from the following No. 1 to No. 3 was mounted on each multilayer printed circuit board, and the simultaneous switching was performed 100 times, and the presence or absence of malfunction was evaluated.

These results are shown in Figure 36. TH used in the drawings is an abbreviation for through hole.

No.1: Drive frequency: 3.06GHz, bus frequency (FSB): 533MHz

No.2: Drive frequency: 3.2GHz, bus frequency (FSB): 800MHz

No.3: Drive frequency: 3.46GHz, bus frequency (FSB): 1066MHz

Comparing the ninth embodiment-10 with the ninth embodiments-19 and 20, it is found that the malfunction of the IC is less likely to occur due to the via holes having no dummy lands. It is presumed that the mutual inductance is reduced because the portion without the dummy land, the through-hole having the opposite potential, and the conductor layer of the inner layer are close to each other. Or it is presumed that this is because the current easily flows on the surface of the conductor, so there is no part of the dummy land, and the length of the wiring where the current flows is shortened.

The printed circuit boards of the ninth embodiment - 3, 4, 13, 14, 17, 18, 28 were placed in an environment of high temperature and high humidity (85 degrees and 85%) for 100 hours. Then, mount the above-mentioned No. 3 IC chip on each printed circuit board, perform simultaneous switching, and check whether there is any malfunction. Except for the ninth embodiment-3, there is no erroneous operation. It is presumed that the resistance of the conductor layer increased due to the high-temperature/high-humidity test, and therefore malfunction occurred in the ninth example-3. It is presumed that the other embodiments are the same, and the resistance increases. However, compared with the ninth embodiment-3, the thickness of the conductor layer in other embodiments is thicker, or the through hole does not have a dummy land, so its inductance is lower than that of the ninth embodiment. 9 Inductance of Example-3, so malfunction does not occur. Therefore, it is considered that the thickness of the conductor layer of the inner layer is preferably 60 μm to 125 μm. From the above, it can be inferred that in the case of a multilayer core, the thickness of the conductor having no inner layer and the via hole of the dummy land affect each other.

(the tenth embodiment)

In the eighth embodiment - multilayer printed circuit boards of 14 to 18, 20 to 24, in the process of Fig. 13(F), the through hole for power supply and the through hole for ground directly under the IC are made to have no dummy connection plate through holes. The numbers are both produced at two levels of 50% and 100% with respect to all through-holes for power supply and all through-holes for grounding. Let these be 10th Example-1-20. The printed circuit boards of the tenth embodiment-1 to 20 were left at high temperature and high humidity (85 degrees and 85%) for 100 hours. Then, the No. 4 IC chip used in the evaluation test of the eighth embodiment was mounted, and simultaneous switching was performed. The results are shown in FIG. 37 . From this result, it was found that by making the via hole not have the dummy land, the side wall of the conductor layer is tapered, and the result becomes more favorable.

Furthermore, in Examples 7 to 10, the conductor thickness of the inner ground layer is the same as the conductor thickness of the inner power layer, and the conductor thickness of the ground layer on the back surface of the core substrate is the same as that of the surface power layer. Therefore, the conductor thickness of the ground layer is the same as that of the power layer, so noise can be reduced and malfunctions are less likely to occur.

Explanation of the reference signs in the drawings

12: Metal layer (metal plate)

14: resin layer

16: conductor circuit

16P: conductor layer

16E: conductor layer

18: resin layer

30: Substrate

32: copper foil

34: conductor circuit

34P: conductor layer

34E: conductor layer

36: Through hole

40: resin filled layer

50: interlayer resin insulation layer

58: conductor circuit

60: Holes for interlayer conduction

70: Solder resist layer

71: opening

76U, 76D: Solder bumps

90: IC chip

94: daughter board

98: chip capacitor

Claims (11)

1. A multilayer printed circuit board, an interlayer insulating layer and a conductor layer are formed on a core substrate, and are electrically connected through an interlayer conduction hole, characterized in that, The core substrate is a multilayer core substrate with three or more layers having conductor layers on the front and back and a thick conductor layer on the inner layer; At least one of the inner conductor layer of the core substrate and the front and back conductor layers is a conductor layer for a power supply layer or a conductor layer for grounding; The side surfaces of the inner conductive layer of the core substrate and the side surfaces of the front and rear conductive layers are tapered, and an angle formed by a straight line connecting the upper and lower ends of the side surfaces of the inner conductive layer and the horizontal plane of the core substrate is set. is θ1, the angle formed by the straight line connecting the upper end and lower end of the side surface of the conductor layer on the front and back and the horizontal plane of the core substrate is θ2, and the θ1 and θ2 satisfy 2.8<tanθ1<55, 2.8<tanθ2<55 and The relational expression of θ1<θ2. 2. The multilayer printed circuit board according to claim 1, wherein the thickness of the conductor layer of the inner layer of the core substrate is greater than the thickness of the conductor layer on the interlayer insulating layer. 3. The multilayer printed circuit board according to claim 1 or 2, wherein the inner layer of the core substrate has two or more conductive layers. 4. The multilayer printed circuit board according to claim 1 or 2, wherein the core substrate is constructed such that the conductor layer of the inner layer is formed on both sides of an electrically insulating metal plate via a resin layer. , and the front and back conductor layers are formed on the outer side of the conductor layer of the inner layer via a resin layer. 5. The multilayer printed circuit board according to claim 1 or 2, wherein the core substrate has a thick conductor layer on an inner layer and a thin conductor layer on a surface layer. 6. The multilayer printed circuit board according to claim 1 or 2, wherein each conductor layer of the inner layer of the core substrate is any one of a conductor layer for power supply and a conductor layer for grounding. layer. 7. The multilayer printed circuit board according to claim 1 or 2, wherein the conductor layer on the surface of the core substrate is a conductor layer for a power supply or a conductor layer for grounding, and the conductor layer on the back is a conductor layer for a power supply. Conductor layer or conductor layer for grounding. 8. The multilayer printed circuit board according to claim 1 or 2, wherein the conductor layers for power supply and the conductor layers for ground are alternately arranged. 9. The multilayer printed circuit board according to claim 1 or 2, wherein the thickness of the conductor layer for power supply on the surface layer of the core substrate is added to the thickness of the conductor layer for power supply on the inner layer to obtain When the thickness of α1 is α1, and the thickness of the conductor layer on the interlayer insulating layer is α2, α1 and α2 are α2<α1≤40α2. 10. The multilayer printed circuit board according to claim 1 or 2, wherein the thickness of the conductor layer for grounding on the surface layer of the core substrate is added to the thickness of the conductor layer for grounding on the inner layer to obtain The thickness of α1 is α1, the thickness of the conductor layer on the interlayer insulating layer is α2, α1 and α2 are α2<α1≤40α2. 11. The multilayer printed circuit board according to claim 1 or 2, wherein the thickness of the conductor layer for power supply on the surface layer of the core substrate is added to the thickness of the conductor layer for power supply on the inner layer to obtain When the thickness of α1 is α1, and the thickness of the conductor layer on the interlayer insulating layer is α2, α1 and α2 are α2<α1≤40α2; When the thickness of the conductor layer for grounding on the surface layer of the core substrate and the thickness of the conductor layer for grounding on the inner layer are added to be α3, and the thickness of the conductor layer on the interlayer insulating layer is α2, α2 and α3 are α2<α3≦40α2.