CN101521567B - Sampling method and its data recovery circuit - Google Patents

Abstract

A sampling method and a data recovery circuit thereof. The sampling method includes the following steps that firstly, a first clock, a second clock, a third clock and a fourth clock are provided, the second clock lags behind the first clock by a first preset phase, the third clock and the fourth clock respectively lag behind the first clock and a second preset phase of the second clock, and the second preset phase is half of the first preset phase. Then, the digital signals are sampled by using the first clock and the second clock respectively. Then, the position of the data transition point of the digital signal is judged according to the sampling results of the first clock and the second clock. And then, selecting the third clock or the fourth clock as a preferred sampling clock according to the judgment result. The digital signal is then sampled using the preferred sampling clock.

Description

Sampling method and its data recovery circuit

technical field

The invention relates to a sampling method and a data recovery circuit thereof, and in particular to a sampling method capable of improving the correctness of data sampling and a data recovery circuit thereof.

Background technique

In the high-speed serial link system, it is often caused by the drift of the semiconductor process or the inconsistency of the chip layout, or because of the length difference of the internal metal wire (wire-interconnect), temperature change, intermediate devices (intermediate devices) ) changes, capacitive coupling, metal imperfections (material imperfections), and the input capacitance difference between the clock and the signal channel... and other factors, resulting in the clock received by the receiving end (in the related field of the present invention, the clock's English is strobe) and the data are out of sync or gap (skew).

Figure 1 is a timing diagram of the clock and digital signals received at the receiving end. As shown in Figure 1, when the clock CLK1 received by the receiver is synchronized with the clock CLK2 of its phase locked loop (PLL), the falling edge (falling edge) of the clock CLK2 will be used to update the received digital signal DATA Take a sample. Ideally, the data transition point of the digital signal DATA is aligned with the rising edge of the clock CLK2. In this way, the falling edge of the clock CLK2 will perform data sampling at the middle point of each bit (that is, the best data sampling point, as shown by mark 102 ), so as to ensure that correct data is obtained.

However, when the digital signal DATA is behind or ahead of the clock CLK2, there will be a gap, as shown in FIG. 2 . FIG. 2 is another timing diagram of clock and data received at the receiving end. The gap 202 is generated when the data transition point of the digital signal DATA is not aligned with the rising edge of the clock CLK2. If the gap 202 is too large, the falling edge of the clock CLK2 just falls near the data transition point of the digital signal DATA (as indicated by the mark 204 ), and it is easy to sample wrong data.

In order to avoid sampling wrong data, US Patent No. 5905769 proposes an over sampling (over sampling) technology, as shown in FIG. 3 . FIG. 3 is a timing diagram of sampling clocks and digital signals of the over-sampling technique. In this figure, marks 24-1-24-12 all represent the rising edge (rising edge) or falling edge of the sampling clock, and these edges can be called sampling edges, and marks 28-1-28-4 represent digital Among the four bits of the signal DATA, the values of the bits 28-1-28-4 are 1, 0, 1 and 0, respectively. As for the marks S[0]-S[11], they represent the sampling results at different times, and the number above each sampling result represents its sampling value. From this figure it can be seen that the sampling frequency has been increased so that each bit can be sampled three times. Taking the previous three sampling results S[0]-S[2] as an example, since the sampling values of these three sampling results are all 1, it can be determined that the value of the first bit (ie bit 28-1) is 1.

Sampling with such a sampling technique can still sample correct data when the digital signal is not synchronized with the sampling clock, as shown in Figure 4. FIG. 4 is another timing diagram of the sampling clock and the digital signal of the over-sampling technique. Please refer to Fig. 4, take the previous three sampling results S[0]-S[2] as an example, because there are two sampling values of 1 among the sampling values of these three sampling results, and only one sampling value is 0, so It can also be determined that the value of the first bit (ie, bit 28-1) is 1. In other words, as long as two sampled values are the same among the three sampled values, the same value is used as the value of the sampled bit.

However, even if this oversampling technique can improve the accuracy of data sampling, if the gap between the digital signal and the sampling clock is too large, so that the sampling edge falls on the data transition point, the sampled data can be judged by this method. If the value of the bit is changed, a judgment error will occur.

Contents of the invention

The purpose of the present invention is to provide a sampling method, which can improve the accuracy of data sampling.

Another object of the present invention is to provide a data recovery circuit, which uses the sampling method of the present invention to improve the accuracy of data sampling.

Based on the above and other purposes, the present invention proposes a sampling method. The steps of the sampling method include: first, providing the first clock, the second clock, the third clock and the fourth clock, each clock has the same frequency, and the second The clock is behind the first clock by a first preset phase, and the third clock and the fourth clock are respectively behind the first clock and the second clock by a second preset phase, and the second preset phase is half of the first preset phase. Then, use the first clock and the second clock to sample the digital signal respectively, and use the rising edge or falling edge of the first clock and the second clock as the sampling edge, wherein the bit length of the digital signal is the same as that of the first clock and the second clock , clock periods of the third clock and the fourth clock are equal. Then, the position of the data transition point of the digital signal is judged according to the sampling results of the first clock and the second clock. Next, the third clock or the fourth clock is selected as a better sampling clock according to the judgment result. Then, the digital signal is sampled using a preferred sampling clock, wherein the sampling edge of the preferred sampling clock is the same as the sampling edge of the first clock.

Based on the above and other objectives, the present invention proposes a data recovery circuit, which includes an oversampling module, a time reset module and a gap control module. The oversampling module is used to receive the first clock, the second clock, the third clock and the fourth clock, each clock has the same frequency, and the second clock lags behind the first clock by the first preset phase, and the third clock and the fourth clock The clock lags behind the first clock and the second clock by a second preset phase respectively, and the second preset phase is half of the first preset phase. During the first period, the over-sampling module uses the first clock and the second clock to sample the digital signal, and takes the rising edge or falling edge of the first clock and the second clock as the sampling edge. During the second period, the over-sampling module uses the third clock and the fourth clock to sample the digital signal, and the sampling edges of the third clock and the fourth clock are the same as the sampling edges of the first clock. In addition, the over-sampling module converts the sampling result into parallel data as an output of the over-sampling module, and the bit length of the above-mentioned digital signal is equal to the clock period of the above-mentioned four clocks. The time reset module is used for synchronizing the parallel data output by the oversampling module to generate a synchronization result. In the first period, the gap control module judges the position of the data transition point of the digital signal according to the synchronization result, so as to select the third clock or the fourth clock as a better sampling clock according to the judgment result, and in the second period, the gap control module The module controls the time reset module, so that the time reset module selects the synchronous parallel data obtained by the better sampling clock from the synchronization results as the output of the data recovery circuit.

Based on the above and other objectives, the present invention proposes another data recovery circuit, which includes an oversampling module, a time reset module and a gap control module. The oversampling module receives the first clock, the second clock, the third clock, the fourth clock, the fifth clock, the sixth clock, the seventh clock and the eighth clock, each clock has the same frequency, and the second clock lags behind the first The first preset phase of the clock, the third clock and the fourth clock are respectively behind the first clock and the second preset phase of the second clock, and the fifth clock, the sixth clock, the seventh clock and the eighth clock are respectively behind the first clock , the third preset phase of the second clock, the third clock and the fourth clock, and the second preset phase is half of the first preset phase, and the third preset phase is half of the second preset phase. During the first period, the over-sampling module uses the first clock and the second clock to sample the digital signal, and takes the rising edge or falling edge of the first clock and the second clock as the sampling edge. During the second period, the over-sampling module uses the third clock and the fourth clock to sample the digital signal, and the sampling edges of the third clock and the fourth clock are the same as the sampling edges of the first clock. During the third period, the over-sampling module uses the fifth clock and the sixth clock to sample the digital signal, or uses the seventh clock and the eighth clock to sample the digital signal. Wherein, the sampling edges of the fifth clock, the sixth clock, the seventh clock and the eighth clock are the same as the sampling edges of the first clock. In addition, the over-sampling module converts the sampling result into parallel data as an output of the over-sampling module, and the bit length of the above-mentioned digital signal is equal to the clock period of the above-mentioned eight clocks. The time reset module is used for synchronizing the parallel data output by the oversampling module to generate a synchronization result. During the first period, the gap control module judges the position of the data transition point of the digital signal according to the synchronization result, so as to select the third clock or the fourth clock as a better sampling clock according to the judgment result. During the second period, the gap control module judges the position of the data transition point of the digital signal according to the synchronization result, and selects one of the two clocks with a third preset phase difference from the better sampling clock as the best according to the judgment result. sampling clock. During the third period, the gap control module controls the oversampling module to select the best sampling clock and the clock with the first preset phase difference from the best sampling clock to sample, and controls the time reset module to make the time reset module synchronize from As a result, the synchronous parallel data obtained by the optimal sampling clock is selected as the output of the data recovery circuit.

According to an embodiment of the present invention, it also includes controlling the delay time of the digital signal according to the position of the data transition point of the digital signal, so that the middle point of the bit of the digital signal is adjusted to a better (/best) The sampling edge of the sampling clock, or the sampling edge of the better (/best) sampling clock where the midpoint of the bit of the digital signal approaches.

The present invention provides four sampling clocks with the same frequency but with different phase delays, and the second clock lags behind the first clock by the first preset phase, while the third clock and the fourth clock lag behind the first clock and the second clock respectively. The second preset phase of the second clock is half of the first preset phase. Next, use the first clock and the second clock to judge the data transition point position of the digital signal, and select the clock whose sampling edge is closer to the middle point of the digital signal from the third clock and the fourth clock as a better sample clock, to use a better sampling clock to sample digital signals, thereby improving the accuracy of data sampling. Even, the present invention can also be combined with the technique of adjusting the delay time of the digital signal, so that the middle point of the bit of the digital signal is adjusted to the sampling edge of the better sampling clock, or the middle point of the bit of the digital signal approaches the better The sampling edge of the sampling clock to further improve the accuracy of data sampling.

Based on the above and other purposes, the present invention also proposes a sampling method, including: providing a first clock, a second clock, a third clock and a fourth clock, each clock has the same frequency, and the second clock lagging behind the first clock by a first preset phase, and the third clock and the fourth clock lagging behind the first clock and the second clock by a second preset phase respectively, and the second preset phase is the first clock Half of a preset phase; use the first clock and the second clock to sample a digital signal respectively, and use the rising edge or falling edge of the first clock and the second clock as the sampling edge, wherein the digital signal The bit length is equal to the clock period of the first clock, the second clock, the third clock and the fourth clock; judge the data transition point of the digital signal according to the sampling results of the first clock and the second clock position; select the third clock or the fourth clock as a better sampling clock according to the judgment result; control the delay time of the digital signal according to the position of the data transition point of the digital signal, so that the digital the midpoint of the bit of the signal is adjusted to the sampling edge of the preferred sampling clock, or the midpoint of the bit of the digital signal is brought closer to the sampling edge of the preferred sampling clock; and the digital signal is sampled using the preferred sampling clock , wherein the sampling edge of the preferred sampling clock is the same as the sampling edge of the first clock.

Based on the above and other purposes, the present invention also proposes a data recovery circuit, including: an oversampling module, receiving a first clock, a second clock, a third clock and a fourth clock, and the frequency of each clock is the same , and the second clock is behind the first clock by a first preset phase, and the third clock and the fourth clock are behind the first clock and the second clock by a second preset phase, and the second The preset phase is half of the first preset phase. In a first period, the oversampling module uses the first clock and the second clock to sample a digital signal, and both use the first clock and the second clock to sample a digital signal. The rising edge or falling edge of the clock is used as the sampling edge. In a second period, the oversampling module uses the third clock and the fourth clock to sample the digital signal, and the sampling edge of the third clock and the fourth clock Same as the sampling edge of the first clock, the oversampling module converts the sampling result into parallel data as the output of the oversampling module, wherein the bit length of the digital signal is equal to the clock period of the above four clocks; A time reset module, used to synchronize the parallel data output by the oversampling module to generate a synchronization result; a gap control module, in the first period, the gap control module judges the data of the digital signal according to the synchronization result The position of the transition point, to select the third clock or the fourth clock as a better sampling clock according to the judgment result, and in the second period, the gap control module controls the time reset module to make the time reset a setting module selects synchronous parallel data obtained by the better sampling clock from the synchronization result as the output of the data recovery circuit; and a variable delay module through which the oversampling module receives the digital signal, the variable delay module controls the delay time of the digital signal according to a first control signal, and in the second period, the gap control module further generates according to the position of the data transition point of the digital signal the first control signal.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with accompanying drawings.

Description of drawings

Figure 1 is a timing diagram of the clock and digital signals received at the receiving end.

FIG. 2 is another timing diagram of clock and data received at the receiving end.

FIG. 3 is a timing diagram of sampling clocks and digital signals of the over-sampling technique.

FIG. 4 is another timing diagram of the sampling clock and the digital signal of the over-sampling technique.

Figure 5(a)-Figure 5(c), Figure 6(a)-Figure 6(c), Figure 7(a)-Figure 7(b), Figure 8(a)-Figure 8(c), Figure 9( a)-FIG. 9(c) and FIG. 10(a)-FIG. 10(b) are explanatory diagrams of the sampling method according to the present invention.

FIG. 11 is a flow chart of one preferred operation of the sampling system of the present invention.

FIG. 12 , FIG. 13 , FIG. 15 and FIG. 16 are block diagrams of one of the data recovery circuits adopting the sampling method of the present invention.

FIG. 14 is a circuit block diagram of one implementation of the variable delay module 1240 .

FIG. 17 is a flowchart of a sampling method according to an embodiment of the present invention.

Explanation of symbols in drawings

24-1-24-12: Sampling Edge

28-1-28-4: bits

102, 204: mark

202: Gap

1102-1112, 1702-1710: Steps

1210, 1510: Oversampling module

1212, 1214, 1414, 1426, 1512, 1514: Multiplexers

1216, 1516: Oversampling circuit

1220, 1520: Time reset module

1230, 1530: gap control module

1240, 1540: variable delay module

1410: First stage delay control circuit

1420: Second stage delay control circuit

1411-1413, 1421-1425: delay unit

A, B, C, D, A', B', C', D', CLK1, CLK2: Clock

CS1, CS2: Control signal

DATA: digital signal

DS: Output of variable delay block

OS: output of the oversampling circuit

OUT: the output of the data recovery circuit

S[0]-S[11]: sampling result

SL: select signal

TS: Sync results.

Detailed ways

Fig. 5(a) is an explanatory diagram of a sampling method according to the present invention. Please refer to Fig. 5 (a), for convenience of explanation, the mark A in the figure, B, C and D represent as four frequency identical, but have the clock of different phase delay (in the relevant field of the present invention, the English of clock is strobe), and the same mark indicates the same clock. As for the arrows next to the marks A, B, C, and D, they represent the sampling edges of the clock. Take the arrows next to the two marks A in the figure as an example. These two arrows represent the sampling edges of two adjacent pulses of the clock A. .

Among these four clocks, clock B lags behind clock A by the first preset phase, while clock C and clock D lag behind clock A and clock B by the second preset phase, and the second preset phase is the first preset phase half of. In this example, the first preset phase is set to be 180°, so the second preset phase is 90°. It can be seen from the figure that clock A, clock B, clock C and clock D all use rising or falling edges as sampling edges. In addition, the mark DATA is represented as a digital signal, the data of which is transmitted in a serial manner, and the bit length of the digital signal DATA is equal to the clock periods of the above four clocks.

Please continue to refer to FIG. 5( a ), firstly, the digital signal DATA is sampled by clock A and clock B respectively. Next, the position of the data transition point of the digital signal DATA is judged according to the sampling results of the clock A and the clock B. The method of judging the position of the data transition point can be described by the following two formulas:

(A[0]XOR B[0])+(A[1]XOR B[1])+(A[2]XOR B[2])+…+(A[M-1]XOR B[M- 1])

...(Formula 1)

(B[0]XOR A[1])+(B[1]XOR A[2])+(B[2]XOR A[3])+…+(B[M-1]XOR A[M] )

...(Formula 2)

Formula 1 is used to determine whether the position of the data transition point is located after the sampling edge of clock A and before the sampling edge of clock B, and formula 2 is used to determine whether the position of the data transition point is located after the sampling edge of clock B and before the sampling edge of clock A.

In Equation 1 and Equation 2, A[0]-A[M] means that clock A has (M+1) sampling results in total, and B[0]-B[M] means that clock B has (M+1) total sampling results. sampling results, wherein M is a positive integer, and the purpose of sampling multiple samples is to ensure that the sampling results are correct. As for XOR, it means that the sampling results of clock A and clock B are subjected to an exclusive-OR (exclusive-OR) operation. When judging the position of the data transition point, it is necessary to use the methods described in formula 1 and formula 2 to judge. If the value obtained by formula 1 is non-zero and the value obtained by formula 2 is zero, it can be judged that the position of the data transition point is located after the sampling edge of clock A and before the sampling edge of clock B, that is, the data transition point The state point is between A[0] and B[0], between A[1] and B[1], and so on. Conversely, if the value obtained by Equation 1 is zero and the value obtained by Equation 2 is non-zero, it can be judged that the position of the data transition point is located after the sampling edge of clock B and before the sampling edge of clock A, that is, the data The transition point is between B[0] and A[1], between B[1] and A[2], and so on.

Next, clock C or clock D can be selected as a better sampling clock according to the judgment result. In this example, since the position of the data transition point is located after the sampling edge of clock A and before the sampling edge of clock B, and just in the middle of the sampling edges of clock A and clock B, the sampling edge of clock D It is located at the middle point of the bit of the digital signal DATA (that is, the best data sampling point), so the clock D can be selected as the better sampling clock, and the clock D can be used for data sampling to ensure that the correct data is obtained. Of course, in a more rigorous system, the steps of using clock A and clock B to determine the position of the data transition point will be repeated several times to avoid misjudging the position of the data transition point.

The example shown in Figure 5(a) is an ideal situation, so that the sampling edge of the clock D is just at the middle point of the bit of the digital signal DATA, but in a non-ideal situation, the better selected according to the judgment result The sampling edge of the sampling clock is still near the middle point of the bit of the digital signal DATA, as shown in FIG. 5(b) and FIG. 5(c). Fig. 5(b) and Fig. 5(c) are another explanatory diagrams of the sampling method according to the present invention. Please refer to Figure 5(b) first. It can be clearly seen from this figure that the position of the data transition point of the digital signal DATA is also located after the sampling edge of clock A and before the sampling edge of clock B, but it is closer to the sampling edge of clock A. Therefore, among the sampling edges of the clock C and the clock D, the sampling edge of the clock D is closer to the middle point of the bit of the digital signal DATA, so it is ideal to select the clock D for sampling. Please refer to Figure 5(c) again, it can be clearly seen from this figure that the position of the data transition point of the digital signal DATA is also located after the sampling edge of clock A and before the sampling edge of clock B, but it is closer to the sampling edge of clock B , so it is ideal to choose the clock D for sampling.

The above-mentioned examples in Figure 5(a)-Figure 5(c) all take the data transition point position after the sampling edge of clock A and before the sampling edge of clock B as an example, so clock D is selected as the best sampling clock, but if it is judged that the position of the data transition point is located after the sampling edge of clock B and before the sampling edge of clock A, it is ideal to select clock C as a better sampling clock, from Figure 6(a)-Figure 6( c) can be understood as shown. Fig. 6(a)-Fig. 6(c) are also another explanatory diagram of the sampling method according to the present invention. Since the operation modes described in Fig. 6(a)-Fig. 6(c) are very similar to those described in Fig. 5(a)-Fig. In addition to the situations described in Figure 5(a)-Figure 5(c) and Figure 6(a)-Figure 6(c), when it is judged that the position of the data transition point is located at the sampling edge of clock A or clock B When the sampling edge of , then either clock C or clock D can be selected as a better sampling clock, which can be understood from Fig. 7(a) and Fig. 7(b). Fig. 7(a) and Fig. 7(b) are another explanatory diagrams of the sampling method according to the present invention.

From the above example, it can be seen that since the possibility of the sampling edge of the better sampling clock being at the data transition point has been ruled out during the selection process of the better sampling clock, the accuracy of the data obtained through this sampling method is The accuracy of the data obtained through the existing technology will be higher.

In addition, under non-ideal conditions, the sampling edge of the preferred sampling clock will not be located at the middle point of the bit of the digital signal DATA, and the present invention further provides a method, which can adjust the delay time of the digital signal DATA appropriately, Let the midpoint of the bit of the digital signal DATA move to the sampling edge of the preferred sampling clock, or at least let the midpoint of the bit of the digital signal DATA approach the sampling edge of the preferred sampling clock.

The adjustment method of the delay time is as follows: First, after selecting clock C or clock D as a better sampling clock, further determine whether the data transition point is located after the sampling edge of clock C and before the sampling edge of clock D, or at After the sampling edge of the clock D and before the sampling edge of the clock C, the delay time of the digital signal DATA is adjusted according to the judgment result. For example, if the clock D is selected as the better sampling clock, and it is determined that the data transition point is located after the sampling edge of the clock C and before the sampling edge of the clock D, it can be known that the middle point of the bit of the digital signal DATA lags behind the clock D Therefore, the delay time of the digital signal DATA should be reduced so that the middle point of the bit of the digital signal DATA is adjusted to the sampling edge of the clock D. In contrast, if clock D is selected as the better sampling clock, but the data transition point is located after the sampling edge of clock D and before the sampling edge of clock C, it can be known that the middle point of the bit of the digital signal DATA is ahead of the sampling of clock D Therefore, it is necessary to increase the delay time of the digital signal DATA, so that the middle point of the bit of the digital signal DATA is adjusted to the sampling edge of the clock D. Similarly, if the clock C is selected as a better sampling clock, the delay time can also be controlled in the same manner.

In the above delay time adjustment methods, whether it is to increase or decrease the delay time of the digital signal DATA, each adjustment can be implemented in a single stage or divided into multiple stages. For example, in terms of being divided into two stages, it can be divided into rough adjustment and fine adjustment. Coarse adjustments are used to make large timing adjustments, followed by fine adjustments to bring the midpoint of the bit closer to the sampling edge of the preferred sampling clock. Wherein, the adjustment range of the rough adjustment (that is, the first-stage adjustment) should not be greater than a quarter of the bit length.

In addition, because the adjustment of each stage may not be adjusted in place at one time, the user can make the adjustment of each stage several times according to the actual needs of the design, and can judge the data transition after each adjustment The position of the point is used to determine whether the position of the middle point of the bit has been adjusted too far, so as to further obtain the optimal delay time of this stage. If the adjustment of a certain stage is constantly changing between a certain two delay times (that is, the toggle phenomenon occurs), then only the execution time of each stage is limited, and the delay time finally obtained is defined as the optimal delay time of this stage. Then proceed to the next stage of adjustment.

Those skilled in this art can also increase the number of clocks to operate, as long as the total number of clocks is equal to 2N, where N is a positive integer. Fig. 8(a) is another explanatory diagram of the sampling method according to the present invention. Please refer to Figure 5(a) and Figure 8(a) at the same time. After comparison, it can be found that Figure 8(a) has four more clocks than Figure 5(a), with A', B', C' and D respectively ' to mark, and the same mark represents the same clock. As for the arrows next to the marks A', B', C' and D', they also indicate the sampling edges of the clock. Take the arrows next to the two marks A' in the figure as an example. These two arrows represent the two points of the clock A'. Sampling edge of adjacent pulses.

Among the eight clocks, the frequency of clock A', clock B', clock C' and clock D' is the same as that of clock A, and clock A', clock B', clock C' and clock D' are respectively The clock A, the clock B, the clock C and the clock D are lagging behind by a third preset phase, and the third preset phase is half of the second preset phase. In this example, the first preset phase is also set to be 180°, so the second preset phase is 90°, and the third preset phase is 45°. It can be seen from the figure that clock A', clock B', clock C' and clock D' all use rising or falling edges as sampling edges, and the sampling edges of these four are the same as that of clock A. In addition, the symbol DATA is also represented as a digital signal, and the bit length of the digital signal DATA is equal to the clock period of eight clocks in the figure.

Please continue to refer to FIG. 8( a ). Although FIG. 8( a ) utilizes 8 clocks for operation, the way to obtain a better sampling clock is exactly the same as that described in FIG. 5( a ). In this example, clock A and clock B are used to determine the position of the data transition point of the digital signal, and then clock D is selected from clock C and clock D as a better sampling clock. However, the difference between the methods described in Fig. 8(a) and Fig. 5(a) is that the method described in Fig. 8(a) further uses the clock C and the clock D which is different from the preferred sampling clock as the reference clock (also That is, the clock C is used as a reference clock), and then the clock C and the clock D are used to sample the digital signal DATA. Next, the position of the data transition point of the digital signal DATA is determined according to the sampling results of the clock D and the clock C. The method of judging the position of the data transition point can be described by the following two formulas:

(C[0]XOR D[0])+(C[1]XOR D[1])+(C[2]XOR D[2])+…+(C[M-1]XOR D[M- 1])

...(Formula 3)

(D[0]XOR C[1])+(D[1]XOR C[2])+(D[2]XOR C[3])+…+(D[M-1]XOR C[M] )

...(Formula 4)

Formula 3 is used to determine whether the position of the data transition point is located after the sampling edge of clock C and before the sampling edge of clock D, and formula 4 is used to determine whether the position of the data transition point is located after the sampling edge of clock D and before the sampling edge of clock C.

In Equation 3 and Equation 4, C[0]-C[M] means that clock C has (M+1) sampling results in total, and D[0]-D[M] means that clock D has (M+1) total sampling results. sampling results, where M is a positive integer. As for XOR, it means that the sampling results of the clock C and the clock D are XORed. When judging the position of the transition point of the data, it is also necessary to use the methods described in Equation 3 and Equation 4 to make the judgment. If the value obtained by Equation 3 is non-zero and the value obtained by Equation 4 is zero, it can be determined that the data transition point is located after the sampling edge of clock C and before the sampling edge of clock D. Conversely, if the value obtained by Equation 3 is zero and the value obtained by Equation 4 is non-zero, it can be determined that the data transition point is located after the sampling edge of clock D and before the sampling edge of clock C.

Next, one of the two clocks that differ by 45° from clock D (that is, the better sampling clock) can be selected as the best sampling clock according to the judgment result, that is, clock B' or clock D' is selected as the best sampling clock clock. In Figure 8(a), since the position of the data transition point is just in the middle of the sampling edges of clock A and clock B, and is just at the sampling edge of clock C, then either clock B' or clock D' Either can be used as the best sampling clock. Although in this example, the sampling edges of the clock B' and the clock D' are not located at the middle point of the bits of the digital signal DATA relative to the clock D, they are still very close, so correct data can be sampled. Of course, in a more rigorous system, the step of using the clock C and the clock D to determine the position of the data transition point can also be repeated several times to avoid misjudging the position of the data transition point.

FIG. 8( b ) and FIG. 8( c ) are also another explanatory diagram of the sampling method according to the present invention, and these two diagrams also take 8 clocks as an example. Please refer to FIG. 8(b) first. It can be clearly seen from this figure that the data transition point of the digital signal DATA is located after the sampling edge of the clock D and before the sampling edge of the clock C, but is closer to the sampling edge of the clock C. Therefore, among the sampling edges of the clock B' and the clock D', the sampling edge of the clock B' is closer to the middle point of the bit of the digital signal DATA, so it is ideal to select the clock B' for sampling. Please refer to FIG. 8(c) again. It can be clearly seen from this figure that the data transition point of the digital signal DATA is located after the sampling edge of the clock C and before the sampling edge of the clock D, but is closer to the sampling edge of the clock C. Therefore, it is ideal to select the clock D' for sampling.

In the above examples shown in Figure 8(a)-Figure 8(c), the positions of the data transition points are located after the sampling edge of clock A and before the sampling edge of clock B, and then use clock C and clock D to determine Optimal sampling clock. In the following, the position of the data transition point is located after the sampling edge of clock B and before the sampling edge of clock A, and then use clock C and clock D to determine the best sampling clock as an example, as shown in Figure 9(a) 9(c). 9(a)-9(c) are another explanatory diagrams of the sampling method according to the present invention. In addition, the position of the data transition point is located at the sampling edge of clock A or the sampling edge of clock B, and then the example of using clock C and clock D to determine the best sampling clock is shown in Figure 10(a) and Figure 10 (b). Fig. 10(a) and Fig. 10(b) are also another explanatory diagram of the sampling method according to the present invention. Since the operation modes described in Fig. 9(a)-Fig. 9(c) and Fig. 10(a)-Fig. 10(b) are very similar to those described in Fig. 8(a)-Fig. 8(c), and The timing relationship between each clock and the digital signal has been shown in these diagrams, and the user can easily select the best sampling clock through the diagrams, and details will not be repeated here.

From the above example, it can be seen that the accuracy of the sampling operation performed by eight clocks is higher than the accuracy of the sampling operation performed by four clocks. In addition, although under non-ideal conditions, the sampling edge of the optimal sampling clock will not be located at the middle point of the bit of the digital signal DATA, the user can also adjust the delay time of the digital signal DATA appropriately, such as using The aforementioned method of adjusting the delay time of the digital signal DATA allows the midpoint of the bit of the digital signal DATA to move to the sampling edge of the optimal sampling clock, or at least allows the midpoint of the bit of the digital signal DATA to approach the sampling edge of the optimal sampling clock. Sample edges. Of course, the delay range that can be adjusted by controlling the delay time of the digital signal DATA should be less than or equal to one-eighth of the bit length of the digital signal.

From the methods described in the above embodiments, it can be known that for the sampling system applying the present invention, its preferred operation flow should include the adjustment of the delay time of the digital signal, as shown in FIG. 11 . FIG. 11 is a flow chart of one preferred operation of the sampling system of the present invention. Referring to FIG. 11 , the sampling system (not shown) will operate according to the following procedure: First, select the best sampling clock from 2 ^N sampling clocks (such as step 1102 ). Next, roughly adjust the delay time of the digital signal (such as step 1104). Then, it is judged whether the action of coarse adjustment exceeds its predetermined time (such as step 1106). When the judgment is no, continue to roughly adjust the delay time of the digital signal; when the judgment is yes, finely adjust the delay time of the digital signal (such as step 1108). Next, it is judged whether the action of detail adjustment exceeds its predetermined time (such as step 1110). When judged as no, continue to adjust the delay time of the digital signal in detail; Such as step 1112). With such a sampling method, the probability of the sampling system sampling wrong data will be greatly reduced. Of course, the operation process shown in FIG. 11 does not necessarily have to undergo two-stage adjustments, and may only need one stage, for example, only rough adjustments. In this way, when it is judged that the rough adjustment has exceeded the predetermined time, step 1112 can be directly executed.

FIG. 12 is a block diagram of one of the data recovery circuits using the sampling method of the present invention. Please refer to FIG. 12 , the data recovery circuit includes an oversampling module 1210 , a time reset module 1220 and a gap control module 1230 . The oversampling module 1210 is used to receive clock A, clock B, clock C, and clock D. The frequencies of these four clocks are the same, and clock B lags behind clock A by a first preset phase, and clock C and clock D lag behind clock A respectively. and a second preset phase of the clock B, and the second preset phase is half of the first preset phase. In this example, the first preset phase is set to be 180°, so the second preset phase is 90°. In addition, the data of the digital signal DATA is transmitted in a serial manner, and the bit length of the digital signal DATA is equal to the clock periods of the above four clocks.

The circuit shown in FIG. 12 is divided into two periods to operate. First, in the first period, the oversampling module 1210 uses clock A and clock B to sample the digital signal DATA, and both clock A and clock B rise or fall as a sampling edge. Moreover, the over-sampling module 1210 converts the sampling result into parallel data to serve as the output OS of the over-sampling module 1210 . Next, the time reset module 1220 synchronizes the parallel data output by the oversampling module 1210 to generate a synchronization result TS. The synchronization result TS is parallel data after synchronization, so the reference point of the data in time has been adjusted from the original inconsistency to the consistency. In this example, synchronization of the parallel data can be achieved by resampling the parallel data with an independent clock. Then, the gap control module 1230 judges the position of the data transition point of the digital signal DATA according to the synchronization result TS, so as to select clock C or clock D as a better sampling clock according to the judgment result. The method of judging the position of the data transition point of the digital signal DATA has been explained in the related descriptions of the foregoing formula (1) and formula (2), and the selection method of a better sampling clock has also been discussed in the previous embodiment. I will not repeat them here.

After selecting a better sampling clock, the data recovery circuit enters a second period to operate. During the second period, the oversampling module 1210 uses the clock C and the clock D to sample the digital signal DATA, and the sampling edge of the clock C and the clock D is the same as the sampling edge of the clock A. Moreover, the over-sampling module 1210 converts the sampling result into parallel data to serve as the output OS of the over-sampling module 1210 . Next, the time reset module 1220 synchronizes the parallel data output by the oversampling module 1210 to generate a synchronization result TS. Then, the gap control module 1230 controls the time reset module 1220 so that the time reset module 1220 selects the synchronous parallel data obtained by a better sampling clock from the synchronization result TS as the output OUT of the data recovery circuit.

In this example, the oversampling module 1210 is implemented with multiplexers 1212 , 1214 and an oversampling circuit 1216 . The multiplexer 1212 is used to receive the clock A and the clock C, and output the clock A and the clock C in the first period and the second period respectively. The multiplexer 1214 is used to receive the clock B and the clock D, and output the clock B and the clock D in the first period and the second period respectively. The over-sampling circuit 1216 is used for sampling the digital signal DATA by using the clock output from the multiplexer 1212 and the multiplexer 1214 . In addition, the user can use an independent selection signal (not shown) to input the multiplexer 1212 and the multiplexer 1214 to control the two multiplexers to select the clock, as long as the selection signal is selected It is enough that the target can match the selection target of the first period and the second period mentioned above. Of course, through proper circuit design, the user can also choose to use the gap control module 1230 to output the above selection signal.

It has been mentioned in the relevant description of Fig. 11 that for the sampling system applying the present invention, its preferred operation process should include the adjustment action of the delay time of the digital signal, and the way of controlling the delay time of the digital signal includes dividing it into multiple Stage way to control the delay time of the digital signal DATA. The following is an example of using two stages to control the delay time of the digital signal DATA, as shown in FIG. 13 .

FIG. 13 is a block diagram of another data recovery circuit employing the sampling method of the present invention. Please refer to FIG. 12 and FIG. 13 at the same time. After comparison, it can be found that the data recovery circuit shown in FIG. 13 has a variable delay module 1240 , and the oversampling circuit 1216 receives the digital signal DATA through the variable delay module 1240 . The variable delay module 1240 controls the delay time of the digital signal DATA according to the control signals CS1 and CS2, and the control signals CS1 and CS2 are the positions of the data transition points of the digital signal DATA by the gap control module 1230 in the second period. generated by the position. The control signal CS1 is used for the first stage of control, and the control signal CS2 is used for the second stage of control. Therefore, the adjustable delay range of the control signal CS2 is smaller than the adjustable delay range of the control signal CS1, and the adjustable delay range of the control signal CS1 is less than or equal to a quarter of the bit length of the digital signal DATA. After the variable delay module 1240 controls the delay time of the digital signal DATA according to the control signals CS1 and CS2, the over-sampling circuit 1216 performs the output DS of the variable delay module 1240 according to the clocks output by the multiplexers 1212 and 1214. sampling.

In order to illustrate more clearly how the control signals CS1 and CS2 control the delay time of the digital signal DATA, one implementation of the variable delay module 1240 is enumerated below, as shown in FIG. 14 . FIG. 14 is a circuit block diagram of one implementation of the variable delay module 1240 . Please refer to FIG. 14 , the variable delay module 1240 includes a first-stage delay control circuit 1410 and a second-stage delay control circuit 1420 . The first-stage delay control circuit 1410 includes delay units 1411 - 1413 and a multiplexer 1414 , and the second-stage delay control circuit 1420 includes delay units 1421 - 1425 and a multiplexer 1426 . These delay units are all implemented with a plurality of series-connected inverters, and the number of series-connected inverters in each delay unit is different, so the delay time of each delay unit is also different. .

In the first-stage delay control circuit 1410, the delay times of the delay units 1411, 1412, and 1413 are respectively set to the minimum delay time, the preset delay time, and the maximum delay time of the first stage, and then the multiplexer 1414 selects to maintain the preset delay time according to the control signal CS1, or selects to adjust to one of the maximum delay time and the minimum delay time. In addition, the distance between the minimum delay time and the predetermined delay time and the distance between the predetermined delay time and the maximum delay time are equal, and the distance is less than or equal to 1/4 of the bit length of the digital signal DATA. In other words, the delay range that can be adjusted by controlling the delay time of the digital signal DATA through the first-stage delay control circuit 1410 is less than or equal to a quarter of the bit length of the digital signal DATA.

Similarly, in the second-stage delay control circuit 1420, the delay times of the delay units 1421, 1422, 1423, 1424, and 1425 are respectively set to the minimum delay time, the second least delay time, the preset delay time, and the second-stage delay time of the second stage. The second maximum delay time and the maximum delay time, and then the multiplexer 1426 selects to maintain the preset delay time according to the control signal CS2, or selects to adjust to the minimum delay time, the second minimum delay time, the second maximum delay time and the maximum delay time one of them. In the delay control of the second stage, the distance between the minimum delay time and the second least delay time, the distance between the second least delay time and the preset delay time, the distance between the preset delay time and the second most delay time, The intervals between the second most delay time and the maximum delay time are equal to the above four intervals.

In addition, the distance between the minimum delay time and the preset delay time and the distance between the default delay time and the maximum delay time in the second stage are smaller than the distance between the minimum delay time and the preset delay time in the first stage and the distance between the preset delay time and the maximum delay time. In other words, the adjustable delay range of the second stage is smaller than the adjustable delay range of the first stage. Therefore, the delay control in the first stage is to roughly adjust the delay time of the digital signal DATA, and the delay control in the second stage is to fine-tune the delay time of the digital signal DATA. Of course, what this figure shows is only one embodiment of the delay control circuit. Users can change the number of delay units in each delay control circuit according to actual design requirements, or even increase the number of delay control circuits. for finer adjustments.

What has been introduced above is a data recovery circuit that obtains a better sampling clock from four sampling clocks. Next, a data recovery circuit that obtains the best sampling clock from eight sampling clocks will be introduced, as shown in FIG. 15 . FIG. 15 is a block diagram of another data recovery circuit employing the sampling method of the present invention. Please refer to FIG. 15 , the data recovery circuit includes an oversampling module 1510 , a time reset module 1520 and a gap control module 1530 . The oversampling module 1510 is used to receive clock A, clock B, clock C, clock D, clock A', clock B', clock C' and clock D', the frequencies of these eight clocks are all the same, and clock B lags behind clock A In the first preset phase, clock C and clock D lag behind clock A and clock B in the second preset phase respectively, while clock A', clock B', clock C' and clock D' lag behind clock A, clock B, clock C. The clock D has a third preset phase, and the second preset phase is half of the first preset phase, and the third preset phase is half of the second preset phase. In this example, the first preset phase is set to be 180°, so the second preset phase is 90°, and the second preset phase is 45°. In addition, the data of the digital signal DATA is transmitted in a serial manner, and the bit length of the digital signal DATA is equal to the clock period of the above eight clocks.

The circuit shown in FIG. 15 is divided into three periods to operate. First, in the first period, the oversampling module 1510 uses clock A and clock B to sample the digital signal DATA, and both clock A and clock B rise or fall as a sampling edge. Moreover, the over-sampling module 1510 converts the sampling result into parallel data as an output OS of the over-sampling module 1510 . Next, the time reset module 1520 synchronizes the parallel data output by the oversampling module 1510 to generate a synchronization result TS. The synchronization result TS is parallel data after synchronization, so the reference point of the data in time has been adjusted from the original inconsistency to the consistency. In this example, the synchronization of the parallel data can also be achieved by resampling the parallel data with an independent clock. Then, the gap control module 1530 judges the position of the data transition point of the digital signal DATA according to the synchronization result TS, so as to select clock C or clock D as a better sampling clock according to the judgment result. The method of judging the position of the data transition point of the digital signal DATA has been explained in the related descriptions of the foregoing formula (1) and formula (2), and the selection method of a better sampling clock has also been discussed in the previous embodiment. I will not repeat them here.

After selecting a better sampling clock, the data recovery circuit enters a second period to operate. During the second period, the oversampling module 1510 uses the clock C and the clock D to sample the digital signal DATA, and the sampling edge of the clock C and the clock D is the same as the sampling edge of the clock A. Moreover, the over-sampling module 1510 converts the sampling result into parallel data as an output OS of the over-sampling module 1510 . Next, the time reset module 1520 synchronizes the parallel data output by the oversampling module 1510 to generate a synchronization result TS. Then, the gap control module 1530 judges the position of the data transition point of the digital signal according to the synchronization result TS, and selects one of the two clocks with a third preset phase difference from the better sampling clock as the best sampling clock according to the judgment result , and generate the selection signal SL according to the optimal sampling clock. The method of using clock C and clock D to determine the position of the data transition point of the digital signal DATA has been explained in the related descriptions of the aforementioned formula (3) and formula (4), and the selection method of the best sampling clock is also explained in the previous The embodiments have already been discussed, and will not be repeated here.

After selecting the best sampling clock, the data recovery circuit enters the third period to operate. In the third period, the oversampling module 1510 selects the clock A' and the clock B' to sample the digital signal DATA according to the selection signal SL, or selects the clock C' and the clock D' to sample the digital signal DATA. In short, the oversampling module 1510 will select the best sampling clock and the clock that is 180° different from the best sampling clock from the clock A', clock B', clock C' and clock D' according to the selection signal SL for sampling, and The sampling edges of these two clocks are the same as the sampling edge of clock A. Moreover, the over-sampling module 1510 converts the sampling result into parallel data as an output OS of the over-sampling module 1510 . Next, the time reset module 1520 synchronizes the parallel data output by the oversampling module 1510 to generate a synchronization result TS. Then, the gap control module 1530 controls the time reset module 1520 so that the time reset module 1520 selects the synchronous parallel data obtained by the optimal sampling clock from the synchronization result TS as the output OUT of the data recovery circuit.

In this example, the oversampling module 1510 is implemented with multiplexers 1512 , 1514 and an oversampling circuit 1516 . The multiplexer 1512 is used to receive clock A, clock C, clock A' and clock C', and output clock A and clock C respectively in the first period and the second period, and in the third period, the multiplexer The multiplexer 1512 selects the clock according to the selection signal SL, so as to select the best sampling clock or the clock different from the best sampling clock by 180° from the clock A' and the clock C' as an output. The multiplexer 1514 is used to receive clock B, clock D, clock B' and clock D', and output clock B and clock D respectively in the first period and the second period, and in the third period, multiplex The multiplexer 1514 selects the clock according to the selection signal SL, so as to select a clock with a difference of 180° from the output of the multiplexer 1512 from the clock B′ and the clock D′ as an output. The over-sampling circuit 1516 is used for sampling the digital signal DATA using the clock output from the multiplexers 1512 and 1514 .

Similarly, the circuit shown in FIG. 15 can also add a variable delay module to adjust the delay time of the digital signal DATA. In the following, it is also taken as an example to control the delay time of the digital signal DATA in a two-stage manner, as shown in FIG. 16 . FIG. 16 is a block diagram of another data recovery circuit employing the sampling method of the present invention. Please refer to FIG. 15 and FIG. 16 at the same time. After comparison, it can be found that the circuit shown in FIG. 16 has a variable delay module 1540 , and the oversampling circuit 1516 receives the digital signal DATA through the variable delay module 1540 . The operation of the variable delay module 1540 is exactly the same as that of the variable delay module 1240 in FIG. 13 , so the internal circuit of the variable delay module 1540 can also be implemented by the circuit shown in FIG. 14 .

According to the teachings of the above embodiments, some basic operation procedures can be summarized, as shown in FIG. 17 . FIG. 17 is a flowchart of a sampling method according to an embodiment of the present invention. Please refer to Fig. 17, at first, provide the first clock, the second clock, the third clock and the fourth clock, the frequency of each clock is the same, and the second clock lags behind the first preset phase of the first clock, and the third clock and The fourth clock lags behind the first clock and the second clock by a second preset phase, and the second preset phase is half of the first preset phase (eg step 1702 ). Then, use the first clock and the second clock to sample the digital signal respectively, and use the rising edge or falling edge of the first clock and the second clock as the sampling edge, wherein the bit length of the digital signal is the same as that of the first clock and the second clock , clock periods of the third clock and the fourth clock are equal (eg step 1704). Then, determine the position of the data transition point of the digital signal according to the sampling results of the first clock and the second clock (such as step 1706). Next, the third clock or the fourth clock is selected as a better sampling clock according to the judgment result (such as step 1708). Then, the digital signal is sampled with a better sampling clock, wherein the sampling edge of the better sampling clock is the same as the sampling edge of the first clock (eg step 1710).

In summary, the present invention provides four sampling clocks with the same frequency but with different phase delays, and the second clock lags behind the first clock by the first preset phase, while the third clock and the fourth clock lag behind respectively The first clock and the second clock have second preset phases, and the second preset phase is half of the first preset phase. Next, use the first clock and the second clock to judge the data transition point position of the digital signal, and select the clock whose sampling edge is closer to the middle point of the digital signal from the third clock and the fourth clock as a better sample clock, to use a better sampling clock to sample digital signals and improve the accuracy of data sampling. Even, the present invention can also be combined with the technique of adjusting the delay time of the digital signal, so that the middle point of the bit of the digital signal is adjusted to the sampling edge of the better sampling clock, or the middle point of the bit of the digital signal approaches the better The sampling edge of the sampling clock to further improve the accuracy of data sampling.

Claims (16)

1. A sampling method comprising: providing a first clock, a second clock, a third clock and a fourth clock, each clock has the same frequency, and the second clock lags behind the first clock by a first preset phase, and the third clock and the fourth clock lags the first clock and the second clock by a second predetermined phase respectively, and the second predetermined phase is half of the first predetermined phase; Sampling a digital signal by using the first clock and the second clock respectively, and taking the rising edge or falling edge of the first clock and the second clock as the sampling edge, wherein the bit length of the digital signal is the same as the first clock periods of the clock, the second clock, the third clock and the fourth clock are equal; judging the position of the data transition point of the digital signal according to the sampling results of the first clock and the second clock; Selecting the third clock or the fourth clock as a better sampling clock according to the judgment result; Control the delay time of the digital signal according to the position of the data transition point of the digital signal, so that the middle point of the bit of the digital signal is adjusted to the sampling edge of the preferred sampling clock, or the digital signal The midpoint of the bit approaches the sampling edge of the preferred sampling clock; and The digital signal is sampled by the preferred sampling clock, wherein the sampling edge of the preferred sampling clock is the same as the sampling edge of the first clock. 2. The sampling method according to claim 1, wherein the method of judging the position of the data transition point of the digital signal comprises judging whether the data transition point of the digital signal is located after the sampling edge of the first clock and the second Before the sampling edge of the clock, after the sampling edge of the second clock and before the sampling edge of the first clock, the sampling edge of the first clock or the sampling edge of the second clock, and when the data transition of the digital signal is judged When the state point is located after the sampling edge of the first clock and before the sampling edge of the second clock, select the fourth clock as the better sampling clock; when it is judged that the data transition point of the digital signal is located at the second clock After the sampling edge and before the sampling edge of the first clock, select the third clock as the preferred sampling clock; when it is judged that the data transition point of the digital signal is located at the sampling edge of the first clock or at the sampling edge of the second clock When sampling an edge, any one of the third clock and the fourth clock is selected as the preferred sampling clock. 3. The sampling method as claimed in claim 1, wherein the mode of controlling the delay time of the digital signal comprises judging that the data transition point of the digital signal is after the sampling edge of the third clock and the sampling edge of the fourth clock Before the edge, or after the sampling edge of the fourth clock and before the sampling edge of the third clock, when the third clock is selected as the preferred sampling clock, and it is judged that the data transition point of the digital signal is located at the first After the sampling edge of the third clock and before the sampling edge of the fourth clock, increase the delay time of the digital signal, when the third clock is selected as the preferred sampling clock, and it is judged that the data transition point of the digital signal is located at When the sampling edge of the fourth clock is before the sampling edge of the third clock, the delay time of the digital signal is reduced, when the fourth clock is selected as the preferred sampling clock, and the data transition point of the digital signal is judged When it is located after the sampling edge of the third clock and before the sampling edge of the fourth clock, the delay time of the digital signal is reduced, when the fourth clock is selected as the better sampling clock, and the data transition of the digital signal is judged When the state point is located after the sampling edge of the fourth clock and before the sampling edge of the third clock, the delay time of the digital signal is increased. 4. The sampling method as claimed in claim 3, wherein, including increasing or decreasing the delay time of the digital signal in a plurality of stages, wherein the adjustment range of the current stage is greater than the adjustment range of the next stage, and the first stage The adjustment range of is less than or equal to a quarter of the bit length of the digital signal. 5. The sampling method according to claim 1, further comprising providing a fifth clock, a sixth clock, a seventh clock and an eighth clock, the fifth clock, the sixth clock, the seventh clock and the frequency of the eighth clock is the same as the frequency of the first clock, and the fifth clock, the sixth clock, the seventh clock and the eighth clock are behind the first clock, the second clock, the second clock, respectively The third clock and the fourth clock have a third preset phase, and the third preset phase is half of the second preset phase, and while sampling the digital signal with the better sampling clock, the second preset phase is further The one of the three clocks and the fourth clock which is different from the preferred sampling clock is used as a reference clock, and the digital signal is sampled by using the reference clock, wherein the sampling edge of the reference clock is the same as the sampling edge of the preferred sampling clock, The sampling method also includes the following steps: judging the position of the data transition point of the digital signal according to the sampling results of the better sampling clock and the reference clock; Selecting one of the two clocks with the third preset phase difference from the preferred sampling clock as an optimal sampling clock according to the judgment result; and The digital signal is sampled using the optimal sampling clock, wherein the sampling edge of the optimal sampling clock is the same as the sampling edge of the preferred sampling clock. 6. The sampling method according to claim 5, wherein the method of judging the position of the data transition point of the digital signal comprises judging whether the data transition point of the digital signal is located after the sampling edge of the preferred sampling clock and the reference Before the sampling edge of the clock, after the sampling edge of the reference clock and before the sampling edge of the better sampling clock, or the sampling edge of the reference clock, and when the third clock is used as the better sampling clock, and the digital When the data transition point of the signal is located after the sampling edge of the preferred sampling clock and before the sampling edge of the reference clock, the fifth clock is selected as the optimal sampling clock; when the third clock is used as the preferred sampling clock, And when judging that the data transition point of the digital signal is located after the sampling edge of the reference clock and before the sampling edge of the better sampling clock, the seventh clock is selected as the best sampling clock; when the third clock is used as the better sampling clock When it is judged that the data transition point of the digital signal is at the sampling edge of the reference clock, any one of the fifth clock and the seventh clock is selected as the best sampling clock; when the fourth clock is used as the When it is judged that the data transition point of the digital signal is located after the sampling edge of the preferred sampling clock and before the sampling edge of the reference clock, the sixth clock is selected as the optimal sampling clock; Four clocks are used as the preferred sampling clock, and when it is judged that the data transition point of the digital signal is located after the sampling edge of the reference clock and before the sampling edge of the preferred sampling clock, the eighth clock is selected as the optimal sampling clock ; When the fourth clock is used as the better sampling clock, and it is judged that the data transition point of the digital signal is at the sampling edge of the reference clock, select any one of the sixth clock and the eighth clock as the best sampling clock. 7. A data recovery circuit comprising: An oversampling module, receiving a first clock, a second clock, a third clock and a fourth clock, each clock has the same frequency, and the second clock lags behind the first clock by a first preset phase, And the third clock and the fourth clock lag behind the first clock and the second clock by a second preset phase respectively, and the second preset phase is half of the first preset phase, during a first period wherein, the oversampling module uses the first clock and the second clock to sample a digital signal, and uses the rising edge or falling edge of the first clock and the second clock as the sampling edge, and in a second period, The oversampling module uses the third clock and the fourth clock to sample the digital signal, and the sampling edge of the third clock and the fourth clock is the same as the sampling edge of the first clock, and the oversampling module converts the sampling result Parallel data as the output of the oversampling module, wherein the bit length of the digital signal is equal to the clock period of the above four clocks; A time reset module, used to synchronize the parallel data output by the oversampling module to generate a synchronization result; A gap control module, in the first period, the gap control module judges the position of the data transition point of the digital signal according to the synchronization result, so as to select the third clock or the fourth clock as a better clock according to the judgment result sampling clock, and in the second period, the gap control module controls the time reset module, so that the time reset module selects the synchronous parallel data obtained by the better sampling clock from the synchronization result as the the output of the data recovery circuit; and A variable delay module, the oversampling module receives the digital signal through the variable delay module, the variable delay module controls the delay time of the digital signal according to a first control signal, and in the second period, the The gap control module further generates the first control signal according to the position of the data transition point of the digital signal. 8. The data recovery circuit as claimed in claim 7, wherein the oversampling module comprises: a first multiplexer, configured to receive the first clock and the third clock, and output the first clock and the third clock during the first period and the second period respectively; a second multiplexer for receiving the second clock and the fourth clock, and outputting the second clock and the fourth clock during the first period and the second period respectively; and A super-sampling circuit is used for sampling the digital signal by using the clocks output by the first multiplexer and the second multiplexer. 9. The data recovery circuit as claimed in claim 7, wherein the manner in which the gap control module judges the position of the data transition point of the digital signal comprises judging that the data transition point of the digital signal is located after the sampling edge of the first clock Before the sampling edge of the second clock, after the sampling edge of the second clock and before the sampling edge of the first clock, the sampling edge of the first clock or the sampling edge of the second clock, and when the gap control When the module judges that the data transition point of the digital signal is located after the sampling edge of the first clock and before the sampling edge of the second clock, the gap control module selects the fourth clock as the preferred sampling clock; when the gap control When the module judges that the data transition point of the digital signal is located after the sampling edge of the second clock and before the sampling edge of the first clock, the gap control module selects the third clock as the preferred sampling clock; when the gap control When the module judges that the data transition point of the digital signal is located at the sampling edge of the first clock or the sampling edge of the second clock, the gap control module selects any one of the third clock and the fourth clock as the better sampling clock. 10. The data recovery circuit as claimed in claim 7, wherein the delay range adjustable by the first control signal is less than or equal to a quarter of the bit length of the digital signal. 11. The data recovery circuit according to claim 10, wherein the variable delay module further controls the delay time of the digital signal according to a second control signal, and the adjustable delay range of the second control signal is smaller than that of the first control signal A control signal can adjust the delay range, and in the second period, the gap control module generates the second control signal according to the position of the data transition point of the digital signal. 12. A data recovery circuit comprising: An oversampling module, receiving a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock and an eighth clock, each clock The frequency is the same, and the second clock lags behind the first clock by a first preset phase, the third clock and the fourth clock lag behind the first clock and the second clock by a second preset phase, and the first The fifth clock, the sixth clock, the seventh clock and the eighth clock are respectively behind the first clock, the second clock, the third clock and the fourth clock by a third preset phase, and the second preset Assuming that the phase is half of the first preset phase, and the third preset phase is half of the second preset phase, during a first period, the oversampling module utilizes the first clock and the second clock Sampling a digital signal, and using the rising edge or falling edge of the first clock and the second clock as the sampling edge, in a second period, the oversampling module uses the third clock and the fourth clock to sample the digital signal, and the sampling edge of the third clock and the fourth clock is the same as the sampling edge of the first clock, in a third period, the oversampling module uses the fifth clock and the sixth clock to sample the digital signal, or use the seventh clock and the eighth clock to sample the digital signal, the sampling edge of the fifth clock, the sixth clock, the seventh clock and the eighth clock and the sampling edge of the first clock The same, and the oversampling module converts the sampling result into parallel data as the output of the oversampling module, wherein the bit length of the digital signal is equal to the clock period of the above eight clocks; a time reset module, used to synchronize the parallel data output by the oversampling module to generate a synchronization result; and A gap control module, in the first period, the gap control module judges the position of the data transition point of the digital signal according to the synchronization result, so as to select the third clock or the fourth clock as a better clock according to the judgment result Sampling clock, in the second period, the gap control module judges the position of the data transition point of the digital signal according to the synchronization result, and selects two phases different from the better sampling clock with the third preset phase according to the judgment result One of the two clocks is used as an optimal sampling clock. In the third period, the gap control module controls the over-sampling module to select the optimal sampling clock and the first preset phase difference from the optimal sampling clock. The clock is used for sampling, and the time reset module is controlled so that the time reset module selects the synchronous parallel data obtained by the optimal sampling clock from the synchronization results as the output of the data recovery circuit. 13. The data recovery circuit as claimed in claim 12, wherein the oversampling module comprises: a first multiplexer for receiving the first clock, the third clock, the fifth clock and the seventh clock, and outputting the first clock during the first period and the second period respectively and the third clock, and during the third period, the first multiplexer is controlled by the gap control module to select the best sampling clock from the fifth clock and the seventh clock or with the The optimal sampling clock differs from the clock with the first preset phase as an output; A second multiplexer, used to receive the second clock, the fourth clock, the sixth clock and the eighth clock, and output the second clock during the first period and the second period respectively and the fourth clock, and in the third period, the second multiplexer is controlled by the gap control module to select the first multiplexer from the sixth clock and the eighth clock The clock whose output is different from the first preset phase is used as an output; and A super-sampling circuit is used for sampling the digital signal by using the clocks output by the first multiplexer and the second multiplexer. 14. The data recovery circuit according to claim 12, further comprising a variable delay module, and the oversampling module further receives the digital signal through the variable delay module, and the variable delay module is based on a first control signal to control the delay time of the digital signal, and in the third period, the gap control module generates the first control signal according to the position of the data transition point of the digital signal. 15. The data recovery circuit according to claim 14, wherein the delay range adjustable by the first control signal is less than or equal to one-eighth of the bit length of the digital signal. 16. The data recovery circuit according to claim 15, wherein the variable delay module further controls the delay time of the digital signal according to a second control signal, and the adjustable delay range of the second control signal is smaller than that of the first control signal A control signal can adjust the delay range, and in the third period, the gap control module generates the second control signal according to the position of the data transition point of the digital signal.

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