CN101577541A

CN101577541A - Frequency divider, frequency dividing method and phase-locked loop using the same

Info

Publication number: CN101577541A
Application number: CN 200910137874
Authority: CN
Inventors: 高宏鑫; 杨孟达; 赵冠华; 徐哲祥
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2008-05-09
Filing date: 2009-05-05
Publication date: 2009-11-11
Also published as: CN101577543A

Abstract

The invention provides a frequency divider, a frequency dividing method and a phase-locked loop using the frequency divider. The phase selector receives a plurality of clock signals and outputs an intermediate signal according to the phase characteristic of at least one of the clock signals. The adjustable delay circuit receives the intermediate signal and generates an output signal by delaying the intermediate signal. The frequency divider of the invention can reduce jitter and power consumption.

Description

Frequency divider, dividing method and use the phase-locked loop of this frequency divider

Technical field

The invention relates to a kind of frequency divider, refer to a kind of frequency divider that reduces shake (Jitter) and power consumption especially, refer in particular to a kind of frequency divider, dividing method and use the phase-locked loop of this frequency divider.

Background technology

Fractional divider (fractional-N frequency divider) be because can produce output frequency accurately according to a reference frequency, and is used in widely in many application.Be different from integer frequency divider (integer-Nfrequency divider) and be merely able to the output that generation time length is the integral multiple in reference cycle (for example generation time length is the output cycle of four double-lengths in reference cycle), fractional divider can be used for producing the output cycle (for example producing the output cycle of a time length for 4.01 double-lengths in this reference cycle) of non-integral multiple.By detecting-when carry signal (Carry Signal) or an overflow signal (Overflow Signal), divisor is switched to (M+1) by M, fractional divider can synthesize (Synthesize) output frequency for the branch several times of reference frequency.For instance, if fractional divider need produce 0.3 times and (also be, divisor is 10/3) reference frequency, then only need be three continuous removing in one number time (Cycle), two divisors that remove one number time are made as 3, and will remain a divisor that removes one number time and be made as 4, can produce this output frequency.

Yet, known fraction frequency divider suitable complexity on circuit design, and its circuit design often is accompanied by high power consumption, bigger chip area, and problem such as shake usefulness.

Summary of the invention

In view of this, one of purpose of the present invention provides a kind of frequency divider that reduces shake, saving chip area and power consumption, to address the above problem.

According to one embodiment of the invention, it is to disclose a kind of frequency divider.Described frequency divider comprises a phase selector and an adjustable delay circuit.Described phase selector is to be used for receiving a plurality of clock signals and to export a M signal.Described M signal is the phase characteristic corresponding at least one clock signal in described these clock signals.Described adjustable delay circuit is to be used for receiving described M signal, and postpones described M signal and produce an output signal.

According to another embodiment of the present invention, it is to disclose a kind of phase-locked loop.Described phase-locked loop comprises phase detectors, a filter, an oscillator and a frequency divider.Described phase detectors are used for detecting the phase difference between a reference signal and an input signal, and produce a difference signal according to described phase difference.Described filter is to be coupled to described phase detectors, is used for described difference signal is carried out filtering to produce a filtering signal.Described oscillator is to be coupled to described filter, is used for producing a plurality of clock signals according to described filtering signal.Described frequency divider is to be coupled to described oscillator and described phase detectors, is used for producing a fractional frequency signal according to described these clock signals.Described frequency divider comprises a phase selector and an adjustable delay circuit.Described phase selector is to be used for receiving described these clock signals and to export a M signal.Described M signal is the phase characteristic corresponding at least one clock signal in described these clock signals.Described adjustable delay circuit is to be coupled to described phase selector, is used for receiving described M signal, and postpones described M signal and produce a fractional frequency signal.Described input signal is corresponding to described fractional frequency signal.

According to another embodiment of the present invention, it is to disclose a kind of dividing method.Described dividing method comprises a plurality of clock signals of reception; Phase characteristic according at least one clock signal in described these clock signals produces a M signal; And postpone described M signal, to produce a fractional frequency signal.

The beneficial effect of the embodiment of the invention is: a kind of frequency divider that reduces shake, saving chip area and power consumption is provided.

Description of drawings

Fig. 1 is the function block diagram according to the disclosed frequency divider of one embodiment of the invention;

Fig. 2 is the schematic diagram according to the disclosed frequency divider of one embodiment of the invention;

Fig. 3 is an embodiment schematic diagram of the included pipeline delay circuit of frequency divider shown in Figure 2;

Fig. 4, Fig. 5 and Fig. 6 are the schematic diagram of the embodiment of the included adjustable delay circuit of frequency divider shown in Figure 2;

Fig. 7 is the time schematic diagram of an embodiment mutually of frequency divider shown in Figure 2;

Fig. 8 is the schematic diagram of a phase-locked loop of the disclosed frequency divider of use the present invention;

Fig. 9 is the flow chart according to the disclosed dividing method of one embodiment of the invention.

Drawing reference numeral

100,201 clock generators

120,220 phase selectors

140,240 adjustable delay circuits

150,250 controllers

200 phase-locked loops

221a, 221b, 221c, 221d phase characteristic are selected circuit

222 combinational circuits

241a, 241b ..., 241n, 301a, 301b ..., 301N delay cell

242a, 242b ..., 242n, 246a, 246b ..., 246n, latch

303a、303b、...、303N

244a, 244b ..., the 244n logical circuit

302a, 302b ..., 302N selects logical circuit

401a, 401b ..., 401N, 501a[1], 502b[1], delay circuit

501b[2]、...、501N[1]、501N[2]、...、501N[2^N]、

601a、601b、...、601N

402a, 402b ..., 402N, 502a, 502b ..., select circuit

502N、603a、603b、...、603N

602a, 602b ..., the 602N load circuit

810 phase/frequency detectors

820 charge pumps

830 loop filters

840 voltage controlled oscillators

850 frequency dividers

900,902,904 steps

Embodiment

See also Fig. 1, it is the function block diagram according to the disclosed frequency divider of one embodiment of the invention.This frequency divider comprises a phase selector (Phase Selector) 120, one an adjustable delay circuit 140 and a controller 150.Phase selector 120 be from a clock generator 100 receive a plurality of clock signal P0, P1 ..., Pn.Clock signal P0, P1 ..., Pn has the delay relation of a scheduled time length to each other.In one embodiment, this scheduled time length is

Wherein T is the cycle of those clock signals, and N is the quantity of clock signal, and i is 0,1 ..., (N-1).With N=4 is example (also being four clock signals), and clock signal P1 is that clock signal P0 postpones

Clock signal P2 is that clock signal P0 postpones

Clock signal P3 is that clock signal P0 postpones

Wherein T be clock signal P0, P1 ..., cycle of Pn (those clock signals P0, P1 ..., Pn has rough identical frequency).Phase selector 120 receive clock signal P0, P1 ..., Pn, according to one select signal select those clock signals P0, P1 ..., at least one clock signal among the Pn, and produce a M signal according to the phase characteristic of the clock signal of selecting.Adjustable delay circuit 140 receives this M signal from phase selector 120, and is used for producing an output signal Out; In one embodiment, adjustable delay circuit 140 is these M signals that postpone to be received according to a delayed control signal, to produce output signal Out.Controller 150 is to be used for producing this selection signal and this delayed control signal, transfers to phase selector 120 and adjustable delay circuit 140 respectively.Though note that in the present embodiment, select signal and delayed control signal to be provided, yet the present invention be not confined to this by single controller 150; In other words, in other embodiments of the invention, select signal and delayed control signal to be provided, and these controllers can be integrated in phase selector 120 and the adjustable delay circuit 140 by different controllers.Moreover, frequency divider also can omit controller, and will select selection function that signal provides and the delay controlled function that delayed control signal provided to default in advance in phase selector 120 and the adjustable inhibit signal 140, such framework can omit this selection signal and this delayed control signal.

See also Fig. 2, it is the schematic diagram of an embodiment of frequency divider shown in Figure 1.In frequency divider shown in Figure 2, the value of N is 4, also is that the clock signal has four.Clock generator 201 can be the part of a phase-locked loop 200, exports four clock signal P0, P1, P2, P3, and four clock signal P0, P1, P2, P3 be respectively with 0 of a delayed reference signal,

Individual,

Individual, and

Individual period T produces.Phase selector 220 comprises four phase

characteristics selection circuit

221a, 221b, 221c, reaches 221d, difference receive clock signal P0, P1, P2, P3, and the selection signal S0 of controlled device 250 outputs, S1, S2, S3 control, according to selecting signal S0, S1, S2, S3 to come the optionally phase characteristic of clock signal P0, P1, P2, P3.For instance, controller 250 may command phase characteristics select circuit 221b to go to select the phase characteristic of clock signal P1, and wherein the phase characteristic of clock signal P1 is representative Delay.In general, clock generator 201 and phase selector 220 can to reference clock signal provide 0 to

Delay, with

Be class interval.Phase characteristic selects

circuit

221a, 221b, 221c, 221d to be realized by trigger (Flip-Flop) circuit, each flip-

flop circuit

221a, 221b, 221c, 221d comprise two inputs and an output, two inputs respectively receive clock signal P0, P1, P2, P3 one of them and select signal S0, S1, S2, S3 one of them, output export the phase characteristic of the clock signal of reception when selection signal S0, S1, S2, the S3 of correspondence are enabled (enabled).Phase characteristic

select circuit

221a, 221b, 221c, and the output of 221d be to be transferred to a combinational circuit 222, combinational circuit 222 is made up the phase characteristic that receives, and produces a M signal B according to this to adjustable delay circuit 240.Combinational circuit 222 can be realized by gate (logic gate), for example or gate (logic OR gate), NOR-logic door (logic NOR), with gate (logic AND gate), and NAND Logic door (logic NAND gate) or the like.

Adjustable delay circuit 240 can provide this M signal B

Delay (be at present embodiment

Delay), this retardation is controlled by the delayed control signal that controller 250 is produced.As shown in Figure 2, adjustable delay circuit 240 can be a pipeline (Pipeline) delay circuit, and comprise a plurality of

delay cell

241a, 241b ..., 241n, a plurality of first latch (Latch) 242a, 242b ..., 242n, a plurality of

logical circuit

244a, 244b ..., 244n and a plurality of

second latch

246a, 246b ..., 246n; Delay

cell

241a, 241b ..., 241n is used for this M signal of postponing to be received, the

first latch

242a, 242b ..., 242n,

logical circuit

244a, 244b ..., 244n and the

second latch

246a, 246b ..., 246n then form

delay cell

241a, 241b ..., the control circuit of 241n, and according to this delayed control signal come

control lag unit

241a, 241b ..., the retardation of 241n.Fig. 3 is the schematic diagram of another embodiment of pipeline delay circuit 240, and Fig. 4, Fig. 5, Fig. 6 are the schematic diagram of other embodiment of adjustable delay circuit 240.Pipeline delay circuit shown in Figure 3 comprise a plurality of

delay cell

301a, 301b ..., 301N, a plurality of selection

logical circuit

302a, 302b ..., 302N and a plurality of

latch circuit

303a, 303b ..., 303N.Delay cell 301a receives an input signal (for example this M signal), and exports an inhibit signal Q1 to delay cell 301b.At process delay cell 301a ..., after the delay of 301N, the M signal OUT that the last output one of delay cell 301N postpones.Adjustable delay circuit shown in Figure 4 comprise a plurality of delay circuit 401a, 401b ..., 401N, and a plurality of

selection circuit

402a, 402b ..., 402N.A delay input signal of selecting circuit 402a to receive an input signal IN and produced by delay circuit 401a, and by a selection signal SEL[0] control, optionally export input signal IN or this delay input signal to selecting circuit 402b and delay circuit 401b.By control

select circuit

402a, 402b ..., 402N goes to select an inhibit signal or without inhibit signal, adjustable circuit shown in Figure 4 can produce the delay of different time length to produce output signal OUT to input signal IN.Adjustable delay circuit shown in Figure 5 is the delay line (Delay Line) of binary bit control (binary-controlled), comprise a plurality of

selection circuit

502a, 502b ..., 502N and a plurality of delay circuit 501a[1], 502b[1], 501b[2] ..., 501N[1], 501N[2] ..., 501N[2^N].The class of operation of the operation of adjustable delay circuit shown in Figure 5 and adjustable delay circuit shown in Figure 4 seemingly, yet use a plurality of selection signal SEL[0 at adjustable delay circuit shown in Figure 5], SEL[1] ..., SEL[N] realize length time of delay of binary bit control.For instance, be that delay circuit shown in Figure 5 can provide 0 times to 15 times delay circuit unit delay length under 3 the situation in the value of N.At SEL[0]=1, SEL[1]=0, SEL[2]=0, SEL[3]=1 situation under, output signal OUT is that input signal IN postpones 9 unit delay length.Adjustable delay circuit shown in Figure 6 comprise a plurality of delay circuit 601a, 601b ..., 601N, a plurality of

load circuit

602a, 602b ..., 602N and a plurality of

selection circuit

603a, 603b ..., 603N.

Select circuit

603a, 603b ..., 603N can be respectively with

load circuit

602a, 602b ..., 602N couples or be not coupled to delay circuit 601a, 601b ..., 601N, and optionally input signal IN is applied delay in view of the above.Couple load circuit and can produce a delay, and each load circuit more can provide different lag characteristics via adjustment.

See also Fig. 7, its be frequency divider shown in Figure 2 the time phase an embodiment schematic diagram.One of them example of only operating shown in Figure 7 for frequency divider.In this embodiment, clock signal P0 is at first selected, and controller 250 will enable corresponding to the selection signal S0 of flip-flop circuit 221a, and will be corresponding to selection signal S1, S2, the S3 anergy (Disable) of other flip-

flop circuits

221b, 221c, 221d.Select signal S0 to start flip-flop circuit 221a, output is corresponding to a latch signal (Latch Signal) A0 of the phase characteristic of clock signal P0.When selecting signal S0 to start flip-flop circuit 221a, flip-

flop circuit

221b, 221c, 221d are pent, make latch signal A1, A2, A3 be in disabled state.This moment, the phase place of the M signal B that combinational circuit 222 is exported was corresponding to clock signal P0.

Adjustable delay circuit 240 is then postponed the pulse of M signal B, has the output signal OUT of Cycle Length for (T '+Δ T) with generation.As shown in Figure 7, the delay of M signal B is progressively to increase Δ T.When the retardation of signal B in the middle of 240 pairs of the adjustable delay circuits surpasses or is about to surpass T/4, controller 250 cuts out flip-flop circuit 221b by cutting out to transfer to opening also simultaneously flip-flop circuit 221a to be transferred to by unlatching, so that M signal B has the phase property of clock signal P1, also be the delay that the phase place of clock signal P0 adds T/4.

The latch signal A1 of flip-flop circuit 221b output is that the circuit 222 that is combined receives, follows combinational circuit 222 output latch signal A1 as M signal B.Similarly, adjustable delay circuit 240 is with the pulse daley Δ T of M signal B, 2 Δ T, 3 Δ T... etc., maintains (T '+Δ T) with the cycle with output signal.Then, the retardation that is provided when adjustable delay circuit 240 reaches T/4 and maybe will surpass in the T/4, controller 250 transfers flip-flop circuit 221c to unlatching by cutting out, and close flip-flop circuit 221b, making M signal B possess the phase characteristic of clock signal P2, also is that the phase place of clock signal P1 adds that the phase place of the delay of T/4 or clock signal P0 adds the delay of T/2.Thus, incoming frequency 1/T can transfer 1/ at the output of frequency divider (T '+Δ T).

Above-mentioned frequency divider only is one embodiment of the invention.Above-mentioned N value can be selected according to different design consideration, and the quantity of phase selector 120 and 220 included flip-flop circuits, clock signal P0, P1 ..., the quantity of PN and select signal S0, S1 ..., the quantity of SN all can design according to system requirements, is not subjected to the restriction of above narration.Flip-

flop circuit

221a, 221b, 221c, 221d utilogic door (logic gate) are replaced.Moreover, clock generator 100 and 200 and phase generator 120 and 220 can on reference signal, produce and be about zero to the (delay of the inequality of (N-1)/N) * T.In like manner, adjustable delay circuit 140 and 240 can produce the delay that is about zero to (1/N) * T inequality on reference signal.Controller the 150, the 250th can be digital, analog or mixed digital analogue.Adjustable circuit 140 and 240 also can adopt the framework beyond Fig. 2 to Fig. 6.

Because the frequency divider of Figure 1 and Figure 2 is to use phase selector to produce zero delay to (N-1) * T/N, the delay length of adjustable delay circuit can shorten significantly.For instance, when the value of N was 4, phase selector provided time span by zero delay to 3/4T, made the adjustable delay circuit only need provide length by zero delay to 1/4T.Therefore thus, the circuit complexity of adjustable delay circuit and area can be reduced, and frequency divider can have better simply circuit design, less power consumption, area, and shake.

See also Fig. 8, it is the schematic diagram of an embodiment of a phase-locked loop of the above-mentioned frequency divider of use.This phase-locked loop comprises a phase/frequency detector (Phase/frequency Detector, PFD) 810, one charge pump (Charge Pump), 820, one loop filter (Loop Filter), 830, one voltage controlled oscillator (Voltage-controlled Oscillator), 840 and one frequency divider 850, wherein the framework of frequency divider 850 and running are as shown in Figures 1 and 2.Phase/frequency detector 810 is the phase differences that detect between a reference signal Fref and the input signal, and produces a difference signal and indicate this phase place extent.Filter 830 is to be coupled to phase/frequency detector 810, is used for this difference signal is carried out filtering to produce a filtering signal.Oscillator 840 is to be coupled to filter 830, is used for producing a plurality of clock signal Fout according to this filtering signal, and in one embodiment, oscillator 840 is a ring oscillator (Ring Oscillator).Frequency divider 850 is to be coupled to oscillator 840 and phase/frequency detector 810, and is used for producing a fractional frequency signal according to those clock signals.Frequency divider 850 comprises a phase selector and an adjustable delay circuit.Phase selector is to receive those clock signals, and output is corresponding to a M signal of the phase characteristic of at least one clock signal in those clock signals.This adjustable delay circuit is to be coupled to this phase selector, is used for receiving this M signal, and produces this fractional frequency signal by postponing this M signal.This input signal is corresponding to this fractional frequency signal.This phase-locked loop also can comprise a controller (not shown), and wherein this controller is to be coupled to frequency divider 850, is used for controlling the phase property selection of phase selector in the frequency divider 850 and the delay of adjustable delay circuit.

See also Fig. 9, it is the flow chart according to the disclosed dividing method of one embodiment of the invention.This dividing method comprises and receives a plurality of clock signals (step 900), produces a M signal (step 902) according to the phase characteristic of at least one clock signal in those clock signals, and postpones this M signal to produce a fractional frequency signal (step 904).The step 902 that produces this M signal comprises the phase characteristic of exporting those clock signals according to a selection signal-selectivity ground, and produces this M signal by merging selecteed phase property.Those phase signals are the delay relation that can have special time length each other, postpone to produce by a reference clock signal being applied zero difference to (N-1) * T/N, and wherein N is the number of clock signal, and T is the cycle of reference clock signal.Postponing this M signal comprises with the step 904 that produces this fractional frequency signal and this M signal is applied zero to T/N delay.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. a frequency divider, is characterized in that, described frequency divider comprises:

a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to a phase characteristic of at least one of said clock signals; and

An adjustable delay circuit is used to receive the intermediate signal and generate an output signal by delaying the intermediate signal.

2. The frequency divider according to claim 1, wherein the clock signals are in a delay relationship with each other with a specific time length.

3. The frequency divider as claimed in claim 2, wherein the clock signals have approximately the same frequency.

4. frequency divider as claimed in claim 3, is characterized in that, described specific time length is

Wherein, T is the period of these clock signals, N is the number of these clock signals, and the value of i is 0, 1, . . . , (N-1).

5. frequency divider as claimed in claim 1, is characterized in that, described phase selector comprises:

a plurality of phase characteristic selection circuits for receiving the clock signals and selectively outputting the phase characteristics of the clock signals according to a selection signal; and

A combination circuit, coupled to the phase characteristic selection circuits, is used to receive the phase characteristics from the phase characteristic selection circuits, and generate the intermediate signal by combining the received phase characteristics.

6. The frequency divider according to claim 5, wherein said phase characteristic selection circuits comprise a plurality of logic gates.

7. The frequency divider according to claim 5, wherein said phase characteristic selection circuits comprise a plurality of flip-flop circuits.

8. frequency divider as claimed in claim 7, is characterized in that, each flip-flop circuit comprises two input terminals, is respectively used for receiving described wherein one of these clock signals and described selection signal; The circuit also includes an output terminal for outputting the phase characteristic of the received clock signal when the corresponding selection signal is enabled.

9. The frequency divider of claim 5, wherein the combinational circuit comprises a logic gate.

10. The frequency divider according to claim 5, wherein the number of the clock signals is the same as the number of the phase characteristic selection circuits.

11. The frequency divider according to claim 1, wherein the adjustable delay circuit is controlled by a delay control signal to provide a delay of 0 to T/N times for the intermediate signal, wherein T is the period of these clock signals, and N is the number of these clock signals.

12. The frequency divider according to claim 1, wherein the adjustable delay circuit is a pipeline delay circuit, and the pipeline delay circuit comprises a plurality of delays controlled by a delay control signal unit.

13. A phase-locked loop, characterized in that, the phase-locked loop comprises:

a phase detector for detecting a phase difference between a reference signal and an input signal, and generating a difference signal indicating the phase difference;

a filter, coupled to the phase detector, for filtering the difference signal to generate a filtered signal;

an oscillator, coupled to the filter, for generating a plurality of clock signals according to the filtered signal; and

A frequency divider, coupled to the oscillator and the phase detector, is used to generate a frequency-divided signal according to the clock signals, and the frequency divider includes:

a phase selector for receiving said clock signals and outputting an intermediate signal corresponding to a phase characteristic of at least one of said clock signals; and

An adjustable delay circuit, coupled to the phase selector, is used to receive the intermediate signal and generate a frequency-divided signal by delaying the intermediate signal;

Wherein, the input signal corresponds to the frequency division signal.

14. The phase-locked loop as claimed in claim 13, wherein the oscillator is a ring oscillator.

15. The phase-locked loop as claimed in claim 13, wherein the phase-locked loop further comprises:

a controller, coupled to the frequency divider, for controlling the phase characteristic selection of the phase selector included in the frequency divider, and controlling the adjustable delay included in the frequency divider circuit delay.

16. A frequency division method, characterized in that, the frequency division method comprises:

Receive multiple clock signals;

generating an intermediate signal based on a phase characteristic of at least one of said clock signals; and

The intermediate signal is delayed to generate a frequency-divided signal.

17. frequency division method as claimed in claim 16, is characterized in that, the step of generating described intermediate signal comprises:

selectively outputting phase characteristics of said clock signals according to a selection signal; and

By combining the selected phase characteristics, the intermediate signal is generated.

18. The frequency division method according to claim 16, characterized in that, the clock signals are in a delay relationship with each other with a specific time length.

19. The frequency division method according to claim 16, wherein the clock signals are generated by delaying a reference clock signal, and the amount of delay is between 0 and

Wherein, N is the number of these clock signals, and T is the period of the reference clock signal.

20. frequency division method as claimed in claim 19, is characterized in that, the step of delaying described intermediate signal to produce described frequency division signal comprises:

Provides 0 to the intermediate signal amount of delay.