CN101599049B - Method for controlling discontinuous physical addresses of DMA access and DMA controller - Google Patents
Method for controlling discontinuous physical addresses of DMA access and DMA controller Download PDFInfo
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Abstract
The invention discloses a method for controlling discontinuous physical addresses of DMA access. The method comprises the following steps that: physical address boundary registers are configured for two adjacent physical memory blocks, wherein each physical address boundary register corresponds to a hole between the two adjacent physical memory blocks, and is stored with an end physical address of the previous physical memory block and a start physical address of the next physical memory block respectively; and the DMA controller updates the memory address thereof according to the accessed physical address, and compares the updated memory address with the end physical address of the physical memory block, if the updated memory address and the end physical address of the physical memory block are same, the updated memory address is transmitted to the previous physical memory block boundary, the memory address in the DMA controller is updated into the start physical address of the next physical memory block, and data is continuously transmitted and compared until data transmission is completed. Therefore, the method avoids reading failures generated when the DMA controller accesses the physical address without the physical memory block under a condition that the memory physical address is not continuous.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method for controlling a DMA to access a discontinuous physical address and a DMA controller.
Background
In order to increase the data transmission rate, a DMA (Direct Memory Address) is proposed to access and transmit data, that is, within a certain period of time, a DMAC (DMA controller) replaces a CPU (central processing Unit) to obtain a bus control right, so as to realize fast transmission of a large amount of data between different areas of a Memory and an external device or an internal Memory. The DMA transfer includes a byte transfer and a block transfer.
FIG. 1 is a schematic diagram of a typical DMAC, with the DMA controller, CPU, memory, data ports and status/control ports all connected by a bus. When data is transferred from the peripheral device to the memory, data from the input device first enters the data buffer register and then reaches the bus through the data port; control commands from the input device arrive at the DMA request trigger, the DMA request is sent to the DMAC, and the command is ready to arrive at the status/control port to trigger the sending of data to the bus. After receiving DMA request, DMA controller sends HOLD to CPU to require CPU to give up right to use address bus, data bus and related control bus. When transferring one byte, the current address and the content of the current byte counting register are automatically modified until the byte number register is reduced from the set value to 0 to terminate the counting, or the external equipment inputs an EOP (end of process) effective signal to terminate the DMA transfer, and the bus control is handed to the CPU. When data is transferred from the memory to the peripheral device, the process is the reverse of the above-described writing process, and is not described in detail.
Wherein, the DMAC includes: the address register is used for storing a memory address in the data transmission process of the DMA; a counter for counting the transmission bytes; and the control/status register is used for storing the status information of the channel terminated count, the channel with DMA request and the like, so that the CPU can know the DMA status of each channel at any time. The format is shown in table 1:
d3 to D0 are corresponding channels 3-0, and Di ═ 1 indicates that i channel has counted to the end or an additional EOP signal appears; d7 through D4 correspond to channels 3-0, and Di ═ 1 indicates that DMA requests have not yet been processed by channel i-4.
Wherein the address register includes: and the base address register is used for storing the memory head address of the DMA transfer, and the content of the base address register is unchanged in the transfer process. The current address register is used for storing a memory address in the DMA transfer process, and the address is automatically increased by 1 or decreased by 1 (the reading or writing sequence is different, for example, the 1 operation is decreased when the high bit is first and then the low bit is second, and the 1 operation is increased when the low bit is first and then the high bit is first) after each transfer; a base byte counting register for storing the total byte number transferred by the DMA; the current byte register is used for storing the byte which is not transmitted in the DMA transmission process, after each transmission, the byte counter is decreased by 1, and when the value is 0, the byte transmission is finished. The base address register and the current address register are written to a starting address at the same time, which can be used as the first address or the last address of the memory region.
The existing DMA controller has no problem for continuous physical memory movement, but in many cases, due to various requirements of CPU chips, the virtual addresses are continuous in the memory management pool, but the physical addresses are discontinuous, namely the addresses of the physical memory are discontinuous and are in a block. In this case, if the virtual memory is poorly managed, it may happen that the memory move start address provided to the DMA is valid, but the move length has actually passed through the hole, which may cause a portion of the DMA controller to hang up due to accessing a non-existent memory address. As shown in FIG. 2, the virtual address space is on the left and the physical address space is on the right. The virtual addresses on the left side are consecutive from 0x10000000 to 0x 30000000. Wherein the physical address corresponding to 0x 10000000-0 x20000000 is 0x 0-0 x10000000, the physical address corresponding to the virtual address of 0x 20000000-0 x30000000 is 0x 20000000-0 x30000000, and the physical address of 0x 10000000-0 x20000000 is a storage hole and does not correspond to any physical entity. The relationship between the virtual address and the physical address is configured by software personnel according to a register of the CPU.
If the DMA starts to put 1 Kbyte into the virtual address 0x1FFFFF00 (physical address 0x0FFFFF00), at the beginning of transmission, the physical memory of the physical address 0x0FFFFF00 corresponding to the virtual address 0x1FFFFF00 exists, and the DMA can normally operate; however, in the process of transmission, the DMA physical address accesses the range of 0x 10000000-0 x20000000 (0x0FFFFF00+1K is 10000F24), and the DMA read-write failure is caused by the invalid write request because the physical address has no physical memory.
Disclosure of Invention
The invention provides a method for controlling a discontinuous physical address accessed by a DMA (direct memory access) and a DMA controller, which are used for solving the problem that in a system with continuous virtual addresses and discontinuous physical memory addresses, the DMA moves data across the boundary of a physical memory block to cause the read-write failure of the DMA controller.
The invention provides a method for controlling discontinuous physical addresses accessed by a DMA (direct memory access), which comprises the following steps:
configuring a physical address boundary register for two adjacent physical storage blocks to form a corresponding relation between the physical storage blocks and the physical address boundary register, wherein each physical address boundary register corresponds to a hole between the two adjacent physical storage blocks and respectively stores an ending physical address of a previous physical storage block and a starting physical address of a next physical storage block;
the DMA controller updates the memory address according to the accessed physical address, compares the updated memory address with the ending physical address of the physical memory block, if the updated memory address is equal to the ending physical address of the physical memory block, the memory address in the DMA controller is updated to the starting physical address of the next physical memory block, and data transmission and comparison are continued until the data transmission is completed;
the comparing the updated memory address with the ending physical address of the physical memory block specifically includes: the DMA controller determines a corresponding physical storage block according to the initial memory address; the DMA controller acquires an ending physical address of the physical storage block from a physical address boundary register corresponding to the physical storage block according to the corresponding relation between the physical storage block and the physical address boundary register; the DMA controller compares the updated memory address to an ending physical address of the physical memory block.
Wherein, still include:
and if the updated memory address is not equal to the ending physical address of the physical memory block, indicating that the data is not transmitted to the boundary of the last physical memory block, and continuing to transmit data comparison.
The configuring, to two adjacent physical memory blocks, a physical address boundary register to form a corresponding relationship between the physical memory blocks and the physical address boundary register specifically includes:
determining a starting physical address and an ending physical address of each physical memory block;
writing the ending physical address of the first physical memory block and the starting physical address of the second physical memory block into a first physical address boundary register according to the address sequence, writing the ending physical address of the second physical memory block and the starting physical address of the third physical memory block into a second physical address boundary register, and so on; and forming the corresponding relation between the physical storage blocks and the physical address boundary registers.
Wherein the transmitting data comprises: data is written from an external device to a physical memory block or read from said memory block to an external device or transferred between different memory blocks.
The invention provides a DMA controller for controlling the access of a physical memory block comprising at least two discontinuous physical addresses, the DMA controller at least comprises: an address register, a comparison processing module and at least one physical address boundary register,
the physical address boundary register corresponds to a hole between two adjacent physical storage blocks and is used for storing an ending physical address of a previous physical storage block and a starting physical address of a next physical storage block in the two adjacent physical storage blocks;
the address register is used for storing the current memory address and updating the memory address according to the accessed physical address;
the comparison processing module is respectively connected with the address register and the physical address boundary register and is used for comparing the updated memory address with the ending physical address of the last physical memory block in the physical address boundary register, if the updated memory address is equal to the ending physical address of the last physical memory block in the physical address boundary register, the updated memory address is transmitted to the boundary of the physical memory block, the memory address in the address register is updated to the starting physical address of the next physical memory block, and data transmission and comparison are continued;
the comparing and processing module compares the updated memory address with the ending physical address of the physical memory block, specifically: the DMA controller determines a corresponding physical storage block according to the initial memory address; the DMA controller acquires the ending physical address of the physical storage block from a physical address boundary register corresponding to the physical storage block; the DMA controller compares the updated memory address to an ending physical address of the physical memory block.
Wherein,
and the comparison processing module is further configured to, if the updated memory address is not equal to the ending physical address of the physical memory block, indicate that the updated memory address is not transmitted to the boundary of the physical memory block, and continue to transmit and compare the data.
Wherein the transmitting data comprises: data is written to or read from the physical memory block from an external device.
Compared with the prior art, the invention has the following advantages:
in the invention, by setting a physical storage block boundary register and a comparison module, the DMA controller judges whether a physical storage block exceeds a boundary after transmitting data every time, and if the physical storage block exceeds the boundary, other physical storage blocks are selected for data transmission. Therefore, the invention avoids the read-write failure caused by the DMA controller accessing the physical address without the physical memory block under the condition that the physical address of the memory is discontinuous, and increases the flexibility and the reliability of the software memory management design.
Drawings
FIG. 1 is a prior art DMA controller schematic;
FIG. 2 is a prior art mapping of virtual address contiguous physical address discontinuities;
FIG. 3 is a flow chart of a method of controlling DMA access to discontiguous physical addresses in accordance with the present invention;
FIG. 4 is a diagram of a DMA controller of the present invention;
FIG. 5 is a boundary register diagram of a specific application scenario of FIG. 4 in which the present invention is applied;
Detailed Description
The core thought of the invention is as follows: by setting a physical storage block boundary register and a comparison module, the DMA controller judges whether a physical storage block exceeds a boundary after transmitting data every time, and if the physical storage block exceeds the boundary, other physical storage blocks are selected for data transmission. Therefore, the invention avoids the read-write failure caused by the DMA controller accessing the physical address without the physical memory block under the condition that the physical address of the memory is discontinuous.
The following description is directed to the case where the storage is physical memory, and the same is true for other storages having virtual addresses and physical addresses.
The invention provides a method for controlling a DMA to access discontinuous physical addresses, which comprises the following steps as shown in FIG. 3:
For example, if N non-contiguous physical memory blocks are included, N-1 physical address boundary registers are required; the first physical address boundary register stores an ending physical address of the first physical memory block and a starting physical address of the second physical memory block, the second physical address boundary register stores an ending physical address of the second physical memory block and a starting physical address of the third physical memory block, and so on, the (N-1) th physical address boundary register stores an ending physical address of the (N-1) th physical memory block and a starting physical address of the (N) th physical memory block.
Comparing the updated memory address with the ending physical address of the physical memory block specifically includes: the DMA controller determines a corresponding physical storage block according to the initial memory address; the DMA controller acquires the ending physical address of the physical storage block from the physical address boundary register corresponding to the physical storage block according to the corresponding relationship between the physical storage block and the physical address boundary register generated in the step 301; the DMA controller compares the updated memory address to an ending physical address of the physical memory block.
Wherein transmitting data comprises: data is written from an external device to a physical memory block or read from said memory block to an external device or transferred between different memory blocks.
The present invention provides a DMA controller for controlling access to a physical memory block comprising at least two physical addresses that are not consecutive, as shown in fig. 4, the DMA controller at least comprises: an address register 410, a comparison processing module 420 and at least one physical address boundary register 430,
a physical address boundary register 410, corresponding to a hole between two adjacent physical memory blocks, for storing an ending physical address of a previous physical memory block and a starting physical address of a next physical memory block in the two adjacent physical memory blocks;
an address register 420, configured to store a current memory address (physical address) and update the memory address according to an accessed physical address, that is, data is not repeatedly written in the same physical address or data is not repeatedly read out;
and a comparison processing module 430, connected to the address register 410 and the physical address boundary register 420, respectively, and configured to compare the updated memory address with an ending physical address of a previous physical memory block in the physical address boundary register, if the updated memory address is equal to the ending physical address of the previous physical memory block in the physical address boundary register, indicate that the updated memory address has been transmitted to the physical memory block boundary, update the memory address in the address register to a starting physical address of a next physical memory block, and continue to transmit data and compare the updated memory address with the starting physical address of the next physical memory block. Wherein transmitting data comprises: data is written to or read from the physical memory block from an external device. Comparing the updated memory address with the ending physical address of the physical memory block specifically includes: the DMA controller determines a corresponding physical storage block according to the initial memory address; the DMA controller acquires the ending physical address of the physical storage block from a physical address boundary register corresponding to the physical storage block; the DMA controller compares the updated memory address to an ending physical address of the physical memory block.
The comparison processing module 430 is further configured to, if the updated memory address is not equal to the ending physical address of the physical memory block, indicate that the updated memory address is not transferred to the boundary of the physical memory block, continue to transfer data, and perform comparison.
The principle of the implementation method of the DMA controller described in fig. 4 is described in detail with reference to specific scenarios. N physical address boundary registers are added to the DMAC, as shown in fig. 5, to support N +1 non-contiguous physical memory blocks (e.g., memory banks, etc.). Where each physical address boundary register has two physical addresses, A0/A1, A0 being the ending physical address of the last physical memory block, A1 being the starting physical address of the next physical memory block corresponding to A0. For example, the memory includes 3 discontinuous physical storage blocks 1, 2, 3, the starting physical address of physical storage block 1 is 0x0, the ending physical address is 0x10000000, the starting physical address of physical storage block 2 is 0x20000000, the ending physical address is 0x50000000, the starting physical address of physical storage block 3 is 0x60000000, and the ending physical address is 0x 80000000; the physical address boundary register set comprises a physical address boundary register 1 and a physical address boundary register 2, wherein A0 of the physical address boundary register 1 is 0x20000000, and A1 is 0x 30000000; a0 of physical address boundary register 2 is 0x50000000 and A1 is 0x 60000000.
And adding a comparison processing module in the DMAC, comparing the current address register with the first address A0 of the corresponding physical address boundary register after each increment or decrement in the DMA transfer process, if the current address register is the same as the address (namely the boundary of the physical memory block is reached, automatically updating the address in the current address register to be the starting address A1 of the next physical memory block), and then continuing to work. This solves the need for discontinuous movement across physical addresses in hardware. Making DMA applications more versatile.
For example, 1 kbyte is written into physical memory block 1 with physical address 0x0FFFFF00 in physical memory block 1 as the starting address. In this embodiment, a comparison example is described once for each 1 byte written, and in practical applications, comparison may be performed after each data block (N bytes) is written. After writing 1 byte, the current register address is 0x0FFFFF00+1 ═ 0x0fff 01, and the result is different when compared with the ending physical address 0x20000000 of the physical memory block 1, which indicates that the physical address is still valid, and data is continuously written and compared; after writing 100 bytes, the current register address is 0x0FFFFF00+100 ═ 0x10000000, and the result is the same as the result when the ending physical address of the physical memory block 1 is 0x10000000, which indicates that the boundary of the physical memory block 1 has been reached, and if the data is written again, the data is written to a non-existing physical address, resulting in data writing failure; therefore, at this time, the DMAC needs to write the subsequent data into the physical memory block 2, that is, to set the write address to the starting physical address 0x20000000 of the physical memory block 2, and perform data writing.
For another example, the method of the present invention may also be applied to read data from an internal memory to an external device, where the data is stored in the physical memory blocks 1, 2, and 3, 1 kbyte is read from the physical memory block 1 to the external device with the physical address 0x0FFFFF00 in the physical memory block 1 as a start address, and after 1 byte is read, the current register address is 0x0FFFFF00+1 ═ 0x0fff 01, and the result is different from the result obtained by comparing with the end physical address 0x20000000 of the physical memory block 1, which indicates that the physical address is still valid, and the data is continuously read and compared; after 100 bytes are read, the current register address is 0x0FFFFF00+100 ═ 0x10000000, and the result is the same when the end physical address of physical memory block 1 is 0x10000000, which indicates that the boundary of physical memory block 1 has been reached and there is no continuous physical address, resulting in data read failure; therefore, in this case, the DMAC needs to read data from the physical memory block 2, that is, read data at the starting physical address 0x20000000 of the physical memory block 2.
Similarly, the invention is also suitable for transmitting data between two internal memories, namely, reading data from one internal memory and writing the data into the other internal memory, the two internal memories can both comprise discontinuous physical storage blocks, and the read-write ends adopt the scheme of the invention; or only one internal memory comprises non-contiguous physical memory blocks and the other internal memory comprises contiguous physical memory blocks, only one end is required to employ the inventive solution.
Of course, in the embodiment of the present invention, writing or reading is performed in the order from the lower bit to the upper bit of the physical address, and in practical applications, reading or writing may also be performed in the reverse order, which has the same principle and is not described in detail again.
In the invention, by setting a physical storage block boundary register and a comparison module, the DMA controller judges whether a physical storage block exceeds a boundary after transmitting data every time, and if the physical storage block exceeds the boundary, other physical storage blocks are selected for data transmission. Therefore, the invention avoids the read-write failure caused by the DMA controller accessing the physical address without the physical memory block under the condition that the physical address of the memory is discontinuous, and increases the flexibility and the reliability of the software memory management design.
Through the above description of the embodiments, those skilled in the art will clearly understand that the present invention may be implemented by hardware, or by software plus a necessary general hardware platform. Based on such understanding, the technical solution of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments of the present invention.
Those skilled in the art will appreciate that the drawings are merely schematic representations of one preferred embodiment and that the blocks or flow diagrams in the drawings are not necessarily required to practice the present invention.
Those skilled in the art will appreciate that the modules in the devices in the embodiments may be distributed in the devices in the embodiments according to the description of the embodiments, and may be correspondingly changed in one or more devices different from the embodiments. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
The above-mentioned serial numbers of the present invention are for description only and do not represent the merits of the embodiments.
The above disclosure is only for a few specific embodiments of the present invention, but the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.
Claims (7)
1. A method for controlling DMA access to discontiguous physical addresses, comprising the steps of:
configuring a physical address boundary register for two adjacent physical storage blocks to form a corresponding relation between the physical storage blocks and the physical address boundary register, wherein each physical address boundary register corresponds to a hole between the two adjacent physical storage blocks and respectively stores an ending physical address of a previous physical storage block and a starting physical address of a next physical storage block;
the DMA controller updates the memory address according to the accessed physical address, compares the updated memory address with the ending physical address of the physical memory block, if the updated memory address is equal to the ending physical address of the physical memory block, the memory address in the DMA controller is updated to the starting physical address of the next physical memory block, and data transmission and comparison are continued until the data transmission is completed;
the comparing the updated memory address with the ending physical address of the physical memory block specifically includes: the DMA controller determines a corresponding physical storage block according to the initial memory address; the DMA controller acquires an ending physical address of the physical storage block from a physical address boundary register corresponding to the physical storage block according to the corresponding relation between the physical storage block and the physical address boundary register; the DMA controller compares the updated memory address to an ending physical address of the physical memory block.
2. The method of claim 1, further comprising:
and if the updated memory address is not equal to the ending physical address of the physical memory block, indicating that the data is not transmitted to the boundary of the last physical memory block, and continuing to transmit data comparison.
3. The method according to claim 1, wherein the configuring the physical address boundary registers for two adjacent physical memory blocks to form a corresponding relationship between the physical memory blocks and the physical address boundary registers comprises:
determining a starting physical address and an ending physical address of each physical memory block;
writing the ending physical address of the first physical memory block and the starting physical address of the second physical memory block into a first physical address boundary register according to the address sequence, writing the ending physical address of the second physical memory block and the starting physical address of the third physical memory block into a second physical address boundary register, and so on; and forming the corresponding relation between the physical storage blocks and the physical address boundary registers.
4. The method of any of claims 1 to 3, wherein the transmitting data comprises: data is written from an external device to a physical memory block or read from said memory block to an external device or transferred between different memory blocks.
5. A DMA controller for controlling access to a physical memory block comprising at least two physical addresses that are not contiguous, the DMA controller comprising at least: an address register, a comparison processing module and at least one physical address boundary register,
the physical address boundary register corresponds to a hole between two adjacent physical storage blocks and is used for storing an ending physical address of a previous physical storage block and a starting physical address of a next physical storage block in the two adjacent physical storage blocks;
the address register is used for storing the current memory address and updating the memory address according to the accessed physical address;
the comparison processing module is respectively connected with the address register and the physical address boundary register and is used for comparing the updated memory address with the ending physical address of the last physical memory block in the physical address boundary register, if the updated memory address is equal to the ending physical address of the last physical memory block in the physical address boundary register, the updated memory address is transmitted to the boundary of the physical memory block, the memory address in the address register is updated to the starting physical address of the next physical memory block, and data transmission and comparison are continued;
the comparing and processing module compares the updated memory address with the ending physical address of the physical memory block, specifically: the DMA controller determines a corresponding physical storage block according to the initial memory address; the DMA controller acquires the ending physical address of the physical storage block from a physical address boundary register corresponding to the physical storage block; the DMA controller compares the updated memory address to an ending physical address of the physical memory block.
6. The DMA controller of claim 5,
and the comparison processing module is further configured to, if the updated memory address is not equal to the ending physical address of the physical memory block, indicate that the updated memory address is not transmitted to the boundary of the physical memory block, and continue to transmit and compare the data.
7. The DMA controller of claim 5 or 6, wherein the transfer data comprises: data is written to or read from the physical memory block from an external device.
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| CN107678987B (en) * | 2017-10-10 | 2021-06-29 | 郑州云海信息技术有限公司 | Method, device and device for DMA transmission |
| CN114124421B (en) * | 2020-08-31 | 2024-04-12 | 深圳市中兴微电子技术有限公司 | ACL rule processing method, ACL rule processing device, computer equipment and readable medium |
| CN112416811B (en) * | 2020-11-18 | 2024-02-27 | 深圳市硅格半导体有限公司 | Garbage collection method, flash memory and device based on data association degree |
| CN114879584B (en) * | 2022-07-05 | 2022-10-28 | 成都智明达电子股份有限公司 | DMA controller boundary alignment method based on FPGA and circuit thereof |
| CN118426707B (en) * | 2024-07-04 | 2024-11-05 | 合肥康芯威存储技术有限公司 | Storage device and data processing method thereof |
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| CN1794214A (en) * | 2005-12-22 | 2006-06-28 | 北京中星微电子有限公司 | Method of direct storage access for non-volatibility storage and its device |
| CN1804823A (en) * | 2005-12-22 | 2006-07-19 | 北京中星微电子有限公司 | Direct memory access controller |
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| CN1794214A (en) * | 2005-12-22 | 2006-06-28 | 北京中星微电子有限公司 | Method of direct storage access for non-volatibility storage and its device |
| CN1804823A (en) * | 2005-12-22 | 2006-07-19 | 北京中星微电子有限公司 | Direct memory access controller |
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