CN101625495A - Display device with bidirectional scanning mechanism and grid signal scanning method thereof - Google Patents

Abstract

The invention discloses a display device with a bidirectional scanning mechanism, which comprises a plurality of grid lines, a first shift buffer circuit and a second shift buffer circuit. The first shift register circuit includes a plurality of stages of downstream shift registers. The second shift register circuit comprises a plurality of stages of upload shift registers. Each gate line is electrically connected to the corresponding downlink shift register and the corresponding uplink shift register. When the first shift register circuit is enabled, the multi-stage downlink shift registers are used for providing a plurality of downlink gate signals which are sequentially enabled, so as to scan the gate lines according to a first sequence. When the second shift register circuit is enabled, the multi-level upload shift registers are used for providing a plurality of upload gate signals which are sequentially enabled, so as to scan the gate lines according to a second sequence which is reverse to the first sequence. The display device can set different scanning directions according to the embedding modes of different electronic devices, so that the display device is convenient to integrate into various portable electronic devices and can also provide high embedding elasticity.

Description

Display device with bidirectional scanning mechanism and gate signal scanning method thereof

technical field

The invention relates to a display device and its gate signal scanning method, in particular to a display device with a bidirectional scanning mechanism and its gate signal scanning method.

Background technique

A liquid crystal display (Liquid Crystal Display; LCD) is a flat panel display widely used at present, which has the advantages of light and thin appearance, power saving and no radiation. The working principle of the liquid crystal display device is to change the arrangement state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference between the two ends of the liquid crystal layer, so as to change the light transmittance of the liquid crystal layer, and cooperate with the light source provided by the backlight module to display images. Generally speaking, a liquid crystal display device includes a plurality of pixel units, a shift register circuit and a source driver. The source driver is used to provide multiple data signals to multiple pixel units. The shift register circuit is used to generate a plurality of gate signals to feed into a plurality of pixel units to control writing operation of a plurality of data signals.

FIG. 1 is a schematic diagram of a conventional liquid crystal display device. As shown in FIG. 1 , the liquid crystal display device 100 includes a pixel array 101 and a shift register circuit 110 . The shift register circuit 110 includes a multi-stage shift register. For convenience of illustration, the shift register circuit 110 only shows the (N−1)th stage shift register 111 , the Nth stage shift register 112 , and the (N+1)th stage shift register 113 . The shift register 111 of the (N-1)th stage is enabled according to the gate signal SGn-2 to generate the gate signal SGn-1, and the gate signal SGn-1 is used to control the writing of the data signal of the data line DLi The pixel unit 103 of the pixel array 101 is also used to enable the Nth shift register 112 to generate the gate signal SGn. Similarly, the gate signal SGn is not only used to control the writing operation of the pixel unit 104 of the pixel array 101, but also used to enable the (N+1)th stage shift register 113 to generate the gate signal SGn+1, and The gate signal SGn+1 is not only used to control the writing operation of the pixel unit 105 of the pixel array 101 , but also used to enable the next stage shift register to generate the corresponding gate signal.

In the operation of the shift register circuit 110, the multi-level shift register can only scan in one direction, so as to drive a plurality of pixel units in a predetermined order. However, since liquid crystal display devices have been widely integrated in portable electronic devices such as mobile phones, personal digital assistants (PDAs) and small audio-visual players, in order to match the different settings of the internal circuit boards of various portable electronic devices , the embedded liquid crystal display device also requires different display scanning specifications. Therefore, for the current diversified portable electronic devices, the existing liquid crystal display devices with only a unidirectional scanning mechanism cannot provide a display scanning specification with high compatibility, that is, they lack high embedding flexibility.

Contents of the invention

The present invention provides a display device with a bidirectional scanning mechanism, which is used to solve the problem that the existing display device can only provide a unidirectional scanning mechanism, but cannot provide a display scanning specification with high compatibility, that is, lacks high embedding flexibility. question.

According to an embodiment of the present invention, a display device with a bidirectional scanning mechanism is disclosed, including a pixel array, a first shift register circuit, and a second shift register circuit. The pixel array includes a plurality of columns of pixel units and a plurality of gate lines arranged in parallel. A plurality of gate lines are perpendicular to the first direction and arranged sequentially along the first direction, and each gate line is electrically connected to a plurality of pixel units in a corresponding row of pixel units. The first shift register circuit includes a multi-stage downlink shift register. When the first shift register circuit is enabled, the multistage downlink shift register is used to provide a plurality of downlink gates that are enabled sequentially. Pole signals are used to scan a plurality of gate lines, so as to sequentially drive a plurality of rows of pixel units in the first direction. The second shift register circuit includes a multi-stage upload shift register. When the second shift register circuit is enabled, the multi-stage upload shift register is used to provide a plurality of sequentially enabled upload gate signals to A plurality of gate lines are scanned to drive a plurality of columns of pixel units in a sequence of a second direction opposite to the first direction. Each gate line is further electrically connected to a corresponding level of downlink shift register of the first shift register circuit and a corresponding level of uplink shift register of the second shift register circuit.

According to an embodiment of the present invention, it further discloses a gate signal scanning method for a display device. The display device includes a pixel array, a first shift register circuit and a second shift register circuit. The pixel array includes a plurality of rows of pixel units and a plurality of gate lines, the plurality of gate lines are perpendicular to the first direction and arranged in sequence along the first direction, and each gate line is electrically connected to a plurality of pixels of the corresponding row of pixel units unit. The first shift register circuit is used to provide a plurality of sequentially enabled downlink gate signals, so as to sequentially scan a plurality of gate lines in the first direction. The second shift register circuit is used to provide a plurality of sequentially enabled uploading gate signals, so as to scan a plurality of gate lines in a sequence of a second direction opposite to the first direction. This gate signal scanning method includes: supplying power to the display device; detecting the placement state of the display device; when the placement state of the display device is detected as the first placement state, enabling the output of the first shift register circuit A plurality of down-transmitting gate signals are used to scan a plurality of gate lines, so as to sequentially drive a plurality of rows of pixel units in the first direction; and when the arrangement state of the display device is detected as the second arrangement state, enable the first The two shift register circuits output a plurality of upload gate signals to scan a plurality of gate lines, so as to sequentially drive a plurality of rows of pixel units in the second direction.

The present invention also discloses a gate signal scanning method for a display device. The display device includes a pixel array, a first shift register circuit and a second shift register circuit. The pixel array includes a plurality of rows of pixel units and a plurality of gate lines, the plurality of gate lines are perpendicular to the first direction and arranged in sequence along the first direction, and each gate line is electrically connected to a plurality of pixels of the corresponding row of pixel units unit. The first shift register circuit is used to provide a plurality of sequentially enabled downlink gate signals, so as to sequentially scan a plurality of gate lines in the first direction. The second shift register circuit is used to provide a plurality of sequentially enabled uploading gate signals, so as to scan a plurality of gate lines in a sequence of a second direction opposite to the first direction. This gate signal scanning method includes: supplying power to the display device; setting the scan mode of the display device according to the instruction signal; when the scan mode is the first scan mode, enabling the first shift register circuit to output multiple Downlink gate signals to scan a plurality of gate lines, so as to sequentially drive a plurality of columns of pixel units in the first direction; and when the scanning mode is the second scanning mode, enable the second shift register circuit to output multiple A gate signal is uploaded to scan a plurality of gate lines, so as to sequentially drive a plurality of columns of pixel units in the second direction.

The display device of the present invention can set different scanning directions according to its embedding mode in different electronic devices, so it is convenient to be integrated in various portable electronic devices, and can provide high embedding flexibility. In addition, the gate signal scanning method of the present invention can set the desired scanning mode according to the placement state of the display device, thus providing more flexible and convenient applications.

Description of drawings

The drawings described here are used to provide further understanding of the present invention, constitute a part of the application, and do not limit the present invention. In the attached picture:

FIG. 1 is a schematic diagram of a conventional liquid crystal display device.

2A and 2B are schematic views of the first embodiment of the display device of the present invention.

FIG. 3 is a schematic diagram of a second embodiment of the display device of the present invention.

FIG. 4 is a schematic diagram of a third embodiment of the display device of the present invention.

FIG. 5 is a schematic diagram of a fourth embodiment of the display device of the present invention.

FIG. 6 is a schematic diagram of a fifth embodiment of the display device of the present invention.

FIG. 7 is a schematic diagram of a sixth embodiment of the display device of the present invention.

FIG. 8 is a flowchart of a gate signal scanning method according to an embodiment of the invention.

FIG. 9 is a flowchart of another gate signal scanning method according to an embodiment of the present invention.

Figure number:

100 liquid crystal display device

101, 201 pixel array

103, 104, 105, 203, 204, 205, 206 pixel units

110 shift register circuit

111th (N-1) stage shift register

112 Nth stage shift register

113th (N+1) stage shift register

200, 300, 400, 500, 600, 700 display devices

210, 510, 610, 710 first shift register circuit

220, 520 (N-1) level downlink shift register

225, 525 Nth stage downlink shift register

230, 530th (N+1) level downlink shift register

235, 535th (N+2) stage downlink shift register

260, 560, 660, 760 second shift register circuit

270, 570 (M-2) stage upload shift register

275, 575 (M-1) stage upload shift register

280, 580 M-level upload shift registers

285, 585 (M+1) stage upload shift register

290, 390 scan mode control unit

299 grid lines

395, 495 sensing module

396, 496 placement status sensor

397, 497 signal processing unit

521, 526, 531, 536 downlink carry unit

571, 576, 581, 586 upload carry units

800, 900 process

DLi data cable

GL_I-1, GL_I, GL_I+1, GL_I+2 gate lines

S810～S860, S910～S970 steps

SC1 first control signal

SC2 second control signal

SCx control signal

SGB_M-3, SGB_M-2, SGB_M-1, SGB_M, SGB_M+1 upload gate signal

SGF_N-2, SGF_N-1, SGF_N, SGF_N+1, SGF_N+2 downlink gate signal

STF_N-2, STF_N-1, STF_N, STF_N+1, STF_N+2 download start pulse signal

STB_M-3, STB_M-2, STB_M-1, STB_M, STB_M+1 upload start pulse signal

Sind indicator signal

SGn-2, SGn-1, SGn, SGn+1 gate signal

Ss sensing signal

Detailed ways

In order to make the present invention clearer and easier to understand, the display device with a bidirectional scanning mechanism and its gate signal scanning method according to the present invention will be described in detail below with reference to the accompanying drawings, but the provided embodiments are not intended to limit the present invention. The scope covered by the invention, and the step numbers of the method flow are not used to limit the order of execution, any execution flow recombined from the method steps, resulting in a method with equal efficacy, is covered by the present invention.

FIG. 2A is a schematic diagram of a first embodiment of the display device of the present invention. As shown in FIG. 2A , the display device 200 includes a pixel array 201 , a first shift register circuit 210 , a second shift register circuit 260 and a scan mode control unit 290 . The pixel array 201 includes a plurality of columns of pixel units and a plurality of parallel gate lines 299 arranged in sequence along the first direction, wherein only the pixel units 203 of the (I-1)th column, the pixel units 204 of the first column, and the ( The pixel unit 205 in the (I+1)th column, the pixel unit 206 in the (I+2)th column, and the four gate lines GL_I−1˜GL_I+2. The first shift register circuit 210 includes multi-stage downlink shift registers arranged sequentially along the first direction, and the second shift register circuit 260 includes multi-stage downlink shift registers arranged sequentially along the second direction opposite to the first direction. Multi-stage upload shift register. For the convenience of illustration, the first shift register circuit 210 only shows the (N-1)th stage downlink shift register 220, the Nth stage downlink shift register 225, the (N+1)th stage downlink shift register The bit register 230 and the (N+2)th stage downlink shift register 235, the second shift register circuit 260 only shows the (M-2)th stage uplink shift register 270, the (M-1)th stage The stage upload shift register 275 , the Mth stage upload shift register 280 and the (M+1)th stage upload shift register 285 .

The scanning mode control unit 290 is electrically connected to the first shift register circuit 210 and the second shift register circuit 260, and is used to provide the first control signal SC1 and the second control signal SC2 according to the indication signal Sind, wherein the first control signal The signal SC1 is used to enable the first shift register circuit 210 , and the second control signal SC2 is used to enable the second shift register circuit 260 . In another embodiment, as shown in FIG. 2B , the scan mode control unit 290 may only provide a single control signal SCx for controlling the enable operation of the first shift register circuit 210 and the second shift register circuit 260 For example, the first shift register circuit 210 is enabled by using the control signal SCx having a high level, and the second shift register circuit 260 is enabled by using the control signal SCx having a low level. Both the (N-1)th downlink shift register 220 and the (M+1)th uplink shift register 285 are electrically connected to the pixel unit 203 through the gate line GL_I-1, and the Nth downlink shift Both the buffer 225 and the Mth stage upload shift register 280 are electrically connected to the pixel unit 204 through the gate line GL_I, and the (N+1)th stage downlink shift register 230 is connected to the (M-1)th stage upper shift register. The bit registers 275 are electrically connected to the pixel unit 205 through the gate line GL_I+1, and the (N+2)th stage downlink shift register 235 and the (M-2)th stage upload shift register 270 are both connected through the gate line GL_I+1. The pole line GL_I+2 is electrically connected to the pixel unit 206 .

The (N-1)th downlink shift register 220 uses the downlink gate signal SGF_N-2 provided by the previous downlink shift register as a start pulse signal to generate the downlink gate signal SGF_N- 1. The downlink gate signal SGF_N-1 is fed into the pixel unit 203 through the gate line GL_I-1 to control the writing of the data signal of the data line DLi into the pixel unit 203 . The Nth stage downlink shift register 225 is enabled according to the downlink gate signal SGF_N−1 to generate the downlink gate signal SGF_N for controlling the writing operation of the pixel unit 204 . The (N+1)th downlink shift register 230 is enabled according to the downlink gate signal SGF_N to generate the downlink gate signal SGF_N+1 for controlling the writing operation of the pixel unit 205 . The (N+2)th stage downlink shift register 235 is enabled according to the downlink gate signal SGF_N+1 to generate the downlink gate signal SGF_N+2 for controlling the writing operation of the pixel unit 206 . In other words, the first shift register circuit 210 is used to provide a plurality of downstream gate signals enabled in sequence to scan the plurality of gate lines 299 in the first direction, so as to sequentially drive the pixels in the first direction Multiple columns of pixel units in the array 201 .

The (M-2)th stage upload shift register 270 uses the upload gate signal SGB_M-3 provided by the previous stage upload shift register as a start pulse signal to generate the upload gate signal SGB_M-2. The upload gate signal SGB_M- 2 is fed into the pixel unit 206 through the gate line GL_I+2 , so as to control the writing operation of the pixel unit 206 . The (M−1)th stage upload shift register 275 is enabled according to the upload gate signal SGB_M−2 to generate the upload gate signal SGB_M−1 for controlling the writing operation of the pixel unit 205 . The Mth stage upload shift register 280 is enabled according to the upload gate signal SGB_M−1 to generate the upload gate signal SGB_M for controlling the writing operation of the pixel unit 204 . The (M+1)th stage upload shift register 285 is enabled according to the upload gate signal SGB_M to generate the upload gate signal SGB_M+1 for controlling the writing operation of the pixel unit 203 . In other words, the second shift register circuit 260 is used to provide a plurality of upload gate signals enabled in sequence to scan the plurality of gate lines 299 in the second direction, so as to sequentially drive the pixel array in the second direction 201 multi-column pixel units.

From the above, it can be known that the display device 200 can set different scanning directions through the instruction signal Sind according to the embedding modes of the display device 200 in different electronic devices, so it can be easily integrated into various portable electronic devices, and can provide high embedding flexibility.

FIG. 3 is a schematic diagram of a second embodiment of the display device of the present invention. As shown in FIG. 3 , the display device 300 is similar to the display device 200 shown in FIG. 2A . Compared with the display device 200 , the display device 300 further includes a sensing module 395 , and the scan mode control unit 290 is replaced by the scan mode control unit 390 . The sensing module 395 includes a placement sensor (Pose Sensor) 396 and a signal processing unit 397, wherein the placement sensor 396 can be a gravity sensor (Gravity Sensing Device) or an orientation sensor (Orientation Sensor). The placement state sensor 396 is used to sense the placement state of the display device 300 to generate a sensing signal Ss. The signal processing unit 397 is electrically connected to the placement state sensor 396 for performing signal processing on the sensing signal Ss to generate the pre-control signal SCp. The scanning mode control unit 390 is electrically connected to the sensing module 395, the first shift register circuit 210 and the second shift register circuit 260, and is used to generate the first control signal SC1 and the first control signal SCp according to the indication signal Sind or the pre-control signal SCp. The second control signal SC2 further enables the first shift register circuit 210 or the second shift register circuit 260 to scan the plurality of gate lines 299 . That is, the display device 300 can set a required scan mode according to the instruction signal Sind to perform a display operation.

When the display device 300 enters the first scan mode according to the instruction signal Sind, the scan mode control unit 390 outputs the first control signal SC1 to enable the first shift register circuit 210 to scan multiple gates sequentially in the first direction. polar line 299. When the display device 300 enters the second scan mode according to the instruction signal Sind, the scan mode control unit 390 outputs the second control signal SC2 to enable the second shift register circuit 260 to scan a plurality of gates sequentially in the second direction. polar line 299. When the display device 300 enters the sensing setting scan mode according to the instruction signal Sind, if the placement state of the display device 300 is detected as the first placement state, the pre-control signal SCp is used to drive the scan mode control unit 390 to output the first placement state. A control signal SC1 enables the first shift register circuit 210 to sequentially scan the plurality of gate lines 299 in the first direction. Alternatively, if the placement state of the display device 300 is detected as the second placement state, the pre-control signal SCp is used to drive the scanning mode control unit 390 to output the second control signal SC1 to enable the second shift register circuit 260 , so as to sequentially scan the plurality of gate lines 299 in the second direction. Therefore, compared with existing display devices, the display device 300 can provide more flexible and convenient applications.

FIG. 4 is a schematic diagram of a third embodiment of the display device of the present invention. As shown in FIG. 4, the display device 400 is similar to the display device 200 shown in FIG. 2A. Compared with the display device 200 , the display device 400 replaces the scanning mode control unit 290 with a sensing module 495 . The sensing module 495 includes a placement state sensor 496 and a signal processing unit 497 , wherein the placement state sensor 496 can be a gravity sensor or an orientation sensor. The placement state sensor 496 is used to sense the placement state of the display device 400 to generate a sensing signal Ss. The signal processing unit 497 is electrically connected to the placement state sensor 496, and is used to perform signal processing on the sensing signal Ss to generate the first control signal SC1 and the second control signal SC2, thereby enabling the first shift register circuit 210 or the second control signal Two shift register circuits 260 scan a plurality of gate lines 299 . In other words, the display device 400 automatically sets the scan mode to display images according to its placement status, so as to provide more flexible and convenient applications.

FIG. 5 is a schematic diagram of a fourth embodiment of the display device of the present invention. As shown in FIG. 5 , the display device 500 includes a pixel array 201 , a first shift register circuit 510 , a second shift register circuit 560 and a scan mode control unit 290 . The first shift register circuit 510 includes multi-stage downlink shift registers arranged sequentially along the first direction, and the second shift register circuit 560 includes multi-stage uplink shift registers arranged sequentially along the second direction . For the convenience of illustration, the first shift register circuit 510 still only shows the (N-1)th stage downlink shift register 520, the Nth stage downlink shift register 525, the (N+1)th stage downlink shift register The shift register 530 and the (N+2)th stage downlink shift register 535, the second shift register circuit 260 still only shows the (M-2)th stage upload shift register 570, the (M- 1) The stage upload shift register 575 , the Mth stage upload shift register 580 and the (M+1) stage upload shift register 585 . The first shift register circuit 510 and the second shift register circuit 560 are similar to the first shift register circuit 210 and the second shift register circuit 260 shown in FIG. 2A . Compared with the first shift register circuit 210 , each stage of the downlink shift register of the first shift register circuit 510 further includes a downlink carry unit to provide a corresponding downlink start pulse signal. Compared with the second shift register circuit 260 , each stage of the upload shift register of the second shift register circuit 560 further includes an upload carry unit for providing a corresponding upload start pulse signal.

For example, the (N-1)th stage downlink shift register 520 further includes a downlink carry unit 521 to provide the downlink start pulse signal STF_N-1, and the (N+2)th stage downlink shift register 535 further includes a downlink carry unit 536 to provide a downlink start pulse signal STF_N+2, and the (M-2)th stage upload shift register 570 further includes an uplink carry unit 571 to provide an upload start pulse signal STB_N-2, The (M+1)th stage upload shift register 585 further includes an upload carry unit 586 to provide the upload start pulse signal STB_M+1, and the other stages of downlink and upload shift registers can be analogized. Therefore, in the operation of the first shift register circuit 510, each stage of downlink shift register is enabled to generate corresponding The downlink gate signal and the corresponding downlink start pulse signal, for example, the Nth stage downlink shift register 525 is enabled according to the downlink start pulse signal STF_N-1 to generate the downlink gate signal SGF_N and Downlink start pulse signal STF_N. Similarly, in the operation of the second shift register circuit 560, the upload shift register of each stage is enabled to generate the corresponding upload shift register according to the upload start pulse signal provided by the upload shift register of the previous stage. The gate signal and the corresponding upload start pulse signal, for example, the Mth stage upload shift register 580 is enabled according to the upload start pulse signal STB_M-1 to generate the upload gate signal SGB_M and the upload start pulse signal STB_M. The rest of the circuit operation of the display device 500 is the same as that of the display device 200 shown in FIG. 2 , so it will not be repeated here.

FIG. 6 is a schematic diagram of a fifth embodiment of the display device of the present invention. As shown in FIG. 6 , the display device 600 is similar to the display device 300 shown in FIG. 3 . Compared with the display device 300, the display device 600 replaces the first shift register circuit 210 with the first shift register circuit 610, and replaces the second shift register circuit 260 with the second shift register circuit 660 . The internal structure and circuit operation of the first shift register circuit 610 and the second shift register circuit 660 are the same as those of the first shift register circuit 510 and the second shift register circuit 560 shown in FIG. 5 , except that Except for the internal circuit operation of the first shift register circuit 610 and the second shift register circuit 660 , the rest of the circuit operation of the display device 600 is the same as that of the display device 300 , so details will not be repeated here.

FIG. 7 is a schematic diagram of a sixth embodiment of the display device of the present invention. As shown in FIG. 7 , the display device 700 is similar to the display device 400 shown in FIG. 4 . Compared with the display device 400, the display device 700 replaces the first shift register circuit 210 with the first shift register circuit 710, and replaces the second shift register circuit 260 with the second shift register circuit 760 . The internal structure and circuit operation of the first shift register circuit 710 and the second shift register circuit 760 are the same as those of the first shift register circuit 510 and the second shift register circuit 560 shown in FIG. 5 , except that Except for the internal circuit operation of the first shift register circuit 710 and the second shift register circuit 760 , the rest of the circuit operation of the display device 700 is the same as that of the display device 400 , so details are not repeated here.

FIG. 8 is a flowchart of a gate signal scanning method according to an embodiment of the invention. The process 800 shown in FIG. 8 is a gate signal scanning method based on the display device 400 shown in FIG. 4 . The process 800 of the gate signal scanning method includes the following steps:

Step S810: supply power to the display device 400;

Step S820: the sensing module 495 detects whether the display device 400 is placed in a preset placement state, if the display device 400 is detected to be in the default placement state, then execute step S830, otherwise execute step S850;

Step S830: the sensing module 495 outputs the first control signal SC1 to enable the first shift register circuit 210;

Step S840: The first shift register circuit 210 provides a plurality of sequentially enabled downstream gate signals to scan the multi-level gate lines 299 in the first direction, so as to drive the pixel array 201 sequentially in the first direction Multi-column pixel units, execute step S820;

Step S850: the sensing module 495 outputs the second control signal SC2 to enable the second shift register circuit 260; and

Step S860: The second shift register circuit 260 provides a plurality of upload gate signals enabled in sequence to scan the multi-level gate lines 299 in the second direction, so as to sequentially drive the multiple gate lines of the pixel array 201 in the second direction. Column pixel unit, execute step S820.

In the process 800 of the gate signal scanning method, the preset placement state is equivalent to the above-mentioned first placement state, so step S850 and step S860 are used to execute when the display device 400 is placed in the above-mentioned second placement state. Related scanners. In another embodiment, the single control signal SCx shown in the embodiment of FIG. 2B can replace the first control signal SC1 and the second control signal SC2 to control the first shift register circuit 210 and the second shift register circuit 260 The enabling operation, for example, using the control signal SCx with a high level to enable the first shift register circuit 210 and using the control signal SCx with a low level to enable the second shift register circuit 260 . In addition, in another embodiment, if the display device 400, the first shift register circuit 210 and the second shift register circuit 260 are changed to the display device 700, the first shift register circuit 710 and the second shift register circuit The register circuit 760, the gate signal scanning method disclosed in the process 800 is applicable to the display device 700 shown in FIG. 7 .

FIG. 9 is a flowchart of another gate signal scanning method according to an embodiment of the present invention. The process 900 shown in FIG. 9 is a gate signal scanning method based on the display device 300 shown in FIG. 3 . The process 900 of the gate signal scanning method includes the following steps:

Step S910: supply power to the display device 300;

Step S915: the scanning mode control unit 390 sets the scanning mode of the display device 300 according to the instruction signal Sind;

Step S920: determine whether the scanning mode of the display device 300 is the first scanning mode, if the scanning mode of the display device 300 is the first scanning mode, execute step S925, otherwise execute step S935;

Step S925: the scanning mode control unit 390 outputs the first control signal SC1 to enable the first shift register circuit 210;

Step S930: the first shift register circuit 210 provides a plurality of sequentially enabled gate signals to scan the plurality of gate lines 299 in the first direction, so as to drive the pixel array 201 sequentially in the first direction Multi-column pixel units, execute step S915;

Step S935: Determine whether the scanning mode of the display device 300 is the second scanning mode, if the scanning mode of the display device 300 is the second scanning mode, execute step S940, otherwise execute step S950;

Step S940: the scan mode control unit 390 outputs a second control signal SC2 to enable the second shift register circuit 260;

Step S945: The second shift register circuit 260 provides a plurality of upload gate signals enabled in sequence to scan the plurality of gate lines 299 in the second direction, so as to sequentially drive the plurality of pixel arrays 201 in the second direction. Column pixel unit, execute step S915;

Step S950: the sensing module 395 detects whether the display device 300 is placed in a preset placement state, if the display device 300 is detected to be in a preset placement state, then execute step S955, otherwise execute step S965;

Step S955: the sensing module 395 provides the pre-control signal SCp to drive the scan mode control unit 390 to output the first control signal SC1 to enable the first shift register circuit 210;

Step S960: The first shift register circuit 210 provides a plurality of downstream gate signals enabled in sequence to scan the plurality of gate lines 299 in the first direction, so as to drive the pixel array 201 sequentially in the first direction Multi-column pixel units, execute step S915;

Step S965: the sensing module 395 provides the pre-control signal SCp to drive the scan mode control unit 390 to output the second control signal SC2 to enable the second shift register circuit 260; and

Step S970: The second shift register circuit 260 provides a plurality of upload gate signals enabled in sequence to scan the plurality of gate lines 299 in the second direction, so as to sequentially drive the plurality of pixel arrays 201 in the second direction. For the column pixel unit, go to step S915.

In the process 900 of the gate signal scanning method, steps S950-S970 are used to execute related scanning procedures after the display device 300 enters the above-mentioned sensing setting scanning mode, wherein the preset placement state is equivalent to the above-mentioned first placement state , as for step S965 and step S970, it is used to execute the relevant scanning procedure when the display device 300 is placed in the above-mentioned second placement state. In another embodiment, the single control signal SCx shown in the embodiment of FIG. 2B can replace the first control signal SC1 and the second control signal SC2 to control the first shift register circuit 210 and the second shift register circuit 260 The enabling operation, for example, using the control signal SCx with a high level to enable the first shift register circuit 210 and using the control signal SCx with a low level to enable the second shift register circuit 260 . In addition, in another embodiment, if the display device 300, the first shift register circuit 210 and the second shift register circuit 260 are changed to the display device 600, the first shift register circuit 610 and the second shift register circuit The bit register circuit 660, the gate signal scanning method disclosed in the process 900 is applicable to the display device 600 shown in FIG. 6 . Alternatively, if the display device 300 and the scanning mode control unit 390 are changed to the display device 200 and the scanning mode control unit 290, and steps S950-S970 are omitted, then the gate signal scanning method disclosed in the process 900 is applicable to the method shown in FIG. 2A Display device 200. In addition, if the display device 300, the scan mode control unit 390, the first shift register circuit 210, and the second shift register circuit 260 are changed to the display device 500, the scan mode control unit 290, and the first shift register circuit 510 and the second shift register circuit 560, and steps S950˜S970 are omitted, then the gate signal scanning method disclosed in the process 900 is applicable to the display device 500 shown in FIG. 5 .

To sum up, the display device of the present invention can set different scanning directions according to its embedding mode in different electronic devices, so it can be easily integrated into various portable electronic devices, and can provide high embedding flexibility. In addition, the gate signal scanning method of the present invention can set the desired scanning mode according to the placement state of the display device, thus providing more flexible and convenient applications.

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Modification, therefore, the protection scope of the present invention should be defined by the scope of the claims.

Claims (17)

1, a kind of display device of tool bidirectional scanning mechanism is characterized in that, described display device comprises:

One pel array comprises multiple row pixel cell and many gate lines that be arranged in parallel, and described gate line is perpendicular to a first direction, and is provided with in regular turn along described first direction, and each described gate line is electrically connected on a plurality of pixel cells of a respective column pixel cell;

One first shift cache circuit, comprise the multistage offset buffer that passes down, when described first shift cache circuit is enabled, the described multistage offset buffer of biography down is used to provide and passes signals under enable in regular turn a plurality of to scan described gate line, and the order according to described first direction drives described multiple row pixel cell according to this; And

One second shift cache circuit, comprise the multistage offset buffer of uploading, when described second shift cache circuit is enabled, the described multistage offset buffer of uploading is used to provide a plurality of signals of uploading of enabling in regular turn to scan described gate line, and the order according to a second direction that is in reverse to described first direction drives described multiple row pixel cell according to this;

Each gate line of wherein said gate line is electrically connected on a respective stages that passes offset buffer and described second shift cache circuit under the respective stages of described first shift cache circuit in addition and uploads offset buffer.

2, display device as claimed in claim 1 is characterized in that, wherein:

Described pel array comprises an I-1 row pixel cell, an I row pixel cell, an I+1 row pixel cell, an I-1 gate line, an I gate line and an I+1 gate line, described I-1 gate line is electrically connected on a plurality of pixel cells of described I-1 row pixel cell, described I gate line is electrically connected on a plurality of pixel cells of described I row pixel cell, and described I+1 gate line is electrically connected on a plurality of pixel cells of described I+1 row pixel cell.

3, display device as claimed in claim 2 is characterized in that, described first shift cache circuit comprises:

Pass offset buffer under the one N-1 level, be electrically connected on described I-1 gate line, be fed into described I-1 gate line in order to provide a N-1 to pass signal down;

Pass offset buffer under the one N level, be electrically connected under described I gate line and the described N-1 level and pass offset buffer, be used for passing signal down and be fed into described I gate line to provide a N to pass signal down according to described N-1; And

Pass offset buffer under the one N+1 level, be electrically connected under described I+1 gate line and the described N level and pass offset buffer, be used for passing signal down and be fed into described I+1 gate line to provide a N+1 to pass signal down according to described N.

4, display device as claimed in claim 2 is characterized in that, described first shift cache circuit comprises:

Pass offset buffer under the one N-1 level, be electrically connected on described I-1 gate line, pass initial pulse signal down in order to provide a N-1 to pass a signal and a N-1 down, described N-1 passes signal down and is fed into described I-1 gate line;

Pass offset buffer under the one N level, be electrically connected under described I gate line and the described N-1 level and pass offset buffer, be used for passing initial pulse signal down according to described N-1 and pass initial pulse signal down to provide a N to pass a signal and a N down, described N passes signal down and is fed into described I gate line; And

Pass offset buffer under the one N+1 level, be electrically connected under described I+1 gate line and the described N level and pass offset buffer, be used for passing initial pulse signal down and be fed into described I+1 gate line to provide a N+1 to pass signal down according to described N.

5, display device as claimed in claim 4 is characterized in that, wherein:

Pass offset buffer under the described N-1 level and comprise biography carry unit under the N-1 who is electrically connected on biography offset buffer under the described N level, described N-1 passes carry unit down in order to biography initial pulse signal under the described N-1 to be provided; And

Pass offset buffer under the described N level and comprise biography carry unit under the N who is electrically connected on biography offset buffer under the described N+1 level, described N passes carry unit down in order to biography initial pulse signal under the described N to be provided.

6, display device as claimed in claim 2 is characterized in that, described second shift cache circuit comprises:

One M-1 level is uploaded offset buffer, is electrically connected on described I+1 gate line, is fed into described I+1 gate line in order to provide a M-1 to upload signal;

One M level is uploaded offset buffer, is electrically connected on described I gate line and described M-1 level and uploads offset buffer, is used for uploading signal according to described M-1 and is fed into described I gate line to provide a M to upload signal; And

One M+1 level is uploaded offset buffer, is electrically connected on described I-1 gate line and described M level and uploads offset buffer, is used for uploading signal according to described M and is fed into described I-1 gate line to provide a M+1 to upload signal.

7, display device as claimed in claim 2 is characterized in that, described second shift cache circuit comprises:

One M-1 level is uploaded offset buffer, is electrically connected on described I+1 gate line, and in order to provide a M-1 to upload signal and a M-1 uploads initial pulse signal, described M-1 uploads signal and is fed into described I+1 gate line;

One M level is uploaded offset buffer, be electrically connected on described I gate line and described M-1 level and upload offset buffer, be used for uploading initial pulse signal a M to be provided to upload signal and a M uploads initial pulse signal according to described M-1, described M uploads signal and is fed into described I gate line; And

One M+1 level is uploaded offset buffer, is electrically connected on described I-1 gate line and described M level and uploads offset buffer, is used for uploading initial pulse signal according to described M and is fed into described I-1 gate line to provide a M+1 to upload signal.

8, display device as claimed in claim 7 is characterized in that, wherein:

Described M-1 level is uploaded offset buffer and is comprised and be electrically connected on described M level and upload a M-1 of offset buffer and upload carry unit, and described M-1 uploads carry unit and uploads initial pulse signal in order to described M-1 to be provided; And

Described M level is uploaded offset buffer and is comprised and be electrically connected on described M+1 level and upload a M of offset buffer and upload carry unit, and described M uploads carry unit and uploads initial pulse signal in order to described M to be provided.

9, display device as claimed in claim 1 is characterized in that, described display device further comprises:

One scan pattern control module is electrically connected on described first shift cache circuit and described second shift cache circuit, is used for according to an indicator signal so that can described first shift cache circuit or described second shift cache circuit.

10, display device as claimed in claim 1 is characterized in that, described display device further comprises:

One sensing module, it comprises:

One placement state sensor is used for the placement state of the described display device of sensing to produce a sensing signal; And

One signal processing unit is electrically connected on described placement state sensor, is used for carrying out the signal Processing of described sensing signal to produce a preposition control signal; And

One scan pattern control module, be electrically connected on described sensing module, described first shift cache circuit and described second shift cache circuit, be used for according to described preposition control signal or an indicator signal enabling described first shift cache circuit or described second shift cache circuit according to this to produce at least one control signal.

11, display device as claimed in claim 10 is characterized in that, described placement state sensor is a gravity sensor or a direction sensor.

12, display device as claimed in claim 1 is characterized in that, described display device further comprises:

One sensing module is electrically connected on described first shift cache circuit and described second shift cache circuit, is used for the placement state of the described display device of sensing so that can described first shift cache circuit or described second shift cache circuit.

13, display device as claimed in claim 12 is characterized in that, described sensing module comprises:

One placement state sensor is used for the placement state of the described display device of sensing to produce a sensing signal; And

One signal processing unit is electrically connected on described placement state sensor, and the signal Processing that is used for carrying out described sensing signal enables described first shift cache circuit or described second shift cache circuit according to this to produce at least one control signal.

14, display device as claimed in claim 13 is characterized in that, described placement state sensor is a gravity sensor or a direction sensor.

15, a kind of grid signal scanning method is characterized in that, described method comprises:

One display device is provided, and described display device comprises:

One pel array comprises multiple row pixel cell and many gate lines, and described gate line is perpendicular to a first direction, and is provided with in regular turn along described first direction, and each described gate line is electrically connected on a plurality of pixel cells of a respective column pixel cell;

One first shift cache circuit is used to provide a plurality of signals that pass down that enable in regular turn, complies with the described gate line of sequential scanning of described first direction according to this; And

One second shift cache circuit is used to provide a plurality of signals of uploading that enable in regular turn, complies with the described gate line of sequential scanning of a second direction that is in reverse to described first direction according to this;

Power supply is to described display device;

Detect a placement state of described display device;

When the placement state of described display device is detected as one first placement state, enable the described signal that passes down of described first shift cache circuit output to scan described gate line, the order of complying with described first direction according to this drives described multiple row pixel cell; And

When the placement state of described display device is detected as one second placement state, enable the described signal of uploading of described second shift cache circuit output to scan described gate line, the order according to described second direction drives described multiple row pixel cell according to this.

16, a kind of grid signal scanning method is characterized in that, described method comprises:

One display device is provided, and described display device comprises:

One pel array comprises multiple row pixel cell and many gate lines, and described gate line is perpendicular to a first direction, and is provided with in regular turn along described first direction, and each described gate line is electrically connected on a plurality of pixel cells of a respective column pixel cell;

One first shift cache circuit is used to provide a plurality of signals that pass down that enable in regular turn, complies with the described gate line of sequential scanning of described first direction according to this; And

One second shift cache circuit is used to provide a plurality of signals of uploading that enable in regular turn, complies with the described gate line of sequential scanning of a second direction that is in reverse to described first direction according to this;

Power supply is to described display device;

According to an indicator signal to set the one scan pattern of described display device;

When described scan pattern is one first scan pattern, enable the described signal that passes down of described first shift cache circuit output to scan described gate line, the order of complying with described first direction according to this drives described multiple row pixel cell; And

When described scan pattern is one second scan pattern, enable the described signal of uploading of described second shift cache circuit output to scan described gate line, the order according to described second direction drives described multiple row pixel cell according to this.

17, grid signal scanning method as claimed in claim 16 is characterized in that, described method further comprises:

When described scan pattern is sensing setting scan pattern, detect a placement state of described display device;

When the placement state of described display device is detected as one first placement state, enable the described signal that passes down of described first shift cache circuit output to scan described gate line, the order of complying with described first direction according to this drives described multiple row pixel cell; And

When the placement state of described display device is detected as one second placement state, enable the described signal of uploading of described second shift cache circuit output to scan described gate line, the order according to described second direction drives described multiple row pixel cell according to this.

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