CN101674155B - Digital communication device and decoding method - Google Patents

Abstract

A digital communication device and a decoding method. The digital communication device comprises a burst error detector, an inner decoder and an outer decoder. The burst error detector determines the burst noise position corresponding to the data stream according to an error checking equation and generates a burst error indicator accordingly; the inner decoder decodes the data stream to generate an inner decoded stream, the inner decoder comprises an erasure marker for performing an erasure marking procedure on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream; and the outer decoder decodes the inner decoded stream corresponding to the erasure indicator to generate a receiver output. The digital communication device and the decoding method described above can enhance the error correction capability of the communication system.

Description

Digital communication apparatus and coding/decoding method

Technical field

The present invention is relevant for a kind of digital communication apparatus, and is particularly to a kind of enhancement mode erroneous erasure (error-erasure) coding/decoding method and digital communication apparatus that can be applicable to burst (burst) error detection mechanism.

Background technology

In the receiver of prior art, thereby various types of noise, distortion and interference normally cause signal quality deteriorates to cause the factor of output error.Error correction coding (Error-Correcting Coding, ECC) is a kind of current techique that helps receiver to resist above-mentioned factor affecting, and it can reduce wrong probability and strengthen the output the reliability of the data.

Concatenated coding (concatenated coding) is a kind of error correction coding of implementing multilevel coding, for example in-line coding of described multilevel coding (inner coding) and external encode (outer coding).By way of example, convolution code (convolutional code) or Trellis-coded modulation (Trellis-Coded Modulation, TCM) code can be used as internal code, and it helps to overcome the random error of dispersion.And reed-solomon (Reed-Solomon, RS) code or BCH (Bose-Chaudhuri Hocquenghem) code can be used as foreign key, and it helps to overcome burst error.

Fig. 1 is the calcspar for the receiver of the prior art of decoding concatenated code.Receiver 100 shown in Figure 1 comprises demodulator 110, inner decoder 120, deinterleaver 130 and outer decoder 140.Demodulator 110 received RF signal #RF are to produce data flow, described demodulator 110 can comprise following assembly, for example: be used for down-conversion (frequency down conversion) synthesizer (synthesizer), be used for the filter of anti-aliasing (anti-aliasing), the equalizer that is used for the synchronizer of sequential or frequency retrieval and is used for compensation decline or damaging (impairment) channel effect.After part or all of aforesaid operations was performed, demodulator 110 can produce data flow #S.

Depend on and use which kind of internal code, inner decoder 120 can be implemented by convolutional decoder or TCM decoder, and it can carry out the inner decoding program to produce Interior Solutions code stream #I to data flow #S.After inner decoder 120, deinterleaver 130 deinterleaving Interior Solutions code stream #I are to produce deinterleaving stream #D.Deinterleaver 130 is being played the part of important role at the burst noise that disperses some type to share in the error correction burden.

140 pairs of deinterleaving stream of outer decoder #D carries out the external decoder program, and with output receiver output #OUT, and described outer decoder 140 can be implemented by RS decoder or BCH decoder.By way of example, when the RS code was used as foreign key, outer decoder 140 can be implemented by the RS decoder.For (n, k, 2t) RS code, outer decoder 140 maximum recoverable t mistake.In other words, outer decoder 140 has the error correction capability of proofreading and correct t mistake.Yet, in some communication system, especially terrestrial broadcasting (terrestrial broadcasting) system, complicated multipath channel can cause various declines or interference, so the equalizer of demodulator 110 can't full remuneration decline or interference.Under this situation, burst noise can cause inner decoder 120 to make a mistake and be transmitted to outer decoder 140, and deinterleaver 130 also can't be with its effective dispersion.Therefore, for strengthening error correction capability, need to propose a kind of mark (erasure marking) mechanism of wiping.

If demodulator 110 can be detected burst noise, and inner decoder 120 to have unreliable sign flag be the mechanism of wiping designator, then outer decoder 140 can be upgraded to RS erroneous erasure decoder.For (n, k, 2t) RS code, if 2x+y≤2t then wipes for x mistake of RS erroneous erasure decoder recoverable and y.In other words, if be apprised of the position that some are marked as the mistake of wiping, outer decoder 140 possible recoverable factual error numbers surpass the code word (codeword) of t.

Wiping the mark program must detect to carry out based on reliable burst error, yet current burst error detecting mechanism is still for being in the technology of starting stage.Therefore, need to provide a kind of enhancement mode burst error detector.

Summary of the invention

In order to strengthen the error correction capability of communication system, the spy provides following technical scheme:

Embodiments of the present invention provide a kind of digital communication apparatus, are used for decoded data stream to produce receiver output, and described digital communication apparatus comprises burst error detector, inner decoder and outer decoder.The burst error detector is used for determining the burst noise position corresponding with data flow according to the error checking equation, and correspondingly produces the burst error designator; Inner decoder is used for decoded data stream to produce the Interior Solutions code stream, described inner decoder comprises wipes marker, wipe marker and be used for based on the burst error designator inner decoded stream being carried out the mark program of wiping, to produce the designator of wiping corresponding to the Interior Solutions code stream; And outer decoder is coupled to inner decoder, is used for the decoding Interior Solutions code stream corresponding with wiping designator and exports to produce receiver.

Embodiments of the present invention provide a kind of coding/decoding method in addition, be used for decoded data stream to produce receiver output, described coding/decoding method comprises: determine the burst noise position corresponding with data flow according to the error checking equation, and correspondingly produce the burst error designator; Decoded data stream is to produce the Interior Solutions code stream; Based on the burst error designator inner decoded stream is carried out the mark program of wiping, to produce the designator of wiping corresponding to the Interior Solutions code stream; And the decoding Interior Solutions code stream corresponding with wiping designator exported to produce receiver.

Above-described digital communication apparatus and coding/decoding method can strengthen the error correction capability of communication system.

Description of drawings

Fig. 1 is the schematic diagram of receiver in the prior art.

Fig. 2 a is the schematic diagram according to the example of the digital communication apparatus of the embodiment of the invention.

Fig. 2 b is the schematic diagram according to another example of the digital communication apparatus of the embodiment of the invention.

Fig. 3 a is the schematic diagram according to the example of the burst error detector of the embodiment of the invention.

Fig. 3 b is the schematic diagram according to the example of the statistic unit of Fig. 3 a illustrated embodiment.

Fig. 3 c is another example schematic according to the statistic unit of Fig. 3 a illustrated embodiment.

Fig. 4 a is the schematic diagram of internal encoder in the prior art.

Fig. 4 b is the schematic diagram of the example of the associating logical block of internal encoder shown in determining means and the response diagram 4a.

Fig. 5 a is the schematic diagram of another internal encoder in the prior art.

Fig. 5 b is the example schematic according to the contraction binary convolutional encoder of internal encoder shown in Fig. 5 a.

Fig. 5 c is the schematic diagram of example that shrinks the associating logical block of binary convolutional encoder shown in the response diagram 5b.

Fig. 5 d is the schematic diagram according to another example of the contraction binary convolutional encoder of internal encoder shown in Fig. 5 a.

Fig. 6 is the schematic diagram of wiping the example of mark program.

Fig. 7 a is the schematic diagram of the example of outer decoder.

Fig. 7 b is the schematic diagram of another example of outer decoder.

Embodiment

In the middle of specification and claims, used some vocabulary to censure specific element.The person of ordinary skill in the field should understand, and hardware manufacturer may be called same element with different nouns.This specification and claims book not with the difference of title as the mode of distinguishing element, but with the difference of element on function as the criterion of distinguishing.Be an open term mentioned " comprising " in specification and the claim in the whole text, so should be construed to " comprise but be not limited to ".In addition, " couple " word and comprise any means that indirectly are electrically connected that directly reach at this.Therefore, be coupled to the second device if describe first device in the literary composition, then represent first device and can directly be electrically connected in the second device, or indirectly be electrically connected to the second device through other device or connection means.

Fig. 2 a of the present invention is the schematic diagram according to the digital communication apparatus 200a of the embodiment of the invention.In the present embodiment, burst error detector 300 is provided, and detects burst error with the data flow #S based on demodulator 110 outputs.Inner decoder 220 has adopted wipes marker 225, exports with the burst error designator #B based on 300 outputs of burst error detector and wipes designator #E.More specifically, recover the position when (recovered bit) when inner decoder 220 is decoded as data flow #S, wipe marker 225 data flow #S is mapped to corresponding position in symbol level (symbollevel).When Interior Solutions code stream #I being converted to deinterleaving stream #D, deinterleaver 230 also deinterleaving is wiped designator #E, and designator #E ' is wiped in the deinterleaving that exports outer decoder 240a with generation to.Subsequently, outer decoder 240a wipes designator #E ' execution adaptability error-correcting routine based on deinterleaving stream #D and deinterleaving, with output receiver output #OUT.

It should be noted that deinterleaver 230 is optional assembly, it depends on the structure of the conveyer that produces radiofrequency signal #RF.Fig. 2 b is that described digital communication apparatus 200b does not comprise deinterleaver 230 according to the schematic diagram of another digital communication apparatus 200b of the embodiment of the invention.Shown in Fig. 2 b, inner decoder 220 provides Interior Solutions code stream #I and wipes designator #E to outer decoder 240b.Subsequently, outer decoder 240b is based on deinterleaving stream #D and wipe designator #E execution adaptability error-correcting routine, with output receiver output #OUT.Details are as follows in the concrete operations of each mac function.

Fig. 3 a is the schematic diagram of the burst error detector 300 shown in 2a and the 2b figure.Data flow #S is continuous bit stream, and it inputs burst error detector 300 continuously with the specific bit rate.Burst error detector 300 is analyzed data flow #S to produce burst error designator #B, and described burst error designator #B is used for representing burst error whether occurs in the corresponding period.In burst error detector 300, determining means 310 cuts (slices) or quantized data stream #S, and from data flow #S, capture useful position (useful bit) to produce at least one encoding stream #U.Described useful position be for data bit parity check bit (parity bit) or the error checking code (error check code) among the embedding data stream #S together, its form depends on following different encoding schemes.By way of example, data flow #S can is-symbol stream, so determining means 310 can be used as amplitude limiter (slicer) or quantizer (quantizer), and encoding stream #U can be used as coding stream output.Alternatively, if data flow #S is the parallel encoding position, but encoding stream #U serial code bit stream then.

Associating logical block 320 is coupled to the output of determining means 310, be used for based on error checking equation (error-check equation) encoding stream #U being carried out associating logical operation to produce logical value #L, described logical value #L is used for the correctness of the specific a plurality of encoding stream #U of expression specific time period.In the present embodiment, described error checking equation is to draw by the special algorithm relevant with the encoding scheme of digital communication apparatus 200a and 200b enforcement.Described error checking equation can change according to the encoding scheme of implementing, and the known structure of the conveyer that it can be by correspondence predetermines or estimates.Because data flow #S is continuous input, so logical value #L is continuously in each time slot output, and each logical value #L is corresponding to specific a plurality of encoding stream #U.

After associating logical block 320, interior a plurality of logical value #L of period of statistic unit 330 compilings are to produce accumulated value #A.The described period is the one group of continuous slot that is offset in time.Described logical value #L produces at each time slot continuously.Simultaneously, accumulated value #A can preferably be considered as gathering of a plurality of logical value #L in the continuous slot.

Comparator 340 is coupled to statistic unit 330, and whether be used for comparing accumulated value #A and threshold value #th has burst error to occur with detecting.If accumulated value #A surpasses threshold value #th, it is that a particular value (for example logical one) occurs in the near future with the expression burst error that comparator 340 arranges (asserts) with burst error designator #B.On the contrary, if accumulated value #A does not surpass threshold value #th, then burst error designator #B is set to another particular value (for example logical zero).Described threshold value #th can be fixed value, single order (single-level) value or multistage (multi-level) value.It should be noted that alternate manner also may be utilized the threshold value #th that provides suitable.

Fig. 3 b is the schematic diagram according to the statistic unit 330b of Fig. 3 a illustrated embodiment.Standard according to convolution code, encoding stream #U among the data flow #S comes segmentation by code period (period), and in statistic unit 330b, delay line (delay line) 334 is designated to represent described code period (period), described delay line 334 comprises multirow (column), every delegation is corresponding to time slot in the described period, and logical value #L of every delegation storage.Adder 332 is from associating logical block 320 continuous receive logic value #L, with every delegation of accumulated delay line 334.Afterwards, the segment boundary (shrinking border-puncture boundary) of selector 336 detecting encoding stream #U, and output corresponding to the value of the row of the accumulation of described segment boundary (contraction border) with as accumulated value #A.Detect the mechanism of described segment boundary and can be learnt that by different prior aries its detailed description is not given unnecessary details in addition.

In statistic unit 330, the accumulation of every delegation can repeat one or more periods (code period of encoding stream #S) in the delay line 334, has the delegation of minimum initial accumulation results in the selector 336 selectable delay lines 334 as described border.Subsequently, selector 336 is based on described border, exports described accumulation results with as accumulated value #A.

Fig. 3 c is the schematic diagram according to the statistic unit 330c of Fig. 3 a illustrated embodiment.Similarly, the encoding stream #U among the data flow #S comes segmentation by code period (period), and in statistic unit 330c, the initial accumulation results of memory module 344 (for example buffer) storage accumulated value #A.Adder 332 receives initial accumulation results from associating logical block 320 receive logic value #L and from memory module 344,, and correspondingly described addition result is stored in the memory module 344 with as described initial accumulation results logical value #L and the described initial accumulation results addition of each input with continuously.The counter 346 counting periods (code period of encoding stream #S), thus enable the output of the initial accumulation results described in the memory module 344, with as accumulated value #A.Subsequently, counter 346 replacements are stored in the initial accumulation results in the memory module 344.

Fig. 4 a is the schematic diagram of internal encoder 400 in the prior art.Internal encoder 400 is to meet eight level vestigial side bands (8-level Vestigial Sideband, 8-VSB) the TCM block of the conveyer of standard, described internal encoder 400 comprise precoder (pre-coder) 410, trellis encoder (trellis encoder) 420 and symbol mapper (symbol mapper) 436.Precoder 410 receives two information bit stream X ₁With X ₂And produce respectively two bit stream Y ₁With Y ₂Precoder 410 has XOR (XOR) door 402 and delay period is the Delay Element 404 of 12 symbols, and it receives bit stream X ₂To produce bit stream Y ₂Trellis encoder 420 receives two bit stream Y ₁With Y ₂And produce three output bit stream U ₀, U ₁And U ₂Described trellis encoder 420 comprises XOR gate 424 and delay period is the Delay Element 422 and 426 of 12 symbols, and it receives bit stream Y ₁And generation output bit stream U ₀And U ₁Symbol mapper 436 receives three output bit stream U ₀, U ₁And U ₂, and utilize the predetermined symbol mapping ruler of 8-VSB standard definition to produce data flow #S.

In trellis encoder 420, output bit stream U ₀And U ₁By bit stream Y ₁And utilize XOR gate 424 and two Delay Elements 422 and 426 to decide.According to the structure of trellis encoder 420, comprise output bit stream U ₀And U ₁And with bit stream Y ₁Incoherent three equations can be determined that it is expressed as follows:

U ₀[n]＝Q ₀[n-1]； (1)

$Q_0\left[n\right]=U_1\left[n\right]\⊕Q_1[n-1];---\left(2\right)$

Q ₁[n-1]＝U ₀[n-1]， (3)

Wherein, n represents index and each increment corresponding to 12 symbol delay cycles, Q ₀And Q ₁Represent respectively the output of Delay Element 422 and 426.

Therefore, equation

Can derive based on equation (1), (2) and (3) and draw.Correspondingly, the error-detecting equation can determine as follows:

$P\left[n\right]=U_0[n+1]\⊕U_1\left[n\right]\⊕U_0[n-1]---\left(4\right)$

Utilization meets the intrinsic error checking equation (4) of conveyer of 8-VSB standard, can design the device that (error metric) measured in a kind of mistake in computation.P[n] represent when having logical value " 0 " that corresponding encoding stream #U is correct.On the contrary, P[n] represent then when having logical value " 1 " that corresponding encoding stream #U is incorrect.

Fig. 4 b is the schematic diagram of the associating logical block 320a of internal encoder 400 shown in determining means 310a and the response diagram 4a.In associating logical block 320a, Delay Element 405 and the associating logical block 320 shown in the XOR gate 407 pie graph 3a.Determining means 310a and associating logical block 320a are used in the embodiment of Fig. 3 a, to consist of burst error detector 300.

By way of example, the data flow #S that usually is derived from the equalizer of demodulator 110 is input to determining means 310a.The sign map rule that the sign map of the symbol mapper 436 of internal encoder 400 rule is symmetrical among utilization and Fig. 4 a, determining means 310a produces three encoding stream U ₀', U ₁' and U ₂'.If encoding stream U ₀', U ₁' and U ₂' be correct, but then the corresponding symbol among the tentation data stream #S also is correct.Therefore, the Delay Element 405 of associating logical block 320a can be used to reduced equation (4), wherein encoding stream U ₁' be delayed 12 symbols, encoding stream U ₀' be delayed 24 symbols.Subsequently, the encoding stream U of XOR gate 407 receive delays ₀' and U ₁' with execution error inspection operation, the logical value #L of XOR gate 407 outputs then represents error check results.Obviously, in the present embodiment, it is correct that logical value " 0 " representative is set to, logical value " 1 " then represent be set to incorrect.

Fig. 5 a is the schematic diagram of internal encoder 500 in the prior art.Internal encoder 500 is to meet the J.83Annex TCM block of the conveyer of B (hereinafter referred to as J83B) standard of ITU-TRecommendation, it is to utilize 64 quadrature amplitude modulation (Quadrature Amplitude Modulation, QAM) mechanism.In Fig. 5 a, internal encoder 500 receives 7 data flow #Din continuously.Four 7 bit signs (namely 28) that resolver (parser) 540 identifications are one group, and specify " I " component of homophase (in-phase) and " Q " component of quadrature (quadrature).Shown in Fig. 5 a, for the I component, two of resolver 540 output tops (upper) coding stream 502 (I not ₂, I ₅, I ₈, I ₁₁, I ₁₃), 504 (I ₁, I ₄, I ₇, I ₁₀, I ₁₂) and the coding stream 512a (I of bottom (lower) ₀, I ₃, I ₆, I ₉).And for the Q component, two of resolver 540 output tops coding stream 506 (Q not ₂, Q ₅, Q ₈, Q ₁₁, Q ₁₃), 508 (Q ₁, Q ₄, Q ₇, Q ₁₀, Q ₁₂) and the coding stream 512b (Q of bottom ₀, Q ₃, Q ₆, Q ₉).Coding stream 502,504,506 and 508 is not sent to QAM mapper 530, and coding stream 512a and 512b then are sent to differential precoder 510.The position of 510 couples of I of differential precoder and Q is to Q ₀With I ₀, Q ₃With I ₃, Q ₆With I ₆And Q ₉With I ₉Carry out invariable rotary grid coding (rotationally invariant trellis coding).Differential precoder 510 is sent to respectively contraction binary convolutional encoder (punctured binary convolutional encoder) 520a and 520b with bottom stream #X and the #Y (4) of differential coding subsequently.

In the present embodiment, the contraction binary convolutional encoder 520a of 4/5 speed (4/5-rate) and 520b are based on the have punctured codes binary convolutional encoder of 1/2 speed of (punctured code).Usually, in digital communication system, error-correcting code is used to increase redundant (redundancy) to improve noise resisting ability.Under 1/2 speed, shrink binary convolutional encoder 520a and 520b and receive 4 (#X and #Y) and produce 8 bits of coded.In addition, transmit if all bits of coded all are used as load (payload), then load can be because excessive redundancy greatly reduces, and the contractile function that shrinks binary convolutional encoder 520a and 520b application can be used for compensating the minimizing of load.In other words, the transmission of some bits of coded was before agreed by conveyer, and receiver is bypassed (bypassed).Shrink binary convolutional encoder 520a and 520b and meet the J83B standard, it is that per 8 bits of coded transmit 5 positions, is 4/5 thereby cause total contraction code check.That is, produce 5 positions according to 4 input positions.

At last, QAM mapper 530 receives coding stream 502,504 not, 506 and come the encoding stream #U (U of self-constriction binary convolutional encoder 520a and 520b ₁, U ₂, U ₃, U ₄, U ₅) and #V (V ₁, V ₂, V ₃, V ₄, V ₅), and produce 64QAM data flow #S.

Fig. 5 b is the schematic diagram according to the contraction binary convolutional encoder 520a of internal encoder 500 shown in Fig. 5 a.Because it is similar to shrink the structure of binary convolutional encoder 520b and 520a, will be not described in detail so shrink binary convolutional encoder 520b.It should be noted that the error checking equation of deriving in the following discussion is also applicable to shrinking binary convolutional encoder 520b.Shrink binary convolutional encoder 520a and comprise four Delay Elements 555, two XOR gate 524 and 526 and steering gear (commutator) 528.Four previous input position X[0 of four Delay Elements, 555 storages], X[-1], X[-2] and X[-3], have 16 states thereby shrink among the binary convolutional encoder 520a.Shown in Fig. 5 b, code OUT _UAnd OUT _LCan be expressed as follows:

${\mathrm{OUT}}_U=X\left[1\right]\⊕X[-1]\⊕X[-3];---\left(5\right)$

${\mathrm{OUT}}_L=X\left[1\right]\⊕X\left[0\right]\⊕X[-1]\⊕X[-2]\⊕X[-3]---\left(6\right)$

Equation (5) and (6) are by producing code (generating code) G ₁With G ₂Decide, wherein G1=[010101], G2=[011111].It should be noted that different convolution coders has different generation codes.The contractile function of steering gear 528 is to utilize to shrink matrix (puncture matrix) [P1; P2]=[0001; 1111] realize that wherein " 0 " represents that this position do not transmit, " 1 " represents that this position sequentially transmits.

For each grid group (trellis group), shrinking binary convolutional encoder 520a can be from being expressed as X[1], X[2], X[3] and X[4] 4 input positions produce 8 bits of coded.According to shrinking matrix, steering gear 528 selects 5 positions with as encoding stream #U from 8 bits of coded.Herein, group coding stream (for example U[5], U[4], U[3], U[2], U[1]) can be represented as one group of corresponding input position (for example X[4], X[3], X[2], X[1]) with previous input position (X[0], X[-1], X[12], X[-3]) equation.In general, for the n group, 5 carry-out bits can be expressed as follows:

$U[n+1]=X[n+1]\⊕X\left[n\right]\⊕X[n-1]\⊕X[n-2]\⊕X[n-3]$

$U[n+2]=X[n+2]\⊕X[n+1]\⊕X\left[n\right]\⊕X[n-1]\⊕X[n-2]$

$U[n+3]=X[n+3]\⊕X[n+2]\⊕X[n+1]\⊕X\left[n\right]\⊕X[n-1]$

$U[n+4]=X[n+4]\⊕X[n+2]\⊕X\left[n\right]$

$U[n+5]=X[n+4]\⊕X[n+3]\⊕X[n+2]\⊕X[n+1]\⊕X\left[n\right]$

Wherein, n represents index.Except the n group, previous two groups ((n-2) reaches (n-1) group) and follow-up two groups ((n+1) reaches (n+2) group) also lists as follows, with for referencial use:

(n-2) group

$U[n-9]=X[n-7]\⊕X[n-8]\⊕X[n-9]\⊕X[n-10]\⊕X[n-11]$

$U[n-8]=X[n-6]\⊕X[n-7]\⊕X[n-8]\⊕X[n-9]\⊕X[n-10]$

$U[n-7]=X[n-5]\⊕X[n-6]\⊕X[n-7]\⊕X[n-8]\⊕X[n-9]$

$U[n-6]=X[n-4]\⊕X[n-6]\⊕X[n-8]$

$U[n-5]=X[n-4]\⊕X[n-5]\⊕X[n-6]\⊕X[n-7]\⊕X[n-8]$

(n-1) group

$U[n-4]=X[n-3]\⊕X[n-4]\⊕X[n-5]\⊕X[n-6]\⊕X[n-7]$

$U[n-3]=X[n-2]\⊕X[n-3]\⊕X[n-4]\⊕X[n-5]\⊕X[n-6]$

$U[n-2]=X[n-1]\⊕X[n-2]\⊕X[n-3]\⊕X[n-4]\⊕X[n-5]$

$U[n-1]=X\left[n\right]\⊕X[n-2]\⊕X[n-4]$

$U\left[n\right]=X\left[n\right]\⊕X[n-1]\⊕X[n-2]\⊕X[n-3]\⊕X[n-4]$

(n+1) group

$U[n+6]=X[n+5]\⊕X[n+4]\⊕X[n+3]\⊕X[n+2]\⊕X[n+1]$

$U[n+7]=X[n+6]\⊕X[n+5]\⊕X[n+4]\⊕X[n+3]\⊕X[n+2]$

$U[n+8]=X[n+7]\⊕X[n+6]\⊕X[n+5]\⊕X[n+4]\⊕X[n+3]$

$U[n+9]=X[n+8]\⊕X[n+6]\⊕X[n+4]$

$U[n+10]=X[n+8]\⊕X[n+7]\⊕X[n+6]\⊕X[n+5]\⊕X[n+4]$

(n+2) group

$U[n+11]=X[n+9]\⊕X[n+8]\⊕X[n+7]\⊕X[n+6]\⊕X[n+5]$

$U[n+12]=X[n+10]\⊕X[n+9]\⊕X[n+8]\⊕X[n+7]\⊕X[n+6]$

$U[n+13]=X[n+11]\⊕X[n+10]\⊕X[n+9]\⊕X[n+8]\⊕X[n+7]$

$U[n+14]=X[n+12]\⊕X[n+10]\⊕X[n+8]$

$U[n+15]=X[n+12]\⊕X[n+11]\⊕X[n+10]\⊕X[n+9]\⊕X[n+8]$

According to above-mentioned continuous 5 groups carry-out bit, can derive and input the incoherent following equation of an X:

$U[n-6]\⊕U[n-5]\⊕U[n-4]\⊕U[n-3]\⊕U[n-2]\⊕U[n-1]\⊕U[n+1]\⊕U[n+4]\⊕U[n+5]\⊕$

$U[n+8]\⊕U[n+9]\⊕U[n+11]\⊕U[n+12]\⊕U[n+13]\⊕U[n+14]\⊕U[n+15]\≡0$

It also can further be derived as polynomial form, is expressed as:

P(x)＝x*(1+x+x ²+x ³+x ⁴+x ⁶+x ⁷+x ¹⁰+x ¹¹+x ¹⁴+x ¹⁶+x ¹⁷+x ¹⁸+x ¹⁹+x ²⁰+x ²¹) (7)

Utilization meets the intrinsic error checking equation (7) of conveyer of J83B standard, can design the associating logical block 320 shown in Fig. 3 a.

On the other hand, in the receiver of J83B cable system (cable system), owing to do not have training sequence (training sequence), determine that from import (incoming) bit stream into contraction border or punctured position (puctured position) are necessary.As mentioned above, one group 5 output code bits are to produce by 4 input positions, and it shows that the bit stream that imports into of TCM decoder has 5 possible punctured positions in the receiver.Therefore, error checking equation (7) only can be applicable to the correct punctured position (contraction border) in 5 possible punctured positions.

Fig. 5 c is the schematic diagram that shrinks the associating logical block 320b of binary convolutional encoder 520a shown in the response diagram 5b, and it meets the J83B standard and utilizes error checking equation (7) to come the correctness of check data stream #S.In digital communication apparatus 200, radiofrequency signal #RF is received, and demodulated device 110 is demodulated into data flow #S continuously, and present embodiment is to utilize the 64-QAM demodulation mechanism.Associating logical block 320b comprises delay line 560 and XOR gate 562, wherein delay line 560 comprises a plurality of Delay Element D of series connection, and XOR gate 562 has a plurality of inputs, and described a plurality of inputs are coupled to respectively the output of a part of a plurality of Delay Element D of delay line delay line 560.The homophase of determining means 310 receiving data stream #S shown in Fig. 3 a and quadrature component are again to capture the described encoding stream #U of Fig. 5 a and #V.In the present embodiment, only description encoding flows #U.

Encoding stream #U is transferred into associating logical block 320b.In associating logical block 320b, delay line 560 utilizes the finite sequence of a plurality of Delay Element D memory encoding stream #U.In the present embodiment, delay line 560 have 21 Delay Element D with among the memory encoding stream #U from U[n-6] to U[n+14] and sequence.According to error checking equation (7), the output of the 1st (right side), the individual delay cell D in 2,3,4,5,6,8,11,12,15,16,18,19,20,21 (left sides) and the input that present bit is connected to XOR gate 562.XOR gate 562 is carried out xor operation to export a plurality of continuous logical value #L to above-mentioned input continuously.Wherein each logical value #L represents a result of error checking equation (7).

Alternatively, burst error detector 300 can use in the application of all burst error detectings widely.By way of example, Fig. 5 d is depicted as and shrinks binary convolutional encoder 520d, it is to define and have by digital video broadcasting (Digital Video Broadcasting, DVB) standard ETSI EN 300744V1.4.1 (2001-01) to comprise 1/2,2/3 and 3/4 difference contraction code check (punctured code rate).Shrink binary convolutional encoder 520d and comprise 6 Delay Elements 555, two XOR gate 524 and 526 and steering gear 528.6 previous input position X[0 of 6 Delay Elements, 555 storages], X[-1], X[-2], X[-3], X[-4] and X[-5].Shown in Fig. 5 d, the code OUT of input steering gear 528 _UAnd OUT _LCan be expressed as follows:

${\mathrm{OUT}}_U=X\left[1\right]\⊕X\left[0\right]\⊕X[-1]\⊕X[-2]\⊕X[-5];---\left(8\right)$

${\mathrm{OUT}}_L=X\left[1\right]\⊕X[-1]\⊕X[-2]\⊕X[-4]\⊕X[-5]---\left(9\right)$

Three of Europe DVB standard recommendation are shunk code check and comprise 1/2,2/3 and 3/4.According to equation (8), (9) and specific contraction code check, can derive the equation that at least one only comprises carry-out bit and parity check polynominal thereof.For simplicity, the relevant derivation do not given unnecessary details in addition at this.

When the contraction code check was set as 1/2, shrinking sequence [1-up 1-down] can be expressed as:

U[1]＝X[1]+X[0]+X[-1]+X[-2]+X[-5]

U[2]＝X[1]+X[-1]+X[-2]+X[-4]+X[-5]

U[3]＝X[2]+X[1]+X[0]+X[-1]+X[-4]

Similarly, U[4]～U[16] also can be from shrinking retrieval.Therefore, based on U[1]～U[16] can draw following equation:

$U\left[1\right]\⊕U\left[2\right]\⊕U\left[4\right]\⊕U\left[5\right]\⊕U\left[7\right]\⊕U\left[8\right]\⊕U\left[11\right]\⊕U\left[13\right]\⊕U\left[15\right]\⊕U\left[16\right]=0$

The error checking equation also can draw thus, and it can be expressed as:

P(x)＝1+x+x ³+x ⁵+x ⁸+x ⁹+x ¹¹+x ¹²+x ¹⁴+x ¹⁵ (10)

When the contraction code check was set as 2/3, shrinking sequence [1-up 1-down 2-down] can be expressed as:

U[1]＝X[1]+X[0]+X[-1]+X[-2]+X[-5]

U[2]＝X[1]+X[-1]+X[-2]+X[-4]+X[-5]

U[3]＝X[2]+X[0]+X[-1]+X[-3]+X[-4]

U[4]＝X[3]+X[2]+X[1]+X[0]+X[-3]

Similarly, U[5]～U[20] also can be from shrinking retrieval.Therefore, be set as 2/3 U[1 based on shrinking code check]～U[16], can draw following error checking equation:

$U\left[1\right]\⊕U\left[2\right]\⊕U\left[3\right]\⊕U\left[4\right]\⊕U\left[8\right]\⊕U\left[10\right]\⊕U\left[12\right]\⊕U\left[13\right]\⊕U\left[15\right]\⊕U\left[18\right]\⊕$

$U\left[19\right]\⊕U\left[20\right]=0$

Its polynomial form is expressed as:

P(x)＝1+x+x ²+x ⁵+x ⁷+x ⁸+x ¹⁰+x ¹²+x ¹⁶+x ¹⁷+x ¹⁸+x ¹⁹ (11)

Further, when the contraction code check was set as 3/4, shrinking sequence [1-up 1-down 2-down 3-up] can be expressed as:

U[1]＝X[1]+X[0]+X[-1]+X[-2]+X[-5]

U[2]＝X[1]+X[-1]+X[-2]+X[-4]+X[-5]

U[3]＝X[2]+X[0]+X[-1]+X[-3]+X[-4]

U[4]＝X[3]+X[2]+X[1]+X[0]+X[-3]

U[5]＝X[4]+X[3]+X[2]+X[1]+X[-2]

Similarly, U[6]～U[34] also can be from shrinking retrieval.Therefore, be set as 2/3 U[1 based on shrinking code check]～U[16], described equation can be expressed as follows:

$U\left[1\right]\⊕U\left[2\right]\⊕U\left[3\right]\⊕U\left[4\right]\⊕U\left[7\right]\⊕U\left[10\right]\⊕U\left[14\right]\⊕U\left[15\right]\⊕U\left[16\right]\⊕U\left[24\right]\⊕$

$U\left[28\right]\⊕U\left[29\right]\⊕U\left[31\right]\⊕U\left[32\right]\⊕U\left[33\right]\⊕U\left[34\right]=0$

Its polynomial form is:

P(x)＝1+x+x ²+x ³+x ⁵+x ⁶+x ¹⁰+x ¹⁸+x ¹⁹+x ²⁰+x ²⁴+x ²⁷+x ³⁰+x ³¹+x ³²+x ³³ (12)

Obviously, the structure that Fig. 5 c advises can be modified, with the different error checking equations of embodiment such as (10), (11) and (12).

Fig. 6 is the schematic diagram by the example of wiping the mark program of wiping marker 225 enforcements of 2a and 2b figure.The top of Fig. 6 is the state of burst error designator #B.At cycle C ₁In, burst error designator #B is high (high), showing has burst error to occur.At cycle C ₂In, burst error designator #B is low (low), showing does not have burst error to occur.

By way of example, the inner decoder 220 of 2a and 2b figure can adopt viterbi algorithm (Viterbi Algorithm) with decoded data stream #S, Fig. 6 middle part is from the remaining path (survivor path) of finding out (trace back) program of recalling of carrying out by inner decoder 220, and wherein Interior Solutions code stream #I is used for decoding.The described mark program of wiping is to carry out at Veterbi decoding program run duration.Because cycle C ₁In burst error appears, it needs higher standard to decide to wipe.Represent the state of mark with hypographous node (shadowed node).On the contrary, because cycle C ₂In burst error does not appear, it can use lower standard to decide and wipe.The bottom of Fig. 6 is the signal condition of wiping designator #E, and it is to determine according to the mark on the remaining path in the grid chart (Trellis diagram).If remaining path Last status is labeled, that wipes then that marker 225 sends logical one wipes designator #E.On the contrary, if remaining path Last status is not labeled, that wipes then that marker 225 sends logical zero wipes designator #E.

Embodiment shown in Figure 6 can enable the outer decoder 240a of Fig. 2 a, to flow #D according to unreliable position decoding deinterleaving, wherein, described unreliable position has been deinterlaced wipes designator #E ' and is defined as the erasure location corresponding with deinterleaving stream #D, and deinterleaving to wipe designator #E ' be that the deinterleaver 230 of Fig. 2 a is wiped designator #E by deinterleaving and produced.Similarly, embodiment shown in Figure 6 can be used for the outer decoder 240b of Fig. 2 b, has been wiped free of the unreliable position decoding Interior Solutions code stream #I that designator #E is defined as the erasure location corresponding with Interior Solutions code stream #I with basis.

Fig. 7 a is the schematic diagram according to the outer decoder 240a of the embodiment of the invention, and described outer decoder 240a is used for Correction Solution weaving flow #D to produce receiver output #OUT.Deinterleaving stream #D is (n, k, 2t) RS code signal.Outer decoder 240a comprises the first error correction unit 710, the second error correction unit 720 and multiplexer 730.As mentioned above, digital communication apparatus 200a among Fig. 2 a is the cascaded code receiver, the operation of wiping marker 225 is the burst error positions that determine according to by the burst error detector 300 that is coupled to demodulator 110, and the unreliable position among designator #E ' the expression deinterleaving stream #D is wiped in the deinterleaving that is produced by deinterleaver 130 during the execution decoding.

Externally among the decoder 240a, 710 decoding deinterleaving stream #D are to produce the first initial output #O1 for the first error correction unit.Because it is irrelevant that designator #E ' is wiped in the operation of the first error correction unit 710 and deinterleaving, therefore, may incorrectly wipe the performance that the mark program can not affect the first error correction unit 710 by what wipe marker 225 execution.T mistake in the first error correction unit 710 maximum each code word of recoverable.On the other hand, the second error correction unit 720 is wiped designator #E ' decoding deinterleaving stream #D to produce the second initial output #O2 according to deinterleaving.More specifically, by deinterleaving being wiped the definite unreliable position of designator #E ' as erasure location, the second error correction unit 720 decoding deinterleaving stream #D.If 2x+y≤2t, then x mistake in code word and y is individual wipes and can successfully be proofreaied and correct.That is, wipe the extraneous information that designator #E ' provides by deinterleaving, wipe for the second error correction unit 720 maximum recoverable 2t.In other words, if all errors presents all are wiped free of marker 225 and determine exactly to be erasure location in the code word, and there is not incorrect erasure location to be labeled, the second error correction unit 720 maximum recoverable 2t mistake, it is equivalent to the twice of the first error correction unit 710 calibration capabilities.

In the present embodiment, but the first error correction unit 710 and 720 parallel runnings of the second error correction unit.For each code word among the deinterleaving stream #D, the first error correction unit 710 and the second error correction unit 720 all can attempt decoding described code word to produce respectively the first initial output #O1 and the second initial output #O2.Guarantee the calibration capability of outer decoder 240a when such scheme can be no more than t in the number of errors that a code word among the #D is flowed in deinterleaving, and strengthen the calibration capability of outer decoder 240a when the number of errors of a code word surpasses t in deinterleaving stream #D.

In addition, when the code word of decoding deinterleaving stream #D, the first error correction unit 710 further produces the first sign #f1, whether to represent that each code word is all successfully proofreaied and correct by the first error correction unit 710 among the deinterleaving stream #D.Similarly, when the code word of designator #E ' decoding deinterleaving stream #D was wiped in the foundation deinterleaving, the second error correction unit 720 also produced the second sign #f2, whether to represent that each code word is all successfully proofreaied and correct by the second error correction unit 720 among the deinterleaving stream #D.According to the first sign #f1 and the second sign #f2, multiplexer 730 select the first initial output #O1 and the second initial output #O2 one of them with as receiver output #OUT.

Because the first error correction unit 710 is relatively reliable decoder, and its performance can not be subject to may be by the incorrect impact of wiping the mark program of wiping marker 225 execution, therefore, as long as the first sign #f1 represents deinterleaving and flows #D and successfully proofreaied and correct to produce the first initial output #O1 by the first error correction unit 710 that then multiplexer 730 can select the first initial output #O1 to export #OUT as receiver.

In the present embodiment, to be not limited only to be necessary assembly to deinterleaver 230.In general, deinterleaver 230 is placed in before the input of the first error correction unit 710 and the second error correction unit 720, with the Interior Solutions code stream #I of deinterleaving before inputting the first error correction unit 710 and the second error correction unit 720 at deinterleaving stream #D from inner decoder 220, and deinterleaving wipes designator #E, wipes designator #E ' and it is provided to the second error correction unit 720 thereby produce deinterleaving.Alternatively, shown in Fig. 2 b, outer decoder 240b is connected directly to inner decoder 220, is not deinterleaving stream #D to process Interior Solutions code stream #I.

Fig. 7 b is the schematic diagram that is similar to the outer decoder 240b of Fig. 7 a illustrated embodiment.Outer decoder 240b adopts in the embodiment shown in Fig. 2 b, and it moves based on wiping designator #E and Interior Solutions code stream #I, and deinterleaver 230 is omitted in Fig. 2 b.The first error correction unit 710 decoding Interior Solutions code stream #I initially export #O1 to produce first, and the second error correction unit 720 is according to wiping designator #E decoding Interior Solutions code stream #I to produce the second initial #O2 of output.More specifically, by wiping the definite unreliable position of designator #E as erasure location, the second error correction unit 720 decoding deinterleavings stream #D.When the code word of decoding Interior Solutions code stream #I, the first error correction unit 710 further produces the first sign #f1, whether to represent that each code word is all successfully proofreaied and correct by the first error correction unit 710 among the Interior Solutions code stream #I.Similarly, when when wiping the code word of designator #E decoding Interior Solutions code stream #I, the second error correction unit 720 also produces the second sign #f2, whether to represent that each code word is all successfully proofreaied and correct by the second error correction unit 720 among the Interior Solutions code stream #I.According to the first sign #f1 and the second sign #f2, multiplexer 730 select the first initial output #O1 and the second initial output #O2 one of them with as receiver output #OUT.Based on the associated description of the above outer decoder 240a, those skilled in the art should know outer decoder 240b and how carry out described operation and function.Therefore, its operation and function is described in detail in this and does not give unnecessary details in addition.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (27)

1. a digital communication apparatus is used for decoded data stream to produce receiver output, and this digital communication apparatus comprises:

The burst error detector is used for determining the burst noise position corresponding with this data flow according to the error checking equation, and correspondingly produces the burst error designator;

Inner decoder, be used for this data flow of decoding to produce the Interior Solutions code stream, this inner decoder comprises wipes marker, and this wipes marker for based on this burst error designator this Interior Solutions code stream being carried out the mark program of wiping, to produce the designator of wiping corresponding to this Interior Solutions code stream; And

Outer decoder is coupled to this inner decoder, is used for decoding and wipes this Interior Solutions code stream corresponding to designator to produce this receiver output with this.

2. digital communication apparatus as claimed in claim 1 is characterized in that: this is wiped marker and adopts a plurality of decision standards according to this burst error designator one of them wipes the mark program to carry out this, wipes designator to produce this.

3. digital communication apparatus as claimed in claim 1 is characterized in that:

When this burst error designator of this burst error detector was set to the first value, this was wiped marker and adopts the first decision standard to wipe the mark program so that this Interior Solutions code stream is carried out this; And

When this burst error designator of this burst error detector was set to the second value, this was wiped marker and adopts the second decision standard to wipe the mark program so that this Interior Solutions code stream is carried out this.

4. digital communication apparatus as claimed in claim 1, more comprise deinterleaver, be coupled to this inner decoder and this outer decoder, this Interior Solutions code stream of this deinterleaver deinterleaves and this are wiped designator, to produce respectively deinterleaving stream and to wipe designator corresponding to the deinterleaving of this deinterleaving stream, wherein this outer decoder is decoded and is wiped this deinterleaving stream of designator corresponding to this deinterleaving, to produce this receiver output.

5. digital communication apparatus as claimed in claim 1, it is characterized in that: this outer decoder comprises:

The first error correction unit is used for proofreading and correct this Interior Solutions code stream to produce the first initially output;

The second error correction unit is used for proofreading and correct corresponding to this this Interior Solutions code stream of wiping designator to produce the second initially output; And

Multiplexer is coupled to this first error correction unit and this second error correction unit, be used for to select this first initial output and this second initial output one of them with as this receiver output.

6. digital communication apparatus as claimed in claim 5 is characterized in that: wipe unreliable position that designator indicates by this and be set to erasure location corresponding to this Interior Solutions code stream, this second error correction unit this Interior Solutions code stream of decoding.

7. digital communication apparatus as claimed in claim 6 is characterized in that:

This first error correction unit more produces the first sign, and whether this first sign is used for this Interior Solutions code stream of expression and is successfully proofreaied and correct by this first error correction unit;

This second error correction unit more produces the second sign, and whether this second sign is used for this Interior Solutions code stream of expression and is successfully proofreaied and correct by this second error correction unit; And

This multiplexer according to this first sign and this second sign select this first initial output and this second initial output one of them, with as this receiver output.

8. digital communication apparatus as claimed in claim 1, it is characterized in that: these data stream conforms eight level vestigial side band standards, this data flow comprises parallel encoding position U ₀, U ₁And U ₂, U wherein ₀Represent U ₁Parity check, be expressed as:

$U_0[n+1]=U_1\left[n\right]\⊕U_0[n-1],$ Wherein n represents time slot, operator

Represent xor operation; And

This error checking equation is expressed as:

$P\left[n\right]=U_0[n+1]\⊕U_1\left[n\right]\⊕U_0[n-1],$ P[n wherein] represent logical value, when this logical value was 0, the encoding stream that represents this data flow was correct, when this logical value is 1, represented that this encoding stream of this data flow is wrong.

9. digital communication apparatus as claimed in claim 1, it is characterized in that: this data stream conforms ITU-TRecommendation is the B standard J.83Annex, this error checking equation is parity check polynominal P[x], it is expressed as:

P(x)＝x*(1+x+x ²+x ³+x ⁴+x ⁶+x ⁷+x ¹⁰+x ¹¹+x ¹⁴+x ¹⁶+x ¹⁷+x ¹⁸+x ¹⁹+x ²⁰+x ²¹)。

10. digital communication apparatus as claimed in claim 1 is characterized in that: this data stream conforms digital video-frequency broadcast standard, this error checking equation is parity check polynominal P[x], when the code check of this data flow was 1/2, it was expressed as:

P(x)＝1+x+x ³+x ⁵+x ⁸+x ⁹+x ¹¹+x ¹²+x ¹⁴+x ¹⁵，

When the code check of this data flow was 2/3, it was expressed as:

P(x)＝1+x+x ²+x ⁵+x ⁷+x ⁸+x ¹⁰+x ¹²+x ¹⁶+x ¹⁷+x ¹⁸+x ¹⁹，

When the code check of this data flow was 3/4, it was expressed as:

P(x)＝1+x+x ²+x ³+x ⁵+x ⁶+x ¹⁰+x ¹⁸+x ¹⁹+x ²⁰+x ²⁴+x ²⁷+x ³⁰+x ³¹+x ³²+x ³³。

11. digital communication apparatus as claimed in claim 1 is characterized in that: this burst error detector comprises:

Determining means receives this data flow to produce at least one encoding stream;

The associating logical block is coupled to this determining means, is used for based on this error checking equation this encoding stream being carried out associating logical operation, to produce the logical value of the correctness that is used for this encoding stream of expression;

Statistic unit is coupled to this associating logical block, is used for interior a plurality of continuous logic values of period of compiling, to produce accumulated value; And

Comparator is coupled to this statistic unit, is used for relatively this accumulated value and threshold value, is used for this burst error designator whether expression occurs corresponding to the burst error of this period to produce.

12. digital communication apparatus as claimed in claim 11 is characterized in that: this associating logical block comprises:

Delay line has a plurality of Delay Elements of series connection, is used for the finite sequence of this data flow of storage; And

XOR gate has a plurality of inputs, receives alternatively the output of these a plurality of Delay Elements to implement this error checking equation, and wherein the output of these chosen a plurality of Delay Elements is carried out xor operation to produce this logical value.

13. digital communication apparatus as claimed in claim 11 is characterized in that: this statistic unit comprises:

Delay line comprises multirow, is used for a plurality of initial accumulation results of this accumulated value of storage, and wherein every delegation is corresponding to time slot in this period;

Adder, recurrence is also accumulated the logical value that every delegation inputs successively continuously; And

Selector is used for the border of this data flow of detecting, and based on these these a plurality of initial accumulation results of border output one of them, with as this accumulated value.

14. digital communication apparatus as claimed in claim 13, it is characterized in that: when this cumulative operation of every delegation repeats at least one period, this selector selects to have in this multirow the delegation of minimum initial accumulation results as this border, and according to this this initial accumulation results of border output with as this accumulated value.

15. digital communication apparatus as claimed in claim 11 is characterized in that: this statistic unit comprises:

Adder is used for uniting from this each continuous input logic value and initial accumulation results addition of logical block, with as this initial accumulation results;

Memory module is used for storage from this accumulation results of this adder; And

Counter is used for enabling the output of this this initial accumulation results of memory module, with will this initial accumulation results as this accumulated value of each period.

16. digital communication apparatus as claimed in claim 11 more comprises demodulator, is used for received RF signal and this radiofrequency signal of demodulation, to produce this data flow.

17. a coding/decoding method is used for decoded data stream to produce receiver output, this coding/decoding method comprises:

Determine the burst noise position corresponding with this data flow according to the error checking equation, and correspondingly produce the burst error designator;

This data flow of decoding is to produce the Interior Solutions code stream;

Based on this burst error designator this Interior Solutions code stream is carried out the mark program of wiping, to produce the designator of wiping corresponding to this Interior Solutions code stream; And

Decoding is wiped this Interior Solutions code stream corresponding to designator to produce this receiver output with this.

18. coding/decoding method as claimed in claim 17 is characterized in that: this is wiped the mark program and comprises: one of them wipes the mark program to carry out this to adopt a plurality of decision standards according to this burst error designator, wipes designator to produce this.

19. coding/decoding method as claimed in claim 17 more comprises:

When this burst error designator is set to the first value, adopt the first decision standard to wipe the mark program so that this Interior Solutions code stream is carried out this; And

When this burst error designator is set to the second value, adopt the second decision standard to wipe the mark program so that this Interior Solutions code stream is carried out this.

20. coding/decoding method as claimed in claim 17 more comprises:

This Interior Solutions code stream of deinterleaving and this are wiped designator, to produce respectively deinterleaving stream and to wipe designator corresponding to the deinterleaving of this deinterleaving stream; And

This deinterleaving that decoding is wiped designator corresponding to this deinterleaving is flowed, to produce this receiver output.

21. coding/decoding method as claimed in claim 17 is characterized in that: the step of this deinterleaving stream of decoding comprises:

This Interior Solutions code stream is carried out the first error correction, to produce the first initially output;

This Interior Solutions code stream is carried out the second error correction, to produce the second initially output; And

Select this first initial output and this second initial output one of them with as this receiver output.

22. coding/decoding method as claimed in claim 21 is characterized in that: this second error correction comprises: wipe unreliable position that designator indicates by this and be set to erasure location corresponding to this Interior Solutions code stream, this Interior Solutions code stream of decoding.

23. coding/decoding method as claimed in claim 17 is characterized in that: these data stream conforms eight level vestigial side band standards, this data flow comprises parallel encoding position U ₀, U ₁And U ₂, U wherein ₀Represent U ₁Parity check, be expressed as:

$U_0[n+1]=U_1\left[n\right]\⊕U_0[n-1],$ Wherein n represents time slot, operator

Represent xor operation; And

This error checking equation is expressed as:

$P\left[n\right]=U_0[n+1]\⊕U_1\left[n\right]\⊕U_0[n-1],$ P[n wherein] represent logical value, when this logical value was 0, the encoding stream that represents this data flow was correct, when this logical value is 1, represented that this encoding stream of this data flow is wrong.

24. coding/decoding method as claimed in claim 17 is characterized in that: this data stream conforms ITU-TRecommendation is Annex B standard J.83, and this error checking equation is parity check polynominal P[x], it is expressed as:

P(x)＝x*(1+x+x ²+x ³+x ⁴+x ⁶+x ⁷+x ¹⁰+x ¹¹+x ¹⁴+x ¹⁶+x ¹⁷+x ¹⁸+x ¹⁹+x ²⁰+x ²¹)。

25. coding/decoding method as claimed in claim 17 is characterized in that: this data stream conforms digital video-frequency broadcast standard, this error checking equation is parity check polynominal P[x], when the code check of this data flow was 1/2, it was expressed as:

P(x)＝1+x+x ³+x ⁵+x ⁸+x ⁹+x ¹¹+x ¹²+x ¹⁴+x ¹⁵，

When the code check of this data flow was 2/3, it was expressed as:

P(x)＝1+x+x ²+x ⁵+x ⁷+x ⁸+x ¹⁰+x ¹²+x ¹⁶+x ¹⁷+x ¹⁸+x ¹⁹，

When the code check of this data flow was 3/4, it was expressed as:

P(x)＝1+x+x ²+x ³+x ⁵+x ⁶+x ¹⁰+x ¹⁸+x ¹⁹+x ²⁰+x ²⁴+x ²⁷+x ³⁰+x ³¹+x ³²+x ³³。

26. coding/decoding method as claimed in claim 17 is characterized in that: the step that determines this burst noise position comprises:

Receive this data flow to produce at least one encoding stream;

Based on this error checking equation this encoding stream is carried out associating logical operation, to produce the logical value of the correctness that is used for this encoding stream of expression;

Compile a plurality of continuous logic values in the period, to produce accumulated value; And

Relatively this accumulated value and threshold value are used for this burst error designator whether expression occurs corresponding to the burst error of this period to produce.

27. coding/decoding method as claimed in claim 17 more comprises:

This radiofrequency signal of received RF signal and demodulation is to produce this data flow.

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