CN101677067B - Manufacturing method of copper core layer multilayer packaging substrate - Google Patents

Abstract

A method for manufacturing a copper core layer multi-layer packaging substrate is a single-sided, multi-layer packaging substrate which is manufactured based on a copper core substrate. The structure includes a thick copper plate with high rigidity support, and one side of the thick copper plate has build-up circuit and the other side has ball side pattern barrier layer. The build-up circuits and the connection between the chip-placing side and the ball side are conducted by a plurality of plated blind holes and buried holes. Therefore, the packaging substrate of the invention is characterized by having high-density build-up circuit to provide the winding wire required by the connection of electronic components, and simultaneously using thick copper plate to provide enough rigidity to make the packaging process easier. Therefore, the multilayer packaging substrate manufactured by the invention can form the copper core layer multilayer packaging substrate with the copper core substrate support according to the actual requirement, and can effectively achieve the purposes of improving the bending problem of the ultrathin core layer substrate plate, simplifying the manufacturing process of the traditional build-up circuit board and further improving the reliability of the packaging body when the packaging body is jointed with the substrate.

Description

Manufacturing method of copper core layer multilayer packaging substrate

Technical field:

The invention relates to a method for manufacturing a multilayer encapsulation substrate with a copper core layer, in particular to a method for manufacturing a single-sided, multilayer encapsulation substrate based on the copper core substrate.

Background technique:

In the production of general multi-layer packaging substrates, the production method usually starts with a core substrate, and then completes a double-sided structure of the inner core board through drilling, electroplating, plug holes, and double-sided circuit production. A multi-layer packaging substrate is then completed through a circuit build-up process. As shown in FIG. 22 , it is a schematic cross-sectional view of a packaging substrate with a nuclear layer. First, a core substrate 60 is prepared, wherein the core substrate 60 is composed of a core layer 601 with a predetermined thickness and a circuit layer 602 formed on the surface of the core layer 601, and several electroplated vias are formed in the core layer 601. The hole 603 can be used to connect the circuit layer 602 on the surface of the core layer 601 .

Next, as shown in FIGS. 23 to 26 , a circuit build-up process is performed on the core substrate 60 . First, a first dielectric layer 61 is formed on the surface of the core substrate 60, and several first openings 62 are formed on the surface of the first dielectric layer 61 to expose the circuit layer 602; A seed layer 63 is formed on the exposed surface of the first dielectric layer 61 in a manner, and a patterned resist layer 64 is formed on the seed layer 63, and a plurality of second openings 65 are formed in the patterned resist layer 64 , to expose part of the seed layer 63 forming the patterned circuit; then, form a first patterned circuit layer 66 and several conductive blind holes 67 in the second opening 65 by electroplating, and make the first pattern The patterned circuit layer 66 can be electrically connected to the circuit layer 602 of the core substrate 60 through the several conductive blind holes 67, and then the patterned resist layer 64 is removed and etched, and a first circuit is formed after completion. Build-up structure 6a. Similarly, this method can be used to form a second dielectric layer 68 and a second patterned circuit layer 69 on the outermost layer surface of the first circuit build-up structure 6a in the same way. 6b, forming a multi-layer packaging substrate by step-by-step build-up. However, this manufacturing method has disadvantages such as low wiring density, many layers, and complicated process.

In addition, there is also a method of using a thick copper metal plate as the core material. After an inner core plate is completed by etching and plugging, a multi-layer packaging substrate can be completed through a circuit build-up process. As shown in FIGS. 27 to 29 , they are schematic cross-sectional views of another encapsulation substrate with a nucleated layer. First, prepare a core substrate 70, which is a single-layer copper core substrate 70 formed by a metal layer with a predetermined thickness by etching and resin plugging holes 701 and drilling and plating through holes 702; In the circuit build-up method, a first dielectric layer 71 and a first patterned circuit layer 72 are formed on the surface of the core substrate 70, thereby forming a first circuit build-up structure 7a. This method is also the same as the above-mentioned method, and is to form a second dielectric layer 73 and a second patterned circuit layer 74 on the outermost surface of the first circuit build-up structure 7a by using a circuit build-up method again. This constitutes a second circuit build-up structure 7b, and forms a multi-layer packaging substrate in a step-by-step build-up manner. However, this manufacturing method is not only difficult to manufacture the copper core substrate, but also has the disadvantages of low wiring density and complicated process, as in the above method. Therefore, generally used ones cannot meet the needs of users in actual use.

Invention content:

The technical problem to be solved by the present invention is to provide a copper core layer multilayer packaging substrate that can be supported by a copper core substrate according to actual needs, and can effectively improve the bending of the ultra-thin core layer substrate. A manufacturing method of copper core layer multilayer package substrate that solves warpage problem, simplifies the production process of traditional build-up circuit board, and improves the reliability (Board Level Reliability) when the package is bonded to the substrate.

In order to solve the above technical problems, the technical solution adopted in the present invention is: a method for manufacturing a copper core layer multilayer package substrate, at least comprising the following steps:

(A) providing a copper core substrate;

(B) respectively forming a first resistance layer on the first surface of the copper core substrate, and forming a fully covered second resistance layer on the second surface of the copper core substrate, wherein the first resistance layer forming a plurality of first openings in the layer;

(C) forming several first grooves under the several first openings;

(D) removing the first resistance layer and the second resistance layer;

(E) forming a first electrical barrier layer in the plurality of first grooves;

(F) forming a first dielectric layer and a first metal layer on the first surface of the copper core substrate and the first electrical isolation layer;

(G) forming a plurality of second openings on the first metal layer and the first dielectric layer, and exposing part of the first surface of the copper core substrate;

(H) forming a second metal layer in the plurality of second openings and on the first metal layer;

(1) Forming a third resistance layer on the second metal layer, and forming a completely covered fourth resistance layer on the second surface of the copper core substrate, wherein the third resistance layer is formed on the second metal layer several third openings;

(J) removing the second metal layer and the first metal layer below the third opening, and forming a first circuit layer;

(K) Remove the third resistance layer and the fourth resistance layer, so far, complete a single-layer build-up circuit substrate with copper core substrate support and electrical connection, and choose to directly proceed to step (L) or step ( M);

(L) On the single-layer build-up circuit substrate, a circuit layer on the crystal side and the ball side is fabricated, wherein a first solder resist layer is formed on the surface of the first circuit layer, and a solder resist layer is formed on the first solder resist layer Several fourth openings are formed on the first circuit layer to expose the part of the first wiring layer as an electrical connection pad, and then a fifth resistance layer is formed on the second surface of the copper core substrate, and a fifth resistance layer is formed on the fifth resistance layer. a plurality of fifth openings, and then respectively forming a first barrier layer in the fourth openings and a second barrier layer in the fifth openings, and finally removing the fifth barrier layer; and

(M) Fabricate a circuit build-up structure on the single-layer build-up circuit substrate, wherein a second dielectric layer is formed on the surface of the first circuit layer, and several The sixth opening is to expose part of the first circuit layer, and then a first seed layer is formed on the second dielectric layer and the surface of several sixth openings, and then a sixth seed layer is formed on the first seed layer respectively. resisting layer, and forming a fully covered seventh resisting layer on the second surface of the copper core substrate, and forming several seventh openings on the sixth resisting layer to expose part of the first seed layer, Then a third metal layer is formed on the exposed first seed layer in the seventh opening, and finally the sixth resistance layer, the seventh resistance layer and the first seed layer are removed, so that the second A second circuit layer is formed on the dielectric layer. So far, a double-layer build-up circuit substrate with copper core substrate support and electrical connection is completed, and this step (M) is continued to increase the circuit build-up structure to form more layer packaging substrate, or go directly to the step (L) to fabricate the circuit layer on the chip side and the ball side.

Compared with the prior art, the beneficial effects of the present invention are: the present invention starts to manufacture single-sided, multi-layer packaging substrates based on the copper core substrate, and its structure includes a thick copper plate with high rigid support, and the thick copper plate One side is provided with build-up lines, and the other side is provided with a patterned barrier layer on the ball side, and each build-up line and the way of connecting the chip side and the ball side are connected by several electroplated blind holes and buried holes. At the same time, the present invention has a high-density build-up circuit to provide the winding required for the connection of electronic components, and at the same time, the thick copper plate provides enough rigidity to make the packaging process easier. In this way, a copper core layer multilayer packaging substrate supported by a copper core substrate can be formed according to actual needs, and the problem of warping of the ultra-thin core layer substrate can be effectively improved, and the manufacturing process of traditional build-up circuit boards can be simplified, thereby achieving improved packaging. The reliability (Board Level Reliability) when the body is bonded to the substrate.

Description of drawings:

Fig. 1 is the schematic diagram of the production process of the present invention.

FIG. 2 is a schematic cross-sectional view of a multilayer packaging substrate (1) according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a multilayer packaging substrate (2) according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a multilayer packaging substrate (3) according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a multilayer packaging substrate (4) according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a multilayer packaging substrate (5) according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a multilayer packaging substrate (6) according to an embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of a multilayer packaging substrate (7) according to an embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of a multilayer packaging substrate (8) according to an embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a multi-layer packaging substrate (9) according to an embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of a multi-layer packaging substrate (10) according to an embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a multilayer packaging substrate (11) according to an embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view of a multi-layer packaging substrate (12) according to an embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view of a multi-layer packaging substrate (13) according to an embodiment of the present invention.

FIG. 15 is a schematic cross-sectional view of a multi-layer packaging substrate (14) according to an embodiment of the present invention.

FIG. 16 is a schematic cross-sectional view of a multi-layer packaging substrate (15) according to an embodiment of the present invention.

FIG. 17 is a schematic cross-sectional view of a multi-layer packaging substrate (16) according to an embodiment of the present invention.

FIG. 18 is a schematic cross-sectional view of a multi-layer packaging substrate (17) according to an embodiment of the present invention.

FIG. 19 is a schematic cross-sectional view of a multi-layer packaging substrate (18) according to an embodiment of the present invention.

FIG. 20 is a schematic cross-sectional view of a multilayer packaging substrate (19) according to an embodiment of the present invention.

FIG. 21 is a schematic cross-sectional view of a multi-layer packaging substrate (20) according to an embodiment of the present invention.

FIG. 22 is a schematic cross-sectional view of a substrate packaged with a nucleated layer.

Fig. 23 is a schematic cross-sectional view of the implemented circuit layer-adding (1).

Fig. 24 is the cross-sectional schematic diagram of implementing the layer-adding (two) line.

Fig. 25 is a schematic sectional view of the implemented circuit layer increase (three).

Fig. 26 is a schematic sectional view of the implemented circuit layer increase (four).

FIG. 27 is a schematic cross-sectional view of another encapsulation substrate with a core layer.

Fig. 28 is a schematic cross-sectional view of another used first line build-up structure.

Fig. 29 is another schematic cross-sectional view of the second road build-up structure that has been used.

Label description:

(invention part)

Steps (A)～(M)11～23 Single-layer build-up circuit substrate 3

Copper core substrate 30 First and second resistance layers 31, 32

First opening 33 First electrical barrier layer 34

First dielectric layer 35 First metal layer 36

Second opening 37 Second metal layer 38

The third and fourth resistance layers 39, 40 layer build-up circuit substrate 4

The third opening 41 The first circuit layer 42

Second dielectric layer 43 Fourth opening 44

The first seed layer 45 The fifth and sixth resistance layers 46, 47

Fifth opening 48 Third metal layer 49

The second circuit layer 50 The first solder resist layer 51

Sixth opening 52 Seventh resistance layer 53

Seventh opening 54 First and second barrier layers 55, 56

(usual part)

The first and second line build-up structures 6a, 6b core substrate 60

Core layer 601 Line layer 602

Plated via hole 603 First dielectric layer 61

First opening 62 The seed layer 63

Patterned resistance layer 64 Second opening 65

The first patterned circuit layer 66 Conductive blind holes 67

Second Dielectric Layer 68 Second Patterned Circuit Layer 69

Two-line build-up structure 7a, 7b Core substrate 70

Resin plug hole 701 Plated through hole 702

First Dielectric Layer 71 First Patterned Circuit Layer 72

Second Dielectric Layer 73 Second Patterned Circuit Layer 74

Detailed ways:

Please refer to FIG. 1 , which is a schematic diagram of the production process of the present invention. As shown in the figure: the present invention is a method for manufacturing a copper core layer multilayer packaging substrate, which at least includes the following steps:

(A) Provide copper core substrate 11: provide a copper core substrate;

(B) Forming the first and second resistance layers and the first opening 12: respectively forming a first resistance layer on the first face of the copper core substrate, and forming a completely covered shape on the second face of the copper core substrate the second resistance layer, and forming a plurality of first openings on the first resistance layer by exposure and development;

(C) Forming the first groove 13: forming several first grooves under the several first openings by etching;

(D) removing the first and second resistance layers 14: removing the first resistance layer and the second resistance layer by stripping;

(E) Forming the first electrical isolation layer 15: forming a first electrical isolation layer in several first grooves by direct lamination or printing;

(F) forming a first dielectric layer and a first metal layer 16: directly pressing a first dielectric layer and a first metal layer on the first surface of the copper core substrate and the first electrical isolation layer, Alternatively, the first metal layer can be formed after laminating the first dielectric layer, wherein the first dielectric layer can be formed by lamination or printing simultaneously with the first electrical insulating layer;

(G) Forming second openings 17: forming several second openings on the first metal layer and the first dielectric layer by laser drilling, and exposing part of the first surface of the copper core substrate, wherein several The second opening can be formed by opening the copper window (Conformal Mask) first, and then formed by laser drilling, or by direct laser drilling (LASER Direct);

(H) Forming the second metal layer 18: forming a second metal layer in several second openings and on the first metal layer by electroless plating or electroplating;

(1) Form the third and fourth resistance layers and the third opening 19: respectively form a third resistance layer on the second metal layer, and form a completely covered fourth resistance layer on the second surface of the copper core substrate. resisting layer, and forming several third openings on the third resisting layer by exposing and developing;

(J) Forming the first wiring layer 20: removing the second metal layer and the first metal layer below the third opening by etching, and forming a first wiring layer;

(K) Completing the single-layer build-up circuit substrate 21 supported by the copper core substrate and electrically connected: removing the third resistance layer and the fourth resistance layer by lift-off. So far, a single-layer build-up circuit substrate with copper core substrate support and electrical connection is completed, and step (L) or step (M) can be directly performed;

(L) Making the circuit layer on the crystal side and the ball side 22: Carry out a circuit layer on the crystal side and the ball side on the single-layer build-up circuit substrate, in which, coat a layer on the surface of the first circuit layer The layer has a first solder resist layer for insulation protection, and several fourth openings are formed on the first solder resist layer by exposure and development to expose the part of the first circuit layer as an electrical connection pad, and then A fifth barrier layer is formed on the second surface of the copper core substrate, and several fifth openings are formed on the fifth barrier layer, and then a first barrier layer is formed in the fourth openings respectively, and A second barrier layer is formed in the fifth opening, and finally the fifth barrier layer is removed by stripping. So far, a completely patterned wiring layer on the crystal side and a patterned but still completely electrically shorted ball side wiring layer have been completed, wherein the first and second barrier layers can be electroplated nickel-gold, electroless nickel-plated gold, either electroplated silver or electroplated tin; and

(M) Fabricate a circuit build-up structure 23: perform a circuit build-up structure on the single-layer build-up circuit substrate, wherein a second circuit layer is formed on the surface of the first circuit layer and the first dielectric layer dielectric layer, and form several sixth openings on the second dielectric layer by laser drilling to expose part of the first circuit layer, and then electroless plating or electroplating on the second dielectric layer A first seed layer is formed on the surface of several sixth openings, a sixth resistance layer is formed on the first seed layer, and a fully covered first layer is formed on the second surface of the copper core substrate. Seven resistance layers, and use exposure and development methods to form several seventh openings on the sixth resistance layer to expose part of the first seed layer, and then electroless plating or electroplating in the seventh openings A third metal layer is formed on the exposed first seed layer, and finally the sixth resistance layer and the seventh resistance layer are removed by lift-off, and the first seed layer is removed by etching, so that A second circuit layer is formed on the second dielectric layer. So far, another layer of circuit build-up structure is added to complete a double-layer build-up circuit substrate supported by the copper core substrate and electrically connected. And this step (M) can be continued to increase the circuit layer build-up structure to form a packaging substrate with more layers, or directly go to this step (L) to make the circuit layer on the crystal side and the ball side, wherein several sixth openings The copper window can be made first, and then formed by laser drilling, or formed by direct laser drilling.

Among them, the above-mentioned first to seventh barrier layers are high-sensitivity photoresists of dry film or wet film by lamination, printing or spin coating; the first electrical barrier layer and the first and second The dielectric layer can be solder resist green paint, epoxy resin insulating film (AjinomotoBuild-up Film, ABF), benzocyclobutene (Benzocyclo-buthene, BCB), bismaleimide triazine resin (Bismaleimide Triazine , BT), epoxy resin board (FR4, FR5), polyimide (Polyimide, PI), polytetrafluoroethylene (Poly (tetra-floroethylene), PTFE) or one composed of epoxy resin and glass fiber .

Please refer to FIG. 2 to FIG. 21, which are respectively a schematic cross-sectional view of a multilayer packaging substrate (1) according to an embodiment of the present invention, a schematic cross-sectional view of a multilayer packaging substrate (2) according to an embodiment of the present invention, and a schematic cross-sectional view of a multilayer packaging substrate (2) according to an embodiment of the present invention. The cross-sectional schematic diagram of the multi-layer packaging substrate (three), the cross-sectional schematic diagram of the multi-layer packaging substrate (four) according to an embodiment of the present invention, the cross-sectional schematic diagram of the multi-layer packaging substrate (five) according to an embodiment of the present invention, the multi-layer packaging substrate according to an embodiment of the present invention Schematic cross-sectional view of the multi-layer packaging substrate (6), schematic cross-sectional view of the multi-layer packaging substrate (7) according to an embodiment of the present invention, schematic cross-sectional view of the multi-layer packaging substrate (8) according to an embodiment of the present invention, multi-layer packaging according to an embodiment of the present invention Schematic cross-sectional view of substrate (9), schematic cross-sectional view of multilayer packaging substrate (10) according to an embodiment of the present invention, schematic cross-sectional view of multilayer packaging substrate (11) according to an embodiment of the present invention, and multilayer packaging substrate according to an embodiment of the present invention (12) Schematic cross-sectional view, schematic cross-sectional view of a multilayer packaging substrate (13) according to an embodiment of the present invention, schematic cross-sectional view of a multilayer packaging substrate (14) according to an embodiment of the present invention, and multilayer packaging according to an embodiment of the present invention Schematic cross-sectional view of substrate (fifteen), schematic cross-sectional view of multilayer packaging substrate (16) according to an embodiment of the present invention, schematic cross-sectional view of multilayer packaging substrate (17) according to an embodiment of the present invention, multi-layer packaging substrate (17) according to an embodiment of the present invention A schematic cross-sectional view of a packaging substrate (18), a schematic cross-sectional view of a multilayer packaging substrate (19) according to an embodiment of the present invention, and a schematic cross-sectional view of a multilayer packaging substrate (20) according to an embodiment of the present invention. As shown in the figure: in a preferred embodiment of the present invention, a copper core substrate 30 is firstly provided, and a high-sensitivity photoactive polymer material is respectively pasted on the first and second faces of the copper core substrate 30. First and second resistance layers 31, 32, and form several first openings 33 on the first resistance layer 31 by means of exposure and development, to expose the first surface of the copper core substrate 30 under it, and the second The second resistance layer 32 on the surface is completely covered. Afterwards, a half-etched groove 311 is formed by etching, wherein the copper core substrate 30 is a thick copper plate without dielectric layer material; the first and second resistance layers 31 and 32 are dry film photoresist layers.

Next, the first and second resistive layers are removed to form a copper core substrate 30 with a first surface of pins. Then print a first electrical barrier layer 34 in the groove 311, and press a first dielectric layer 35 and a first metal layer 36 on the first surface of the copper core substrate 30, and then use laser drilling Form several second openings 37 on the first metal layer 36 and the first dielectric layer 35 by means of holes, and then form several second openings 37 and the first metal layer 36 by electroless plating or electroplating. A second metal layer 38 is formed on the surface, wherein the first and second metal layers 36 , 38 are both copper, and the second metal layer 38 is used for electrical connection with the first surface of the copper core substrate 30 .

Next, a third resistive layer 39 of a highly photosensitive polymer material is pasted on the second metal layer 38, and a high photosensitive polymer material is pasted on the second surface of the copper core substrate 30. The fourth resistance layer 40. A plurality of third openings 41 are formed on the third resistance layer 39 by means of exposure and development to expose the second metal layer 38 thereunder. Then the first and second metal layers under the third opening 41 are removed by etching to form a first circuit layer 42 , and finally the third and fourth resistance layers are removed. So far, a single-layer build-up circuit substrate 3 with patterned circuits and connected to the first surface of the pins of the copper core substrate 30 is completed.

Next, in a preferred embodiment of the present invention, the fabrication of the circuit build-up structure is carried out first. First, a second dielectric layer 43 made of epoxy resin insulating film material is pasted and pressed together on the first circuit layer 42 and the first dielectric layer 35, and then the second dielectric layer is formed by laser drilling. Several fourth openings 44 are formed on the dielectric layer 43 to expose the first wiring layer 42 below, and a first crystal layer is formed on the surface of the second dielectric layer 43 and the fourth opening 44 by electroless plating or electroplating. Seed layer 45. Afterwards, a fifth resistive layer 46 of a highly photosensitive polymer material is pasted on the first seed layer 45, and a high photosensitive polymer material is pasted on the second surface of the copper core substrate 30. The sixth resistance layer 47, and then use exposure and development to form several fifth openings 48 on the fifth resistance layer 46, and then electrolessly or electroplate a third metal layer 49 in the fifth openings 48 , and finally remove the fifth and sixth resistance layers, and then remove the first seed layer by etching to form a second circuit layer 50 . So far, another layer of circuit build-up structure is added to complete a double-layer build-up circuit substrate 4 with copper core substrate support and electrical connection, in which the first seed layer and the third metal layer are both For metallic copper.

Afterwards, the fabrication of the circuit layers on the die side and the ball side is carried out. First, a layer of first solder resist layer 51 for insulation and protection is coated on the surface of the second circuit layer 50, and then several sixth openings 52 are formed on the first solder resist layer 51 by exposure and development to reveal The circuit build-up structure acts as an electrical connection pad. Next, attach a seventh resistance layer 53 of a highly photosensitive polymer material on the second surface of the copper core substrate 30, and form several seventh openings on the seventh resistance layer 53 by means of exposure and development. 54 , and then respectively form a first barrier layer 55 on the several sixth openings 52 , and form a second barrier layer 56 on the several seventh openings 54 , and finally, remove the seventh barrier layer. So far, a multi-layer packaging substrate 5 supported by copper core layers is completed, wherein the first and second barrier layers 55 and 56 are both Ni-Au layers.

It can be seen from the above that the present invention is based on the copper core substrate, and starts to produce a single-sided, multi-layer packaging substrate. Then it has a ball-side patterned barrier layer. Among them, each build-up circuit and the way of connecting the die side and the ball side are connected by several electroplated blind holes and buried holes. Therefore, the feature of the packaging substrate of the present invention is that it has high-density build-up circuits to provide the winding required for connecting electronic components, and at the same time, the thick copper plate provides sufficient rigidity to simplify the packaging process. Although each circuit is completely shorted electrically before the packaging process is completed, after the packaging process is completed, the ball-side pattern barrier layer can be used to remove part of the thick copper plate by etching, thereby making the electrical isolation and forming a unique Protective pillar pins. Thereby, the multilayer packaging substrate manufactured by using the high-density build-up circuit packaging substrate method of the present invention can form a copper core layer multilayer packaging substrate supported by a copper core substrate according to actual needs, and can effectively improve the ultra-thin The warping problem of the core layer substrate and the simplification of the traditional build-up circuit board manufacturing process, thereby achieving the purpose of improving the reliability (Board Level Reliability) when the package is bonded to the substrate.

In summary, the present invention is a method for manufacturing a copper core layer multilayer packaging substrate, which can effectively improve the various shortcomings of the existing ones, and has high-density build-up circuits to provide the required windings for connecting electronic components. At the same time, And the thick copper plate provides sufficient rigidity to make the packaging process easier. Thereby, using the multilayer packaging substrate manufactured by the present invention, a copper core layer multilayer packaging substrate supported by a copper core substrate can be formed according to actual needs, and the problem of warping of the ultra-thin core layer substrate can be effectively improved and simplified. Traditional build-up circuit board production process, in order to achieve the purpose of improving the reliability (Board Level Reliability) when the package is bonded to the substrate, and then make the production of the present invention more advanced, more practical, and more in line with the needs of users, it has indeed met To apply for an invention patent, one must file a patent application in accordance with the law.

But the above is only a preferred embodiment of the present invention, and should not limit the scope of the present invention; therefore, all simple equivalent changes and modifications made according to the claims of the present invention and the contents of the description should be Still belong to the scope that the patent of the present invention covers.

Claims (13)

1. A method for making a copper core layer multilayer packaging substrate, characterized in that it comprises at least the following steps: (A) providing a copper core substrate; (B) respectively forming a first resistance layer on the first surface of the copper core substrate, and forming a fully covered second resistance layer on the second surface of the copper core substrate, wherein the first resistance layer forming a plurality of first openings in the layer; (C) forming several first grooves under the several first openings; (D) removing the first resistance layer and the second resistance layer; (E) forming a first electrical barrier layer in the plurality of first grooves; (F) forming a first dielectric layer and a first metal layer on the first surface of the copper core substrate and the first electrical isolation layer; (G) forming several second openings on the first metal layer and the first dielectric layer, and exposing part of the first surface of the copper core substrate; (H) forming several second openings and the first metal layer forming a second metal layer on the layer; (1) Forming a third resistance layer on the second metal layer, and forming a completely covered fourth resistance layer on the second surface of the copper core substrate, wherein the third resistance layer is formed on the second metal layer several third openings; (J) removing the second metal layer and the first metal layer below the third opening, and forming a first circuit layer; (K) Remove the third resistance layer and the fourth resistance layer, so far, complete a single-layer build-up circuit substrate with copper core substrate support and electrical connection, and choose to directly proceed to step (L) or step ( M); (L) On the single-layer build-up circuit substrate, a circuit layer on the crystal side and the ball side is fabricated, wherein a first solder resist layer is formed on the surface of the first circuit layer, and a solder resist layer is formed on the first solder resist layer Several fourth openings are formed on the first circuit layer to expose the part of the first wiring layer as an electrical connection pad, and then a fifth resistance layer is formed on the second surface of the copper core substrate, and a fifth resistance layer is formed on the fifth resistance layer. a plurality of fifth openings, and then respectively forming a first barrier layer in the fourth openings and a second barrier layer in the fifth openings, and finally removing the fifth barrier layer; and (M) Fabricate a circuit build-up structure on the single-layer build-up circuit substrate, wherein a second dielectric layer is formed on the surface of the first circuit layer, and several The sixth opening is to expose part of the first circuit layer, and then a first seed layer is formed on the second dielectric layer and the surface of several sixth openings, and then a sixth seed layer is formed on the first seed layer respectively. resisting layer, and forming a fully covered seventh resisting layer on the second surface of the copper core substrate, and forming several seventh openings on the sixth resisting layer to expose part of the first seed layer, Then a third metal layer is formed on the exposed first seed layer in the seventh opening, and finally the sixth resistance layer, the seventh resistance layer and the first seed layer are removed, so that the second A second circuit layer is formed on the dielectric layer. So far, a double-layer build-up circuit substrate with copper core substrate support and electrical connection is completed, and this step (M) is continued to increase the circuit build-up structure to form more layer packaging substrate, or go directly to the step (L) to fabricate the circuit layer on the chip side and the ball side. 2 . The method for manufacturing a copper-core layer multilayer package substrate according to claim 1 , wherein the copper-core substrate is a copper plate without dielectric material. 3 . 3. The manufacturing method of copper core layer multilayer packaging substrate according to claim 1, characterized in that, the first to seventh resistance layers are made of dry film or wet film by lamination, printing or spin coating High-sensitivity photoresist. 4 . The method for manufacturing a copper core layer multilayer packaging substrate according to claim 1 , wherein the first, third, fifth and seventh openings are formed by exposure and development. 5. The manufacturing method of copper core layer multilayer packaging substrate according to claim 1, characterized in that, the step (C) forms several first grooves, and the step (J) removes the first and second metal layer and the step (M) The method of removing the first seed layer is etching. 6 . The method for manufacturing the copper core layer multilayer packaging substrate according to claim 1 , wherein the removal method of the first to seventh resistance layers is peeling. 7 . 7 . The method for manufacturing a copper core layer multilayer packaging substrate according to claim 1 , wherein the first electrical barrier layer is formed by direct lamination or printing. 8 . 8. The manufacturing method of copper core layer multilayer packaging substrate according to claim 1, characterized in that, the first electrical barrier layer and the first and second dielectric layers are solder resist green paint, epoxy resin insulation One of film, benzocyclobutene, bismaleimide-triazepine resin, epoxy resin sheet, polyimide, polytetrafluoroethylene, epoxy resin or fiberglass. 9. The manufacturing method of copper core layer multilayer packaging substrate according to claim 1, characterized in that, the first electrical barrier layer of the step (E) and the first dielectric layer of the step (F) are pressed together or Printed form. 10. The manufacturing method of copper core layer multilayer package substrate according to claim 1, characterized in that, the step (F) is to directly press the first dielectric layer and the first metal layer on it, or After laminating the first dielectric layer, the first metal layer is formed. 11. The manufacturing method of copper core layer multilayer packaging substrate according to claim 1, characterized in that, the second and sixth openings are formed by first opening copper windows, and then by laser drilling, or Formed by direct laser drilling. 12 . The method for manufacturing a copper core layer multilayer package substrate according to claim 1 , wherein the second and third metal layers and the first seed layer are formed by electroless plating or electroplating. 13 . 13. The manufacturing method of copper core layer multilayer packaging substrate according to claim 1, characterized in that the first and second barrier layers are one of electroplated nickel-gold, electroless nickel-plated gold, electroplated silver or electroplated tin .

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