CN101681877B - quasi-vertical structure light-emitting diode - Google Patents

Abstract

The invention discloses a light-emitting device with a quasi-vertical structure. According to one embodiment of the present invention, a quasi-vertical structure light emitting diode includes a sapphire substrate; a plurality of semiconductor layers grown on the sapphire substrate, the plurality of semiconductor layers including an n-GaN layer, an active layer and a p-GaN layer; a plurality of holes etched in the plurality of semiconductor layers, each hole etched into the sapphire substrate, and a plurality of sapphire holes in the sapphire substrate, each hole aligned with one of the sapphire holes to form a hole wall, the hole wall and bottom being deposited with one of the n-semiconductor metals, and each hole being filled with the other metal to form an n-electrode contact; an n-mesa at the active layer and the p-GaN layer, the n-mesa being deposited with an n-semiconductor metal, and a passivation layer grown over the n-semiconductor metal; and a p-semiconductor metal layer deposited on the p-GaN layer, and a p-electrode metal bonded to the p-semiconductor metal.

Description

quasi-vertical light-emitting diode

technical field

The invention relates to a semiconductor device, in particular to a light emitting diode and a manufacturing method thereof.

Background of the invention

Light-emitting diodes (LEDs) are currently one of the newest and fastest-growing technologies in the semiconductor field. Although LEDs have been used for indication and signaling purposes over the past decade, technological developments and improvements have allowed LEDs to be widely used in lighting applications.

Semiconductors containing the group V element nitrogen (N) have proven useful in short-wavelength light-emitting devices. In the meantime, GaN-based semiconductors such as _InxGa1 - _xN and _AlxGayInzN have been widely studied _as light-emitting diodes, so that _such light-emitting diodes (LEDs) have been put into practical use.

Typically, vertical GaN-based LEDs are grown on a sapphire substrate. Sapphire substrates are rigid, non-conductive, and have low thermal conductivity. In a conventional process for making GaN-based LEDs, multiple GaN layers are grown on a sapphire substrate. One or more p-electrodes can then be formed on the p-type GaN layer, using a laser lift-off (LLO) process to remove the sapphire substrate, exposing the n-type layer for subsequent further processing.

LLO is a technique used to remove sapphire. However, LLO can cause damage from laser-induced shock waves and impact yield, causing problems with device performance and reliability. Sapphire can also be removed by mechanical methods, including grinding, polishing, and chemical mechanopolishing (CMP), but the difficulty of achieving uniform adhesion to the disc and uniform polishing in the range of a few microns makes it difficult to simply use this mechanical method to achieve reliable device performance and higher output.

Flip-chip LEDs are a common alternative to vertically structured LEDs and have a more mature process, but the structure has lower heat dissipation due to the airgap between the components and the heat sink . Flip-chip mounting and packaging are also more expensive compared to vertically structured LEDs.

Therefore, there is a need for a light-emitting diode with a quasi-vertical structure, which can overcome many defects of known light-emitting devices, and can achieve desired performance requirements, while reducing technical challenges and obtaining higher yields.

Summary of the invention

According to an embodiment of the present invention, a method for manufacturing a quasi-vertical structure light emitting device is disclosed. The method includes providing a growth substrate; growing a plurality of semiconductor layers on the growth substrate; etching the plurality of semiconductor layers to produce device isolation trenches, which form a plurality of separable semiconductor devices and a plurality of holes; drilling a plurality of blind holes into the sapphire substrate, the plurality of blind holes being drilled to a predetermined depth, wherein the holes define a blind hole wall and a blind hole end on each blind hole; Deposit n-semiconductor metal in each blind hole; form an n-electrode contact in each blind hole by electroplating an n-electrode metal In each blind hole, the n-electrode metal is connected to the n-semiconductor metal; thinning the sapphire substrate to expose the n-electrode metal as an n-electrode; and depositing bonding metal to the n-electrode for packaging.

According to an embodiment of the present invention, a method for manufacturing a quasi-vertical structure light emitting device is disclosed. The method includes providing a sapphire substrate; growing a plurality of semiconductor layers on the sapphire substrate, the plurality of semiconductor layers including an n-GaN layer, an active layer and a p-GaN layer; etching the plurality of semiconductor layers to produce device isolation grooves, The isolation trenches form a plurality of separable semiconductor devices; etch the plurality of semiconductor layers to provide at least one hole in the plurality of semiconductor layers, at least one hole is etched into the sapphire substrate; etch an n-mesa between the active layer and p-GaN layer; at least one blind hole is drilled into the sapphire substrate at the position of at least one hole in a plurality of semiconductor layers, at least one sapphire hole is drilled to a predetermined depth, wherein the hole defines a blind hole wall of at least one blind hole; depositing a p-semiconductor metal on p-GaN layer; deposit an n-semiconductor metal on n-GaN; deposit an n-semiconductor metal along the wall of the blind hole; electroplate an n-electrode metal in at least one blind hole; fill Each blind hole to form an n-electrode contact; grow a passivation layer (passivation layer) on top of all n-metal; apply a p-electrode metal to the p-semiconductor metal; thin the sapphire substrate to expose the n-electrode contact points; and cutting along the device isolation trenches to form a plurality of semiconductor devices.

According to another embodiment of the present invention, a quasi-vertical structure light emitting device is disclosed. The quasi-vertical structure light-emitting device includes a sapphire substrate; a plurality of semiconductor layers grown on the sapphire substrate, the plurality of semiconductor layers including an n-GaN layer, an active layer and a p-GaN layer; etched on the plurality of semiconductor layers A plurality of holes, each hole is etched into the sapphire substrate, and a plurality of sapphire holes on the sapphire substrate, each hole is aligned with a sapphire hole to form the hole walls, and an n-semiconductor metal is deposited on the hole walls and bottom , and the n-semiconductor metal is connected to n-GaN to form an n-electrode contact; an n-GaN is plated with an n-electrode metal, the n-electrode metal is connected to the n-semiconductor metal, and a passivation layer is grown on over the n-semiconductor metal; a p-semiconductor metal layer is deposited on the p-GaN layer; and a p-electrode is bonded to the p-semiconductor metal.

Other embodiments of the present invention will be readily understood by those skilled in the art from the following detailed description, in which embodiments of the present invention are illustrated by the accompanying drawings. As will be realized, its several details can be changed in various respects to form other and different embodiments of the invention without departing from the spirit and scope of the invention.

Description of drawings

FIG. 1 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

FIG. 2 is a cross-sectional side view of the semiconductor structure shown in FIG. 1 at line A according to one embodiment of the present invention.

3 is a cross-sectional side view of the semiconductor structure shown in FIG. 1 at line B according to one embodiment of the present invention.

FIG. 4 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

FIG. 5 is a cross-sectional side view of the semiconductor structure shown in FIG. 4 at line A according to one embodiment of the present invention.

6 is a cross-sectional side view of the semiconductor structure shown in FIG. 4 at line B according to one embodiment of the present invention.

FIG. 7 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

FIG. 8 is a cross-sectional side view of the semiconductor structure shown in FIG. 7 at line A according to one embodiment of the present invention.

9 is a cross-sectional side view of the semiconductor structure shown in FIG. 7 at line B according to one embodiment of the present invention.

FIG. 10 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

11 is a cross-sectional side view of the semiconductor structure shown in FIG. 10 at line A according to one embodiment of the present invention.

12 is a cross-sectional side view of the semiconductor structure shown in FIG. 10 at line B according to one embodiment of the present invention.

FIG. 13 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

14 is a cross-sectional side view of the semiconductor structure shown in FIG. 13 at line A according to one embodiment of the present invention.

15 is a cross-sectional side view of the semiconductor structure shown in FIG. 13 at line B according to one embodiment of the present invention.

FIG. 16 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

17 is a cross-sectional side view of the semiconductor structure shown in FIG. 16 along line A according to one embodiment of the present invention.

18 is a cross-sectional side view of the semiconductor structure shown in FIG. 16 at line B according to one embodiment of the present invention.

FIG. 19 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

20 is a cross-sectional side view of the semiconductor structure shown in FIG. 19 at line A according to one embodiment of the present invention.

21 is a cross-sectional side view of the semiconductor structure shown in FIG. 19 at line B according to one embodiment of the present invention.

Figure 22 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

23 is a cross-sectional side view of the semiconductor structure shown in FIG. 22 at line A according to one embodiment of the present invention.

24 is a cross-sectional side view of the semiconductor structure shown in FIG. 22 at line B according to one embodiment of the present invention.

Figure 25 is a partial top view of a semiconductor structure according to one embodiment of the present invention.

26 is a cross-sectional side view of the semiconductor structure shown in FIG. 25 at line A according to one embodiment of the present invention.

Detailed description of the invention

In the following description, specific embodiments of the present invention are shown by description with reference to the accompanying drawings. It will be understood that other embodiments may be made as structural and other changes can be made without departing from the scope of the present invention. Moreover, the various embodiments and aspects of each different embodiment may be combined in any suitable manner. Accordingly, the drawings and detailed description are to be regarded as descriptive and not restrictive. In the drawings, the same reference numbers refer to the same or similar elements.

In the specification, the prefix "u-" is used to refer to undoped or slightly doped, "p-" to refer to p-type or positive electrode, and "n-" to refer to n-type or negative electrode.

In general, embodiments of the present invention relate to a quasi-vertical light emitting diode (quasi-VLED). According to one embodiment of the quasi-VLED, blind vias are drilled in the growth substrate to form n-electrode contacts. Therefore, there is no need to completely remove the growth substrate to expose the n-electrode contacts. 1 to 26 depict an example process for fabricating a semiconductor structure for use in a quasi-vertical light emitting diode.

According to an embodiment of the present invention, the method includes: providing a growth substrate; growing a plurality of semiconductor layers on the growth substrate; etching the plurality of semiconductor layers to form device isolation grooves and a plurality of separable semiconductor devices. Holes; Drilled by laser or dry etching, a plurality of blind vias are drilled in the sapphire substrate from the side of the semiconductor layer to a predetermined depth, wherein the drilled holes define the blind vias of each blind via wall; and forming an ohmic contact to the n-semiconductor by depositing metal such as electron beam (E-beam) or sputtering. The n-semiconductor metal forms an ohmic contact with the n-type semiconductor, and also covers the regions of the plurality of blind holes. Plating of the plurality of blind vias may use any suitable metal, such as copper or nickel. Metal plating is provided to electrically connect to the n-semiconductor metal. Next, the side of the sapphire substrate without the semiconductor layer is thinned to expose the metal to be plated. Other metals can be deposited onto the plated metal for LED packaging.

Referring now to the drawings, FIG. 1 is a partial top view of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure is any suitable semiconductor wafer or substrate. 2 is a cross-sectional side view of the semiconductor structure shown in FIG. 1 on line A, and FIG. 3 is a cross-sectional side view of the semiconductor structure shown in FIG. 1 on line B, according to an embodiment of the present invention. 1 to 3, the semiconductor structure shown includes a sapphire substrate 110, an undoped or slightly doped n-GaN layer 112 is grown on the sapphire substrate 110, and an active layer 114 with multiple quantum wells is grown on the On the n-GaN layer 112 , a p-GaN layer 116 is grown on the active layer 114 . The semiconductor is singulated into individual wafers 118 using mesa isolation. Although four individual wafers 118 are shown here, FIG. 1 is only a partial schematic diagram of a semiconductor structure, and embodiments of the invention may form any suitable number of wafers. Etching may also be used to define the plurality of holes 120 in the n-GaN layer 112 , the active layer 114 and the p-GaN layer 116 . Two holes 120 are formed in each wafer 118 as an n-electrode bonding area. The holes shown are square, but may be of any suitable shape and location as required by the specific component requirements.

Referring now to Figures 4 to 6, Figure 4 is a partial top view of a semiconductor structure according to an embodiment of the present invention, Figure 5 is a cross-sectional side view of the semiconductor structure shown in Figure 4 on line A, and Figure 6 is a cross-sectional side view of the semiconductor structure shown in Figure 4 on line B cross-sectional side view. An n-GaN 400 is etched into the active layer 114 and p-GaN layer 118 . The n-GaN 400 can be etched by ICP (Inductively Coupled Plasma) etching or any other suitable etching method.

For clarity of description, FIGS. 7 to 26 depict a single wafer among the four wafers shown in the semiconductor structure shown in FIGS. 1 to 6. Referring to FIG. However, any number of elements may be fabricated during the process.

Referring now to Figures 7 to 9, Figure 7 is a partial top view of a semiconductor structure according to an embodiment of the present invention, Figure 8 is a cross-sectional side view of the semiconductor structure shown in Figure 7 on line A, and Figure 9 is a cross-sectional side view of the semiconductor structure shown in Figure 7 on line B cross-sectional side view. A plurality of sapphire holes 700 are formed in the sapphire layer 110 . In one embodiment, the sapphire drilling is performed by laser, dry etching, wet etching, or any other suitable method, drilling to a predetermined depth at each location of the etched hole 120 . According to one embodiment, the suitable depth is greater than 3um. According to another embodiment, the suitable depth is greater than 10 um, and according to another embodiment, the suitable depth is 30 um. However, these are only example depths and other depths may be used, depending mainly on the specific requirements of the installation.

Referring now to Figures 10 to 12, Figure 10 is a partial top view of a semiconductor structure according to an embodiment of the present invention, Figure 11 is a cross-sectional side view of the semiconductor structure shown in Figure 10 on line A, and Figure 12 is a cross-sectional side view of the semiconductor structure shown in Figure 10 on line B cross-sectional side view. A p-semiconductor metal 1000 is deposited on the p-GaN layer. An example p-semiconductor metal is nickel/gold. However, other suitable metals may also be used.

Referring now to Figures 13 to 15, Figure 13 is a partial top view of a semiconductor structure according to an embodiment of the present invention, Figure 14 is a cross-sectional side view of the semiconductor structure shown in Figure 13 on line A, and Figure 15 is a cross-sectional side view of the semiconductor structure shown in Figure 13 on line B cross-sectional side view. An n-semiconductor metal 1300 is deposited at the n-GaN 400 shown in FIGS. 4-6. The n-semiconductor metal 1300 is also deposited on the walls and ends of the plurality of sapphire holes 700 . An example n-semiconductor metal is titanium/aluminum/titanium/gold.

Referring now to Figures 16 to 18, Figure 16 is a partial top view of a semiconductor structure according to an embodiment of the present invention, Figure 17 is a cross-sectional side view of the semiconductor structure shown in Figure 16 on line A, and Figure 18 is a cross-sectional side view of the semiconductor structure shown in Figure 16 on line B cross-sectional side view. Via/hole plating is performed to form an electrode contact 1600 . Via/hole plating is done by electroless plating or electroplating or any other suitable method to fill the holes with metal. For example, a suitable metal is nickel or copper.

Referring now to Figures 19 to 21, Figure 19 is a partial plan view of a semiconductor structure according to an embodiment of the present invention, Figure 20 is a cross-sectional side view of the semiconductor structure shown in Figure 19 on line A, and Figure 21 is a cross-sectional side view of the semiconductor structure shown in Figure 19 on line B cross-sectional side view. A passivation layer 1900 is grown to cover all of the n-semiconductor metal, so that now only the p-semiconductor metal is exposed. According to one embodiment, the passivation layer is a silicon oxide (SiO ₂ ) passivation layer.

Referring now to Figures 22 to 24, Figure 22 is a partial top view of a semiconductor structure according to an embodiment of the present invention, Figure 23 is a cross-sectional side view of the semiconductor structure shown in Figure 22 on line A, and Figure 24 is a cross-sectional side view of the semiconductor structure shown in Figure 22 on line B cross-sectional side view. As a master substrate, a p-electrode metal 2200 is applied to the p-semiconductor metal 1000 and then the sapphire substrate 110 is thinned. According to one embodiment, copper is bonded to the p-semiconductor metal 1000 . According to another embodiment, silicon is bonded to the p-semiconductor metal 1000 . However, other conductive materials may be applied using any suitable method.

Referring now to FIGS. 25-26, FIG. 25 is a partial plan view of the sapphire side of the semiconductor structure of one embodiment of the present invention, and FIG. 26 is a cross-sectional side view of the semiconductor structure shown in FIG. 25 at line A. The sapphire substrate 110 is then thinned to expose the electrode contacts 1600 using grinding, polishing, chemical mechanical polishing (CMP), or other suitable thinning methods. Next, the electrode contact 1600 is exposed to make contact with an n-electrode. As shown in Figures 22 to 24, there is a p-electrode 2200 on the other side of the semiconductor structure.

Next, the semiconductor structure can be diced into individual light emitting diodes. The quasi-vertical light-emitting diodes manufactured according to the embodiments of the present invention can be packaged with vertical-structure LEDs, avoiding the need for any new and complicated packaging process. According to one embodiment, a mirror can be added to reflect light to the sapphire side of the device. Light extraction can also be improved by surface roughening.

Embodiments of the present invention have many advantages over the prior art. For example, according to one embodiment, due to the large contact area between the p-electrode 2200 (which is a good thermal and electrical conductor) and the active layer 114, the heat dissipation and current spreading of p-GaN will be very good, especially Compared to flip-chip LEDs (which have an air gap and have less heat dissipation). Also, along the hole walls of the sapphire holes 700, the ohmic contact metal of the n-GaN layer can be connected to a conductive metal, such as copper or nickel. Furthermore, the ohmic contact metal (n-semiconductor metal 1300) of the n-GaN layer 112 is connected to the n-GaN layer 112 on the same side of the n-GaN layer 112 as the electrode metal of the p-GaN layer 116 (p -semiconductor metal 1000) same. Therefore, it is not necessary to completely remove the sapphire substrate 110 . The uniformity tolerance of mechanical thinning is determined by the depth drilled or etched into the sapphire, so the tolerance will be greater than that required to completely remove the sapphire. According to one embodiment, by stopping the mechanical thinning before reaching the active layer or before approaching the active layer, device performance will not be degraded due to mechanical damage, thereby enabling improved yield.

Although the present invention has been particularly shown and described with reference to the illustrated embodiments, workers skilled in the art will understand that changes may be made in form and detail without departing from the spirit and scope of the invention. For example, while embodiments of the invention have been described with reference to GaN devices, embodiments of the invention may also be used with nitride-based semiconductors, lasers, and any other suitable optoelectronic devices. Additionally, while certain example materials and processes have been described, other suitable materials and processes can also be used.

Therefore, the above description is intended to provide example embodiments of the invention, and the scope of the invention should not be limited by the specific examples provided.

Claims (28)

1. method of making accurate vertical structure light-emitting device, the method comprises:

A growth substrate is provided;

The a plurality of semiconductor layers of growth on growth substrate;

The a plurality of semiconductor layers of etching and generation device isolation channel, it forms a plurality of separable semiconductor elements and a plurality of hole;

Bore a plurality of blind holes on the position in each hole in a plurality of semiconductor layers in sapphire substrate, wherein a blind hole end on blind pore wall and each blind hole has been determined in boring;

Deposition n-semiconductor alloy is in each blind hole;

By electroplating a kind of n-electrode metal in each blind hole, form a n-electrode contacts in each blind hole, the n-electrode metal is connected to the n-semiconductor alloy;

The thinning sapphire substrate is to expose the n-electrode metal as a n-electrode; With

Deposition bonding metal to the n-electrode so that encapsulate.

2. method according to claim 1, wherein the degree of depth of each blind hole is greater than 3um, and greater than the wafer epitaxy layer thickness.

3. method according to claim 1 also comprises:

Before electroplating the n-electrode metal, deposition n-semiconductor alloy is on blind pore wall; With

Fill up metal to the blind pore wall to form a n-electrode contacts.

4. method according to claim 3, wherein the step of thinning sapphire substrate comprises that a kind of mechanical thinning method of use comes the thinning sapphire substrate to expose the n-electrode contacts.

5. method according to claim 3, described a plurality of semiconductor layers of growing on growth substrate comprise growth a n-GaN layer, an active layer and a p-GaN layer, and wherein the n-GaN layer growth is on sapphire substrate, and active layer is grown on the n-GaN layer, the p-GaN layer growth is on active layer

Behind a plurality of semiconductor layers of growth, also comprise:

N-table top of etching;

Deposit a kind of n-semiconductor alloy at n-GaN layer place;

Deposit a kind of p-semiconductor alloy on the p-GaN layer;

Grow a passivation layer above all n-semiconductor alloys;

Apply a p-electrode to the p-semiconductor alloy; With

Cut to form a plurality of semiconductor elements along the device isolation channel.

6. method of making accurate vertical structure light-emitting device, the method comprises:

A sapphire substrate is provided;

The a plurality of semiconductor layers of growth on sapphire substrate, a plurality of semiconductor layers comprise a n-GaN layer, an active layer and a p-GaN layer, and wherein the n-GaN layer growth is on sapphire substrate, and active layer is grown on the n-GaN layer, and the p-GaN layer growth is on active layer;

The a plurality of semiconductor layers of etching and generation device isolation channel, it forms a plurality of separable semiconductor elements;

The a plurality of semiconductor layers of etching are to form at least one hole in a plurality of semiconductor layers, and at least one hole is etched to sapphire substrate;

N-table top of etching is on active layer and p-GaN layer;

Bore at least one blind hole on the position at least one hole of a plurality of semiconductor layers in sapphire substrate, wherein the blind pore wall in each blind hole has been determined in boring;

Deposit a kind of p-semiconductor alloy on the p-GaN layer;

Deposit a kind of n-semiconductor alloy at the n-GaN place;

Deposit a kind of n-semiconductor alloy along blind pore wall;

Electroplate a kind of n-electrode metal at least one blind hole, the n-electrode metal is filled up each blind hole to form a n-electrode contacts;

Grow a passivation layer above all n-semiconductor alloys;

Apply a p-electrode to the p-semiconductor alloy;

The thinning sapphire substrate is to expose the n-electrode contacts; With

Cut to form a plurality of semiconductor devices along the device isolation channel.

7. method according to claim 6, wherein at least one blind hole is from the drilled sky of aufwuchsplate of semiconductor layer.

8. method according to claim 6, wherein the degree of depth of at least one blind hole is greater than 3um, and greater than the wafer epitaxy layer thickness.

9. method according to claim 6, wherein the n-electrode contacts is a copper, at least one blind hole is to be filled copper to form the n-electrode contacts by chemical plating.

10. method according to claim 6, wherein the n-electrode contacts is a copper, at least one blind hole is to be filled copper to form the n-electrode contacts by plating.

11. method according to claim 6, wherein the n-electrode contacts is a nickel, and at least one blind hole is to be filled nickel to form the n-electrode contacts by chemical plating.

12. method according to claim 6, wherein the n-electrode contacts is a nickel, and at least one blind hole is to be filled nickel to form the n-electrode contacts by plating.

13. method according to claim 6, wherein the p-electrode metal is silicon or copper.

14. method according to claim 6, wherein the p-electrode metal is a larger area p-electrode, and the size of p-electrode equals a separable semiconductor device.

15. method according to claim 6, wherein the step of thinning sapphire substrate comprises that a kind of mechanical thinning method of use comes the thinning sapphire substrate to expose the n-electrode contacts.

16. method according to claim 6, wherein the n-semiconductor alloy is connected to the n-GaN layer on n-GaN layer the same side, and the p-semiconductor alloy is connected to the p-GaN layer.

17. an accurate vertical structure light-emitting device comprises:

A sapphire substrate;

Be grown in a plurality of semiconductor layers on the sapphire substrate, these a plurality of semiconductor layers comprise a n-GaN layer, an active layer and a p-GaN layer, wherein the n-GaN layer growth is on sapphire substrate, and active layer is grown on the n-GaN layer, and the p-GaN layer growth is on active layer;

Be etched in a plurality of holes in a plurality of semiconductor layers, each hole all is etched in the sapphire substrate, and a plurality of sapphire blind holes in sapphire substrate, each Kong Yuyi sapphire blind hole alignment is to form hole wall, be deposited a n-semiconductor alloy at the bottom of hole wall and the hole, and the n-semiconductor alloy links to each other with n-GaN to form a n-electrode contacts;

N-table top in active layer and p-GaN layer, the n-table top is electroplated a kind of n-electrode metal, and the n-electrode metal links to each other with the n-semiconductor alloy, and a passivation layer is grown in n-semiconductor alloy top; With

A p-semiconductor alloy layer is deposited on the p-GaN layer, and a p-electrode is bonded to the p-semiconductor alloy.

18. accurate vertical structure light-emitting device according to claim 17, wherein the n-semiconductor alloy is connected to the n-GaN layer on n-GaN layer same side, and the p-semiconductor alloy is connected to the p-GaN layer.

19. accurate vertical structure light-emitting device according to claim 17, wherein the n-electrode contacts is a copper, and at least one blind hole is to be filled copper to form the n-electrode contacts by chemical plating.

20. accurate vertical structure light-emitting device according to claim 17, wherein the n-electrode contacts is a copper, and at least one blind hole is to be filled copper to form the n-electrode contacts by plating.

21. accurate vertical structure light-emitting device according to claim 17, wherein the n-electrode contacts is a nickel, and at least one blind hole is to be filled nickel to form the n-electrode contacts by chemical plating.

22. accurate vertical structure light-emitting device according to claim 17, wherein the n-electrode contacts is a nickel, and at least one blind hole is to be filled nickel to form the n-electrode contacts by plating.

23. accurate vertical structure light-emitting device according to claim 17, wherein the p-electrode is silicon or copper.

24. accurate vertical structure light-emitting device according to claim 17, wherein the p-electrode is a large-area p-electrode, and the size of p-electrode equals a separable semiconductor device.

25. accurate vertical structure light-emitting device according to claim 17, wherein the p-electrode is a kind of conducting metal, and it covers the whole surface of accurate vertical structure light-emitting device.

26. accurate vertical structure light-emitting device according to claim 17, the n-semiconductor alloy that wherein is deposited over n-table top place is connected to along the n-electrode metal of hole wall and nose end plating.

27. accurate vertical structure light-emitting device according to claim 17, wherein the n-electrode metal is the emission side at accurate vertical structure light-emitting device.

28. accurate vertical structure light-emitting device according to claim 17, wherein the n-semiconductor alloy is an opposite side that is grown in the emission side of accurate vertical structure light-emitting device.

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