CN101702328B - Three-dimensional memory element and method of operation thereof - Google Patents

Abstract

A three-dimensional memory (3D memory) is composed of multi-layer memory. Each layer of memory includes m word lines, n bit lines and a plurality of starting switch layers. Wherein m and n are natural numbers. The starting switch layer is composed of a chalcogenide material. There are two starting switch layers Ci _,j+1 and Ci _+1,j in the area surrounded by word line i, word line i+1 and bit line j, bit line j+1, while there is no starting switch layer in the area surrounded by word line i+1, word line i+2 and bit line j, bit line j+1. Wherein, i is an odd number and 1≤i≤m-1; j is a natural number and j＝1～n-1; the above-mentioned starting switch layer Ci _,j+1 represents the starting switch layer connecting word line i and bit line j+1; and the above-mentioned starting switch layer Ci _+1,j represents the starting switch layer connecting word line i+1 and bit line j. Each starting switch layer and the connected word line and the connected bit line constitute a memory core.

Description

Three-dimensional memory element and method of operation thereof

The present invention is a divisional application with the original application number 200510105365.1, the application date is September 23, 2005, and the invention name is "chalcogenide storage device"

technical field

The present invention relates to a storage device, and more particularly to a three-dimensional storage device without an access transistor (access transistor) and its operating method.

Background technique

A typical storage unit includes a steering element, such as one or more transistors (transistors are transistors, hereinafter referred to as transistors), for accessing each storage unit. The access transistor can also be a diode (a diode is a diode, hereinafter referred to as a diode), which provides a word line for accessing a bit line of a storage unit. Especially for reading and writing data of the memory cell, the access transistor can act as a pass gate for word line to bit line access. For example, dynamic random access memory (DRAM), flash memory (flash memory), static random access memory (SRAM), traditional chalcogenide (chalcogenide) memory, European memory (ovonic unified memory, OUM) ) or phase-change random access memory (PCRAM) requires transistors or PN diodes as steering elements or addressing elements. In DRAM, the steering element is a transistor and the data is stored in a capacitor. Similarly, six transistors are required in SRAM. But making transistors requires high-quality silicon, and when transistors are made on silicon wafers, some problems arise. Therefore, it is difficult to fabricate a three-dimensional (3D) memory with transistors on a silicon wafer.

A viable solution is to use polysilicon p-n junctions (p-n junction) as the storage for the steering element. However, this method has certain drawbacks. For example, most of these memory types are limited to one time programmable memory (OTP), which requires high programming voltage and high process temperature. This high process temperature would hinder the use of aluminum (Al) and copper (Cu) wires. For example, the maximum process temperature for aluminum is 500°C, and the process temperature range for copper is about 400-500°C. Since aluminum and copper are commonly used interlayer wiring metals, excluding these two metals will make interlayer wiring more difficult. In addition, when the three-dimensional memory is manufactured by packaging technology, the bonding alignment between layers will become very difficult. Based on the aforementioned viewpoint, there is a need for a memory cell structure capable of selectively accessing core memory cells without access transistors.

Contents of the invention

The present invention does this by using an initial threshold-switching material that can be programmed to perform the function of a steering element without requiring access transistors that can be used as steering elements for accessing a memory core cell.

The present invention further provides a three-dimensional memory (3D memory) composed of multi-layer memory. Each storage layer includes m word lines, n bit lines and most initial switch layers. Among them, m and n are natural numbers. The initial switching layer is composed of a chalcogenide material. There are two initial switching layers C _{i,j+1 and C i+1,j in the area surrounded by word line i, word line i+1} and bit line j, bit _{line j+1} , and in the area surrounded by word line There is no initial switch layer in the area surrounded by i+1, word line i+2, bit line j, and bit line j+1. Among them, i is an odd number and 1≤i≤m-1; j is a natural number and j=1~n-1; the above-mentioned initial switch layer C _{i, j+1} represents the starting point of connecting word line i and bit line j+1 and the above-mentioned initial switch layer C _{i+1, j} represents the initial switch layer connecting the word line i+1 and the bit line j. Each initial switch layer and the connected word lines and connected bit lines form a memory core. Each memory core has a first initial voltage of a low voltage value and a second initial voltage of a high voltage value, the first initial voltage corresponds to a first storage state of the initial switch layer, the second initial The voltage corresponds to a second storage state of the memory. When the voltage value between the word line and the bit line is the first initial voltage, the initial switch layer is gated and in the first storage state, when the voltage value between the word line and the bit line is When it is the second start voltage, the start switch layer is gated and is in the second storage state, and when the word line and the bit line are floating, the start switch layer is in a non-gate state.

The present invention further provides a method for accessing memory cores in the above-mentioned three-dimensional memory, and the method includes the following steps. Firstly, a threshold voltage for accessing one of the memory cores is determined. Then, an initial switch material of the memory core is programmed so that the memory core can be accessed at the initial voltage. Next, a voltage is applied to a word line communicating with the memory core. If the voltage is at least equal to the initial voltage, the memory core can be accessed.

The present invention further provides a method for reading the above-mentioned 3D chalcogenide memory element, which includes the following steps. First, a read voltage is applied to a word line. The read voltage can be used to directly access the memory core corresponding to the selected word line. Then, a zero bias is applied on the bit line corresponding to the word line. Next, the value stored in the memory core is read.

Anyone familiar with the present invention can clearly understand that the present invention can be applied to many storage/solid state devices. A significant advantage of the memory core is that it eliminates the need for access transistors that serve as steering elements for transmitting signals to the memory core. In addition, the present invention can reduce the programming voltage required by the memory core, and can also reduce its process temperature. The present invention will facilitate the fabrication of three-dimensional memories, which may be non-volatile and fast memories.

The above summary of the invention and the embodiments disclosed below are only used to explain examples of the implementation of the present invention, but they are not intended to limit the present invention.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1A is a schematic diagram of a memory core according to an embodiment of the present invention.

FIG. 1B is a schematic diagram of a memory core according to an embodiment of the present invention.

2A and 2B are schematic diagrams of a three-dimensional memory formed by stacking memory cores.

FIG. 2C is a schematic cross-sectional view of a three-dimensional memory manufactured by stacking memory cores.

FIG. 3A is a schematic diagram of an array of memory cores forming a layer.

FIG. 3B is a schematic diagram of a memory core array connected to bit lines and word lines of a selection circuit.

FIG. 3C is a schematic diagram of a three-dimensional memory with multiple layers.

FIG. 3D shows an array of memory cores forming multiple layers, which is part of a three-dimensional memory.

4A-4D are schematic diagrams of programming techniques that may be applied to chalcogenide memory devices.

5A to 5C illustrate methods for reading a device according to three embodiments of the present invention.

102, 108: top electrode

104, 110: initial switch layer

106, 112: Bottom electrodes

114: Select circuit

202, 210, 214, 222: word lines

204, 212, 216, 220: initial switch layer

206, 208, 218: bit lines

304, 310, 318: word lines

306, 314, 320: initial switch layer

302, 312, 316: bit lines

308: Select components

311: Storage array layer

317: memory core

408s, 408r: storage unit

408a to 408n: storage unit

Vthl: low starting voltage

Vthh: High starting voltage

Vp, Vpl, Vph: bias voltage

Detailed ways

The present invention eliminates the need for access transistors by incorporating an initiation switch into a memory cell. In one embodiment, the starting switch material is a chalcogenide material. Further information on Vth adjustment of materials capable of changing the threshold voltage Vth is disclosed in US Pat. No. 10/465,120.

In one embodiment, the transistor-like properties of the starting switch material can be used to simplify the memory cell structure without the need for a steering element, such as an access transistor or a P-N diode. Apparently, those skilled in the art can implant logic circuits on the chalcogenide memory cells to form a system on a chip (SoC). Furthermore, for chalcogenides, once the non-volatile nature is programmed, read and write operations can be performed relatively quickly. It is worth noting that the programming voltage associated with the initial switching material (for example, chalcogenide material) is much lower than that of flash read only memory (ROM). For example, the programming voltage of a chalcogenide memory cell is about 5 volts (V), while that of a flash ROM is about 10 volts.

The chalcogenide storage unit has the dual function of guiding element and storage element. Therefore, it is much easier to make just a chalcogenide memory than to combine a transistor and a chalcogenide memory cell. In addition, when the storage unit is used as a guide element, its wafer volume will be smaller than that of a storage with separate guide elements and storage units with the same storage capacity. In contrast, with the same reservoir volume, a dual functioning chalcogenide reservoir will be able to provide a higher storage capacity than a reservoir with separate guide elements and storage units. A small-sized chalcogenide memory element would be able to pass higher currents than an access transistor. In this embodiment, using the chalcogenide material as the starting switch material is just an example, and is not limited to the chalcogenide material. Any material with the properties of the chalcogenide material, such as stable and adjustable threshold voltage (Vth) characteristics, can be used for the non-volatile dual-function memory cell.

1A and 1B are schematic diagrams of a memory core according to an embodiment of the present invention. The memory core cell shown in FIG. 1A includes a top electrode 102 and a bottom electrode 106 and a threshold-switching layer 104 disposed between the top electrode 102 and the bottom electrode 106 . The top electrode 106 can be metal, metalloid, semiconductor, or silicide, or other materials with stable and adjustable threshold characteristics.

Similarly, FIG. 1B is another embodiment of the memory core. In this embodiment, the memory core includes a top electrode 108 and a bottom electrode 112 and an initial switch layer 110 disposed between first ends of the top electrode 108 and the bottom electrode 112 . A first end of the bottom electrode 112 is connected to the initial switch layer 110 and a second end of the bottom electrode 112 is connected to the selection circuit 114 . The selection circuit 114 can select a bit line and a word line corresponding to a memory cell.

2A and 2B are schematic views of a storage device formed by stacking the memory cores shown in FIGS. 1A and 1B . FIG. 2A includes a word line 202 and a bit line 206 . Of course, in some embodiments, 206 may represent a word line and 202 may represent a bit line. FIG. 2A further includes an initial switch layer 204 disposed between the word line 202 and the bit line 206 . The wordlines 202 and bitlines 206 may be electrodes similar to those in FIGS. 1A and 1B . Each memory core can be stacked on top of another memory core to form a memory element.

Figure 2B is similar to Figure 2A, except for the individual layers that make up the memory core. In this embodiment, the memory core includes a bit line 208 and a word line 210 . Of course, in some embodiments, 208 may represent a word line and 210 may represent a bit line. The initial switch layer 212 is located under the word line 210 . Thus, each layer of the stack includes a bit line 208 , a word line 210 and an initial switch layer 212 .

FIG. 2C is a schematic cross-sectional view of a three-dimensional memory manufactured by stacking the memory cores shown in FIGS. 2A and 2B . FIG. 2C includes a word line 214 and a bit line 218 . FIG. 2C further includes an initial switch layer 216 disposed between the word line 214 and the bit line 218 . Likewise, another initial switch layer 220 is disposed between the bit line 218 and the word line 222 .

A three-dimensional memory can be manufactured by stacking the above-mentioned array of memory cores. FIG. 3A is a schematic diagram of an array of memory cores of FIGS. 2A and 2B . The reservoir arrays can be stacked to form a three-dimensional reservoir. Each memory core in the array of memory cores includes a bit line 302 , a word line 304 , and an initial switch layer 306 disposed between the word line 304 and the bit line 302 .

FIG. 3B is a schematic diagram of a memory core array similar to that described in FIG. 3A . In one embodiment of the present invention, the selection elements 308 of the word lines 304 and the bit lines 302 are connected to the outer edge of the memory core array. Although the selection element 308 shown in FIG. 3B is a transistor, the selection element may also be a P-N diode, Schottky diodes or tunneling diodes. FIG. 3C is a schematic diagram of a three-dimensional memory with multiple layers. FIG. 3C includes multiple memory array layers 311 . Each memory array layer 311 includes a plurality of word lines 310 , bit lines 312 and an initial switch layer 314 .

3D is a schematic diagram of a three-dimensional memory manufactured by stacking memory core arrays according to an embodiment of the present invention. Each storage layer 317 includes a plurality of bit lines 316 , a plurality of word lines 318 and an initial switch layer 320 disposed between the bit lines 316 and the word lines 318 .

More specifically, a three-dimensional memory (3D memory) is composed of a multilayer memory. Each storage layer includes m word lines WL ₁ , WL ₂ . . . WL _m , n bit lines BL ₁ , _{BL 2} . Among them, m and n are natural numbers. This three-dimensional memory only has two initial switch layers C i,j+1 and C i+1,j in the area surrounded by word line i, word line i ₊₁ and bit line _{j, bit line j+1} . Among them, i is an odd number and 1≤i≤m-1; j is a natural number and j=1~n-1; the above-mentioned initial switch layer C _{i, j+1} represents the starting point of connecting word line i and bit line j+1 The initial switch layer; the above initial switch layer C _i+1,j represents the initial switch layer connecting the word line i+1 and the bit line j.

The initial switching layers (C _i,j+1 and C _i+1,j ) 320 are composed of chalcogenide materials. Each initial switch layer and the connected word lines and connected bit lines form a memory core. Taking the memory core composed of the initial switch layer C _i,j+1 , word line i and word line i+1 as an example, it has a first initial voltage with a low voltage value and a second initial voltage with a high voltage value. The initial voltage corresponds to the first storage state of the initial switching layer C _i,j+1 , and the second initial voltage corresponds to the second storage state of the initial switching layer C _i,j+1 . When the voltage value between the word line WL _i and the bit line BL _j+1 is the first start voltage, the start switch layer C _{i, j+1} is gated and in the first storage state, when the word line WL _i and the bit line BL j+1 are in the first storage state. When the voltage value between the bit line BL _j+1 is the second initial voltage, the initial switch layer C _{i, j+1} is gated and is in the second storage state, when the word line WL _i and the bit line BL _j+ When ₁ is floating, the initial switch layer C _i,j+1 is in a non-selected state.

In the present invention, since the memory core is both a steering element and a storage unit, there is no need to use a transistor as a steering element. As mentioned above, the omission of the transistor as a steering element effectively eliminates the need for high-quality silicon in the manufacture of the memory. At the same time, the temperature for manufacturing the storage is relatively reduced. Therefore, the multi-layer memory can be fabricated by conventional photo-etching or damascene technology without any inter-layer alignment.

Since the starting switch material acts as a guiding element, the need for additional guiding elements is eliminated. Therefore, an array of memory cores can be easily combined into a three-dimensional memory by fabricating the memory core layer by layer. In addition, it helps to increase memory density by merging multiple layers.

4A-4D are schematic diagrams of programming techniques that may be applied to chalcogenide memory devices. FIG. 4A shows a floating programming technique. Here, it is assumed that the chalcogenide memory element includes two threshold voltages, eg, a low threshold voltage (Vthl) for state 1 and a high threshold voltage (Vthh) for state 0. Figure 4A depicts the bias voltage applied to the memory cell. Unselected memory cells are biased between -Vp and +Vp, and selected cells are biased forward +Vp. Storage cell 408s represents selected cells, and the remaining cells 408a to 408n represent unselected cells. Table 1 summarizes the programming methods of program 1 and program 0.

Table 1

Program 1 Program 0 Selected bit line 0 0 other bit lines floating floating Selected word line Vpl Vph Other word lines floating floating

With the biases shown in Table 1, the selected bit line is zero and the selected word line is either Vpl or Vph depending on the program or selected state.

Figure 4B shows a bias programming technique. The graph of Figure 4B represents the applied bias voltage. Here, a voltage (bias) may be applied to unselected word lines and bit lines. A forward +Vp bias is applied to the selected cell 408s. It may be assumed that the chalcogenide memory element comprises two start voltages, for example a low start voltage (Vthl) as state 1 and a high start voltage (Vthh) as state 0. Table 2 below lists the programming methods of program 1 and program 0.

Table 2

Program 1 Program 0 Selected bit line 0 0 other bit lines 0≤V≤Vp 1 0≤V≤Vph Selected word line Vp 1 Vph Other word lines 0≤V≤Vpl 0≤V≤Vph

With the biases shown in Table 2, the selected bit line is zero, and the selected word line is either Vpl or Vph depending on the program or selected state. It is worth noting that two embodiments of the bias programming method, namely the V/2 method and the V/3 method, can be employed, as shown in FIGS. 4C and 4D , respectively. Of course, other bias programming methods can also be used as the programming method of the present invention, so the method described here is only used as an embodiment but not limited to this embodiment.

FIG. 4C is a schematic diagram of the V/2 method. Figure 4C depicts the bias applied to the memory cell. A forward +Vp bias is applied to the selected memory cell 408s, while a forward +Vp/2 bias is applied to the remaining unselected memory cells. It can be assumed that the chalcogenide memory element includes two start voltages, namely a low start voltage (Vthl) as state 1 and a high start voltage (Vthh) as state 0. The programming methods of state 1 and state 0 are listed in Table 3 below.

table 3

Program 1 Program 0 Selected bit line 0 0 other bit lines Vpl /2 Vph/2 Selected word line Vpl Vph Other word lines Vpl /2 Vph/2

The biases shown in Table 3, the selected bit line is zero, and the selected word line is either Vpl or Vph depending on the program or selected state.

FIG. 4D is a schematic diagram of the V/3 method. FIG. 4D depicts the bias applied to the memory cell. The selected memory cell 408s is applied with forward +Vp bias, and the remaining other unselected memory cells have one of the following two characteristics, that is, some unselected memory cells are applied with forward bias Voltage +Vp/3, while some unselected memory cells are reverse biased -Vp/3. The storage cell 408f is applied with a forward bias of +Vp/3, while the storage cell 408r is applied with a reverse bias of -Vp/3. It may be assumed that the chalcogenide memory element comprises two start voltages, namely a low start voltage (Vthl) as state 1 and a high start voltage (Vthh) as state 0. The programming methods for state 1 and state 0 are listed in Table 4 below.

Table 4

Program 1 Program 0 Selected bit line 0 0 other bit lines 2Vpl/3 2Vph/3 Selected word line Vpl Vph Other word lines Vpl/3 Vph/3

With the bias shown in Table 4, the selected bit line is zero, and the selected word line is Vpl or Vph depending on the program or selected state. It should be noted that the limited range of the programming voltage can be: "Vthh<Vp<3Vthl".

The reading method includes a floating method and a bias method. The floating method involves applying a bias voltage between Vthl and Vthh on the selected word line (or bit line) and a bias voltage Vr of zero bias applied on the selected word line (or bit line), while Other word lines and bit lines are floating. The biasing method involves a bias between Vthl and Vthh applied to the selected word line (or bit line) and a bias voltage Vr of zero bias applied to the selected word line (or bit line), while Other word lines and bit lines are applied with fixed bias voltages in the range of 0<V<Vthl. In the present invention, two different biasing methods are provided, that is, the V/2 method and the V/3 method.

5A to 5C respectively illustrate a method for reading a device according to an embodiment of the present invention. 5A to 5C each represent a bias voltage applied to a memory cell. FIG. 5A represents a floating method in which the bias voltage is from -Vr to +Vr and the selection cell 408s is forward biased to +Vr. FIG. 5B represents a V/2 reading method, in which the selection unit 408s applies a forward bias voltage +Vr. As shown in FIG. 5B, the remaining unselected cells are forward biased by +Vr/2. FIG. 5C represents a V/3 reading method, and the selection unit 408s is applied with a forward bias +Vr. The remaining unselected cells in FIG. 5C are applied with a forward bias of +Vr/3 or a reverse bias of -Vr/3. It is worth noting that the unselected cells in Figure 5C form a pattern similar to that in Figure 4D.

In summary, the present invention provides a memory core without using access transistors for accessing core memory cells. In other words, when the core cell incorporates an initial switching material, such as a chalcogenide material, the core memory cell can be accessed by programming the core memory cell. In essence, the initial switching material can also be used as a steering element by programming. Anyone familiar with the present invention will appreciate that a simplified way of decoding logic signals to access transistors can also be provided, so that the present invention does not require access transistors.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any skilled person can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined in the scope of the appended patent application.

Claims (14)

1. A kind of three-dimensional storage device, is made of multi-layer storage device, is characterized in that each layer storage device comprises: m word lines, wherein m is a natural number; n bit lines, where n is a natural number; A plurality of initial switching layers are composed of chalcogenide materials, and there are only two initial switching layers C _i in the area surrounded by word line i, word line i+1, bit line j, and bit line j+1 _{, j+1} and C _{i+1, j} , in i is an odd number, 1≤i≤m-1; j is a natural number, j=1～n-1; The aforementioned initial switch layer C _{i, j+1} represents the initial switch layer connecting word line i and bit line j+1; The above initial switch layer C _{i+1, j} represents the initial switch layer connecting word line i+1 and bit line j; The initial switch layer C _{i, j+1} and the word line i connected to it and the bit line j+1 connected to form a memory core, and the initial switch layer C _{i+1, j} connected to the The word line i+1 and the connected bit line j form a storage core, and each storage core has a first starting voltage of a low voltage value and a second starting voltage of a high voltage value, and the first starting voltage The initial voltage corresponds to a first storage state of the initial switching layer C _i,j+1 , and the second initial voltage corresponds to a second storage state of the initial switching layer C _i,j+1 ; When the voltage value between the word line i and the bit line j+1 is the first start voltage, the corresponding start switch layer C _{i, j+1} is gated and in the first storage state, when When the voltage value between the word line i and the bit line j+1 is the second initial voltage, the corresponding initial switch layer C _i,j+1 is gated and in the second storage state, when When the word line i and the bit line j+1 are floating, the initial switch layer C _{i, j+1} is in a non-selected state, When the voltage between the word line i+1 and the bit line j is the first initial voltage, the corresponding initial switch layer C _i+1,j is gated and is in the first storage state when the When the voltage value between the word line i+1 and the bit line j is the second initial voltage, the corresponding initial switch layer C _i+1,j is gated and in the second storage state, when the When the word line i+1 and the bit line j are floating, the initial switch layer is in a non-selected state. 2. The three-dimensional memory according to claim 1, wherein said word line comprises a metal material or a type of metal material. 3. The three-dimensional memory according to claim 1, wherein the bit line comprises a semiconductor material or silicide. 4. The memory core of claim 3, wherein the semiconductor material comprises silicon. 5. The three-dimensional memory as claimed in claim 1, wherein the initial switch layer can be used to provide a non-volatile memory. 6. The three-dimensional storage according to claim 1, wherein the first storage state is represented as state 1, and the second storage state is represented as state 0. 7. A method for accessing a storage core in a three-dimensional storage, the three-dimensional storage is composed of multi-layer storage, and each storage layer includes: m word lines, wherein m is a natural number; n bit lines, where n is a natural number; A plurality of initial switching layers are composed of chalcogenide materials, and there are only two initial switching layers C _i in the area surrounded by word line i, word line i+1, bit line j, and bit line j+1 _{, j+1} and C _{i+1, j} , in i is an odd number, 1≤i≤m-1; j is a natural number, j=1～n-1; The aforementioned initial switch layer C _{i, j+1} represents the initial switch layer connecting word line i and bit line j+1; The above initial switch layer C _{i+1, j} represents the initial switch layer connecting word line i+1 and bit line j; The initial switch layer C _{i, j+1} and the word line i connected to it and the bit line j+1 connected to form a memory core, and the initial switch layer C _{i+1, j} connected to the The word line i+1 and the connected bit line j form a storage core, and each storage core has a first starting voltage of a low voltage value and a second starting voltage of a high voltage value, and the first starting voltage The initial voltage corresponds to a first storage state of the initial switching layer C _i,j+1 , and the second initial voltage corresponds to a second storage state of the initial switching layer C _i,j+1 ; When the voltage value between the word line i and the bit line j+1 is the first start voltage, the corresponding start switch layer C _{i, j+1} is gated and in the first storage state, when When the voltage value between the word line i and the bit line j+1 is the second initial voltage, the corresponding initial switch layer C _i,j+1 is gated and in the second storage state, when When the word line i and the bit line j+1 are floating, the initial switch layer C _{i, j+1} is in a non-selected state, When the voltage between the word line i+1 and the bit line j is the first initial voltage, the corresponding initial switch layer C _i+1,j is gated and is in the first storage state when the When the voltage value between the word line i+1 and the bit line j is the second initial voltage, the corresponding initial switch layer C _i+1,j is gated and in the second storage state, when the When the word line i+1 and the bit line j are floating, the initial switch layer C _{i+1, j} is in a non-selected state, It is characterized in that it includes: determining that an initial voltage for accessing one of the memory cores is the first initial voltage or the second initial voltage; programming an initial switch layer of the memory core to enable access to the memory core at the first initial voltage or the second initial voltage; applying a first voltage to a word line; and If the first voltage is at least equal to the first starting voltage or the second starting voltage, the memory core can be accessed. 8. The method for accessing a memory core in a three-dimensional memory according to claim 7, wherein the initial switch layer of the memory core is programmed so that the memory can be accessed at the initial voltage The steps for the core of the device include: adopting a floating technique or a bias technique. 9. The method for accessing a memory core in a three-dimensional memory according to claim 7, further comprising: denying access to the memory core if the first voltage is lower than the initial voltage. 10. A method for reading a three-dimensional storage element, the three-dimensional storage is composed of multi-layer storage, and each layer of storage includes: m word lines, wherein m is a natural number; n bit lines, where n is a natural number; A plurality of initial switching layers are composed of chalcogenide materials, and there are only two initial switching layers C _i in the area surrounded by word line i, word line i+1, bit line j, and bit line j+1 _{, j+1} and C _{i+1, j} , in i is an odd number, 1≤i≤m-1; j is a natural number, j=1～n-1; The aforementioned initial switch layer C _{i, j+1} represents the initial switch layer connecting word line i and bit line j+1; The above initial switch layer C _{i+1, j} represents the initial switch layer connecting word line i+1 and bit line j; The initial switch layer C _{i, j+1} and the connected word line i and the connected bit line j+1 constitute a memory core, and the above-mentioned initial switch layer C _{i+1, j} and the connected word line The word line i+1 and the connected bit line j form a storage core, and each of the storage cores has a first initial voltage of a low voltage value and a second initial voltage of a high voltage value, and the first initial initial voltage a voltage corresponding to a first storage state of the initial switching layer C _i,j+1 , the second initial voltage corresponding to a second storage state of the initial switching layer C _i,j+1 ; When the voltage value between the word line i and the bit line j+1 is the first start voltage, the corresponding start switch layer C _{i, j+1} is gated and in the first storage state, when When the voltage value between the word line i and the bit line j+1 is the second start voltage, the start switch layer C _{i, j+1} is gated and in the second storage state, when the word When the line i and the bit line j+1 are floating, the initial switch layer C _{i, j+1} is in a non-selected state, When the voltage between the word line i+1 and the bit line j is the first initial voltage, the corresponding initial switch layer C _i+1,j is gated and is in the first storage state when the When the voltage value between the word line i+1 and the bit line j is the second initial voltage, the corresponding initial switch layer C _i+1,j is gated and in the second storage state, when the When the word line i+1 and the bit line j are floating, the initial switch layer C _{i+1, j} is in a non-selected state, It is characterized in that it includes: applying a read voltage to a selected word line, and the read voltage can be used to directly access the memory core corresponding to the selected word line; applying a zero bias to the bit line corresponding to the selected word line; and Read a value stored in the memory core. 11. The method for reading a three-dimensional memory device according to claim 10, further comprising: maintaining unselected word lines and unselected bit lines in a floating state. 12. The method for reading a three-dimensional memory element according to claim 10, further comprising: A first bias voltage is applied to unselected word lines and a second bias voltage is applied to unselected bit lines. 13. The method for reading a three-dimensional memory element according to claim 12, wherein, determining an initial voltage to be the first initial voltage or the second initial voltage; The first bias voltage and the second bias voltage are less than the initial voltage, and the range of the first bias voltage and the second bias voltage is between 0.1V and 20V . 14. The method for reading a three-dimensional memory element according to claim 12, wherein said first bias voltage is approximately one-third of a read voltage on a selected word line and said first bias voltage is The second bias voltage is two-thirds of the read voltage on the selected word line.

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