CN101728286B - A Method for Suppressing Electromigration Failure of Solder Interconnect Bumps - Google Patents
A Method for Suppressing Electromigration Failure of Solder Interconnect Bumps Download PDFInfo
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- CN101728286B CN101728286B CN2008102281377A CN200810228137A CN101728286B CN 101728286 B CN101728286 B CN 101728286B CN 2008102281377 A CN2008102281377 A CN 2008102281377A CN 200810228137 A CN200810228137 A CN 200810228137A CN 101728286 B CN101728286 B CN 101728286B
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- Prior art keywords
- bumps
- solder
- interconnection
- electromigration
- electromigration failure
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 24
- 230000000694 effects Effects 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000005204 segregation Methods 0.000 claims abstract 2
- 238000012360 testing method Methods 0.000 claims description 21
- 238000013508 migration Methods 0.000 claims description 17
- 238000011056 performance test Methods 0.000 claims description 2
- 230000005012 migration Effects 0.000 claims 2
- 230000006835 compression Effects 0.000 claims 1
- 238000007906 compression Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract 1
- 230000004907 flux Effects 0.000 description 9
- 238000003466 welding Methods 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 7
- 230000005764 inhibitory process Effects 0.000 description 5
- 238000005498 polishing Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 230000001476 alcoholic effect Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 244000137852 Petrea volubilis Species 0.000 description 1
- JWVAUCBYEDDGAD-UHFFFAOYSA-N bismuth tin Chemical compound [Sn].[Bi] JWVAUCBYEDDGAD-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- Wire Bonding (AREA)
Abstract
本发明涉及微电子封装领域的微互连结构的可靠性，具体地说是一种抑制焊料互连凸点电迁移失效的方法，适用于抑制焊料互连凸点电迁移失效，提高互连凸点结构的可靠性。采用力学加载的方法，对焊料互连凸点施加2-30％的塑性变形，经过预应变的互连凸点显示出良好的抗电迁移性能。互连凸点在电迁移失效中常见的“极性效应”得到抑制，互连凸点焊料中元素的偏聚也被有效阻止，从而显著提高了凸点的机械强度。此外，空洞及金属小丘在互连凸点上的形成也被抑制，这也减少了互连凸点因电迁移导致断路及凸点间短路的危险。因此，该方法可以有效抑制互连凸点的电迁移失效，满足当前集成度不断提高的倒装芯片中互连凸点结构可靠性的要求，具有广泛的应用范围。
The invention relates to the reliability of micro-interconnection structures in the field of microelectronic packaging, in particular to a method for suppressing electromigration failure of solder interconnection bumps, which is suitable for suppressing electromigration failure of solder interconnection bumps and improving interconnection bumps. The reliability of the point structure. Using the method of mechanical loading, 2-30% plastic deformation is applied to the solder interconnect bumps, and the pre-strained interconnect bumps show good anti-electromigration performance. The common "polarity effect" of interconnect bumps in electromigration failure is suppressed, and the segregation of elements in the interconnect bump solder is also effectively prevented, thereby significantly improving the mechanical strength of the bumps. In addition, the formation of voids and metal hillocks on the interconnect bumps is also suppressed, which also reduces the risk of interconnect bumps causing open circuits and inter-bump shorts due to electromigration. Therefore, the method can effectively suppress the electromigration failure of interconnection bumps, meet the reliability requirements of interconnection bump structures in flip chips with increasing integration, and has a wide range of applications.
Description
Technical field
The present invention relates to the reliability of little interconnection structure in microelectronics Packaging field; Specifically a kind of method that suppresses electromigration invalidation of welding flux interconnected salient points; Be applicable to and suppress welding flux interconnected salient points (as shown in Figure 1) electromigration invalidation, improve the interconnected salient points reliability of structure.This method can be widely used in electronics industry, aerospace and general engineering.
Background technology
The microminiaturization of electronic product and high performance order about the integrated circuit size to be continued to reduce, and correspondingly, as connecting and the size of the solder bump of conduction bridge also sharply reduces, thereby brings a series of integrity problems, wherein outstanding with electromigration especially.
Electromigration is meant conductive metallic material under the high current density condition, and a kind of phenomenon of diffusion takes place along the electron stream direction for metallic atom in the conductor or ion.Electromigration makes negative electrode produce the cavity because of moving out of atom, can cause interconnection structure to open circuit when serious; At anode, form " hillock " because of moving into of atom, cause short circuit.These two kinds of basic failure modes all are enough to cause the irreversible destruction of little interconnection structure.Therefore, the electromigration invalidation problem has caused the extensive concern of domestic and international academia and industrial quarters.
At present, the electromigration invalidation of inhibition welding flux interconnected salient points still lacks effective method and technology.Alloying (promptly through adding the electromigration invalidation that ternary usually suppresses solder bump) is though be the electromigratory method of a kind of inhibition interconnected salient points; But seek suitable interpolation element and become a bottleneck; And inhibition DeGrain, this method just rest on the theoretical aspect at present.Therefore, the method for seeking more simple inhibition interconnected salient points electromigration invalidation becomes the key issue that improves the interconnected salient points reliability.
Summary of the invention
Actual conditions in view of above-mentioned prior art; The purpose of this invention is to provide a kind of method that suppresses electromigration invalidation of welding flux interconnected salient points; It is simple and effectively suppresses the method for flip chip interconnects salient point electromigration invalidation, is fit to the demand of current microelectronics Packaging bumps interconnection structure reliability.
For realizing above purpose, technical scheme of the present invention is following:
A kind of method that suppresses electromigration invalidation of welding flux interconnected salient points applies the prefabricated plastic deformation of 2-30% to welding flux interconnected salient points.Then, the interconnected salient points of plastic pre-strain is carried out electromigration performance test, as a comparison with the electromigration invalidation of strainless interconnected salient points.After the plastic pre-strain processing, the polar effect of interconnected salient points and element gather phenomenon partially and are suppressed, and its phenomenon that produces cavity and metal hillock is prevented from.
Among the present invention, at high current density (current density range 1 * 10<sup >4</sup>A/cm<sup >2</sup>～1 * 10<sup >6</sup>A/cm<sup >2</sup>) under test respond well, at low current density (100A/cm<sup >2</sup>≤current density<1 * 10<sup >4</sup>A/cm<sup >2</sup>) effect is more excellent down, in lower current density (0<current density<100Acm<sup >2</sup>) under, have better effect!
Among the present invention, prefabricated plastic deformation is stretching plastic deformation or compressive plastic deformation etc.
Plastic pre-strain of the present invention has very big adjustable range, can satisfy the demand of the interconnected salient points of different size.
The present invention is applicable to the flip chip interconnects salient point, and other welding flux interconnected body.
The method that the present invention adopts mechanics to load applies the plastic deformation of 2-30% (being preferably 2-20%) to welding flux interconnected salient points, demonstrates good deelectric transferred performance through the interconnected salient points of prestrain.Interconnected salient points common " polar effect " in electromigration invalidation is inhibited, the gathering partially also of element in the interconnected salient points scolder by effective prevention, thus significantly improved the mechanical strength of salient point.In addition, cavity and the formation of metal hillock on interconnected salient points also are suppressed, this reduced also that interconnected salient points causes opening circuit because of electromigration and salient point between risk of short-circuits.Therefore, this method can effectively suppress the electromigration invalidation of interconnected salient points, satisfies the requirement of interconnected salient points structural reliability in the flip-chip that current integrated level improves constantly, and is with a wide range of applications.
The present invention has following advantage:
When 1, employing was of the present invention, " polar effect " of intermetallic compound was suppressed.Through after the prestrain, under the function of current, compound no longer takes place interconnected salient points peels off and assembles (like Fig. 3, shown in 4,5) in the formation of anode in the decomposition of negative electrode, has improved the mechanical strength of bump interconnect structure greatly.
When 2, employing was of the present invention, metallic element was effectively suppressed toward the phenomenon that anode gathers partially.Through prestrain, interconnected salient points is under the function of current, and the solder metal element gathers by effective prevention (like Fig. 7, shown in 8) toward anode partially, and its mechanical property is greatly improved.
When 3, employing was of the present invention, interconnected salient points opened circuit and the phenomenon of short circuit is effectively controlled.Because after the prestrain, under the function of current, the element of salient point gathers by effective inhibition partially, the metal hillock of while bump surface is also by effective prevention, thereby salient point opens circuit and the condition of short circuit is broken.
4, the inventive method is simple for process, and is applied widely, can be widely used in electronics industry, aerospace and general engineering.
Description of drawings
The flipchip-bumped interconnection sketch map that Fig. 1 is suitable for for the inventive method.Among the figure, 1 chip; 2 solder bumps; 3 printed circuit board (PCB)s; Metal layer under 4 salient points; 5 pad metal layers.
Fig. 2 is the stress strain curve of SnAgCu/Cu salient point prestrain 20%.
Fig. 3 is the interface micro-organization chart of SnAgCu/Cu salient point prestrain 5% back electro-migration testing.
Fig. 4 is the interface micro-organization chart of SnAgCu/Cu salient point prestrain 10% back electro-migration testing.
Fig. 5 is the interface micro-organization chart of SnAgCu/Cu salient point prestrain 20% back electro-migration testing.
The interface micro-organization chart of electro-migration testing when Fig. 6 does not have strain for the SnAgCu/Cu salient point.
Fig. 7 is the interface micro-organization chart of SnBi/Cu salient point prestrain 10% back electro-migration testing.
Fig. 8 is the interface micro-organization chart of SnBi/Cu salient point prestrain 20% back electro-migration testing.
The interface micro-organization chart of electro-migration testing when Fig. 9 does not have strain for the SnBi/Cu salient point.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
As shown in Figure 1; The flipchip-bumped interconnected relationship that the inventive method is suitable for is: be connected through solder bump 2 between chip 1 and the printed circuit board (PCB) 3; Being metal layer 4 under the salient point between chip 1 and the solder bump 2, is pad metal layer 5 between printed circuit board (PCB) 3 and the solder bump 2.
Embodiment 1: the electromigration invalidation analysis of Sn3.0Ag0.5Cu/Cu interconnected salient points after the prestrain
In order to eliminate current gathering effect, present embodiment has adopted the sandwich bump interconnect structure of Cu/Sn3.0Ag0.5Cu/Cu.At first polish polishing to two Cu pieces, on the Cu sample, be coated with last layer SAC soldering paste then, adopt the BGA&CSP reclamation work station of U.S. ok company to weld, the suffered maximum temperature of its solder joint is 260 ℃, the 90 seconds above time of scolder fusing point (217 ℃).To weld appearance again and adopt line to be cut into the cuboid appearance that the cross section is 700 μ m * 700 μ m, and polish and polishing through sand paper, finally being prepared into the cross section is the cuboid sample of 300 μ m * 300 μ m.Then on the small sample fatigue tester, the salient point sample is carried out 5%, 10% and 20% stretching plastic deformation (as shown in Figure 2, as 20% to be example to stretch), strain rate is 10
-3/ s.After carrying out prestrain, the salient point sample carries out electro-migration testing.Its test condition is that current density is 10
4A/cm
2The order of magnitude, be 182 hours conduction time.Sample behind the electro-migration testing through polishing again, adopts FeCl
3The alcoholic solution corrosion is with the institutional framework at its interface of scanning electron microscopic observation, like Fig. 3, shown in 4,5.From Fig. 3,4,5 can find out, the electromigration solder bump after handling through prestrain, and the institutional framework of the compound on its anode and cathode interface is identical, and so-called " polar effect " do not take place, i.e. the anode compound phenomenon thicker than cathode compound.
Comparative example 1: the electromigration invalidation analysis of strainless Sn3.0Ag0.5Cu/Cu salient point
The test specimens that employing is made with quadrat method is not having under the condition of prestrain, carries out electro-migration testing according to embodiment 1, and its interface microstructure is as shown in Figure 6.Can find that from Fig. 6 cathode compound decomposes to be peeled off, and anode compound thickens obviously, and so-called " polar effect " taken place.
Embodiment 2: the electromigration invalidation analysis of Sn58Bi/Cu salient point after the prestrain
According to the method for embodiment 1, in order to eliminate current gathering effect, present embodiment has adopted the sandwich bump interconnect structure of Cu/Sn58Bi/Cu equally.Adopt and handle the Cu piece in the same way, on the Cu sample, be coated with last layer tin bismuth soldering paste then, adopt the BGA&CSP reclamation work station of U.S. ok company to weld, the suffered maximum temperature of its solder joint is 170 ℃, and scolder fusing point (140 ℃) the above time is 90 seconds.Becoming the cross section to sample preparation according to the mode of embodiment 1 then is the cuboid sample of 300 μ m * 300 μ m.Then on the small sample fatigue tester, the salient point sample is carried out 10% and 20% stretching plastic deformation, strain rate is 10
-3/ s.After carrying out prestrain, the salient point sample carries out electro-migration testing.Its test condition is that current density is 10
4A/cm
2The order of magnitude, be 182 hours conduction time.Sample behind the electro-migration testing through polishing again, adopts FeCl
3The alcoholic solution corrosion is with the institutional framework (the continuous Bi layer of enrichment at the interface) at its interface of scanning electron microscopic observation, like Fig. 7, shown in 8.From Fig. 7,8 can find out, the electromigration solder bump after handling through prestrain, and its Bi significantly reduces (comparison diagram 9) toward the quantity that anode gathers partially.
Comparative example 2: the electromigration invalidation analysis of strainless Sn58Bi/Cu salient point
The test specimens that employing is made with quadrat method is not having under the condition of prestrain, carries out electro-migration testing according to embodiment 2, and its interface microstructure is as shown in Figure 9.Can find that from Fig. 9 what the Bi element was a large amount of accumulates near the anodic interface.In contrast to the interconnected salient points electro-migration testing that applies 10% and 20% prestrain, after handling through prestrain, the diffusion of Bi is effectively suppressed.Data show, interconnected salient points is applied prestrain after, Bi elemental diffusion amount can reduce 60% with respect to the electro-migration testing result who does not have prestrain.Thereby its mechanical property is more excellent.
Suppress the solder bump electromigration invalidation with alloying and compare, technology of the present invention is simple, and practicability and effectiveness has range of application more widely.This method can suppress the generation of interface compound " polar effect ", can suppress gathering partially of the past anode of Bi element effectively, can reduce the formation of bump surface metal hillock effectively, opens circuit and risk of short-circuits property thereby reduced circuit.The present invention can improve the reliability of interconnected salient points effectively, thereby has improved the reliability of IC and components and parts, for the microminiaturization of electronic product and the development of high performance provide the foundation.Equally, this method also can be widely used in electronics industry, aerospace and general engineering.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102281377A CN101728286B (en) | 2008-10-17 | 2008-10-17 | A Method for Suppressing Electromigration Failure of Solder Interconnect Bumps |
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|---|---|---|---|
| CN2008102281377A CN101728286B (en) | 2008-10-17 | 2008-10-17 | A Method for Suppressing Electromigration Failure of Solder Interconnect Bumps |
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| Publication Number | Publication Date |
|---|---|
| CN101728286A CN101728286A (en) | 2010-06-09 |
| CN101728286B true CN101728286B (en) | 2012-02-08 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867610B2 (en) * | 2002-11-27 | 2005-03-15 | Advanced Micro Devices, Inc. | Test structure for determining the stability of electronic devices comprising connected substrates |
| CN1815724A (en) * | 2005-02-01 | 2006-08-09 | 安捷伦科技有限公司 | Routing design to minimize electromigration damage to solder bumps |
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2008
- 2008-10-17 CN CN2008102281377A patent/CN101728286B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867610B2 (en) * | 2002-11-27 | 2005-03-15 | Advanced Micro Devices, Inc. | Test structure for determining the stability of electronic devices comprising connected substrates |
| CN1815724A (en) * | 2005-02-01 | 2006-08-09 | 安捷伦科技有限公司 | Routing design to minimize electromigration damage to solder bumps |
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| Publication number | Publication date |
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| CN101728286A (en) | 2010-06-09 |
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