CN101728380A - Source follower and process structure thereof - Google Patents
Source follower and process structure thereof Download PDFInfo
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- CN101728380A CN101728380A CN200810121914A CN200810121914A CN101728380A CN 101728380 A CN101728380 A CN 101728380A CN 200810121914 A CN200810121914 A CN 200810121914A CN 200810121914 A CN200810121914 A CN 200810121914A CN 101728380 A CN101728380 A CN 101728380A
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 230000000694 effects Effects 0.000 abstract description 7
- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
The invention provides a source follower which comprises an NMOS transistor and a current source, and is characterized in that a gate of the NMOS is taken as an input end, a drain is connected with a power supply, a source is connected with the current source, the current source is grounded, and a substrate of the NMOS is in short connection with the source of the NMOS. The invention further provides a process structure of the source follower, which comprises a P substrate, a P well, P diffusion and N diffusion, and is characterized in that the process structure adopts an N well, an N buried layer and a P buried layer which are independent respectively for separating the P substrate from the P diffusion and realizing the connection of the potential of the P well of the NMOS with the source. The source follower can reduce the body effect and reduce the source drain voltage, and is applicable to low-voltage work.
Description
Technical field
The present invention relates to circuit and process structure thereof, especially source follower circuit and the process structure thereof of device.
Background technology
The source follower of traditional as shown in Figure 1 NMOS, the substrate ground connection of NMOS.Need low-voltage power supply at some, perhaps signal swing had in the circuit of requirement, need the source with source-drain voltage V
GSLittle as far as possible, the common mode electrical level translation circuit of the source follower that employing as shown in Figure 4 is traditional, wherein, VDD is the supply voltage of common mode electrical level translation circuit, and Vin1 is the input of common mode electrical level translation circuit, and Vout1 is the output of common mode electrical level translation circuit, V
GS1, V
GS2Be respectively transistor M1, the source-drain voltage of M2, V
GS4Be the source-drain voltage of M4, V
ThpBe PMOS pipe M4 threshold voltage, (| V
GS4|-| V
Thp|) be the overdrive voltage of transistor M4
Vin|
min＝Vout1|
min+V
GS2+V
GS1
Vin|
Max＝VDD-(|V
GS4|-|V
thp|)
Because two sources are with NMOS bulk effect relation, transistor M1, the source-drain voltage V of M2
GS1, V
GS2Can be bigger, be issued to about 1.1V such as normal conditions, suppose Vout1|
MinBe 200mV, so Vin|
MinBe 2.4V, if (| V
GS4|-| V
Thp|) overdrive voltage of transistor M4 is 200mV, then Vin|
MaxFor about VDD-0.2V, the amplitude of oscillation of circuit requirement Vin will arrive 500mV, and then the VDD minimum is wanted 3.1V, and the VDD minimum voltage that provides of chip is that 2.7-2.8V requires and can not reach like this, and bulk effect can introduce non-linearly, and small signal gain also can be less than normal.
Summary of the invention
The present invention is intended to solve the deficiencies in the prior art, and a kind of bulk effect that reduces is provided, and reduces source-drain voltage V
GSSource follower, this source follower is fit to low voltage operating.
The present invention also provides a kind of process structure that adopts two trap BiCMOS technology source followers.
A kind of source follower comprises a nmos pass transistor and current source, and the grid that it is characterized in that described NMOS is as input, and drain electrode connects power supply, and source electrode connects current source, current source ground connection, the substrate of NMOS and nmos source short circuit.
A kind of process structure of source follower comprises P substrate, P trap, P diffusion and N diffusion, it is characterized in that adopting independently N trap, N buried regions, P buried regions that the P substrate is kept apart with the P diffusion, realizes the P trap potential of NMOS and being connected of source electrode.
Aforesaid source follower adopts BiCMOS technology.
Source follower is applied to the common mode electrical level translation circuit of telecar detection module, it is characterized in that of the input of the grid of NMOS pipe M0 as common mode electrical level translation circuit, the source ground of M0, the drain electrode of M0 connects the grid of NMOS M1 and the drain electrode of PMOS M4, the source electrode of M4 connects power supply, nmos pass transistor M1, the drain electrode of M2 connects power supply, the source electrode of M1 connects current source, current source ground connection, the source shorted of M1 substrate and M1, the grid of M2 connects the source electrode of M1, the substrate of M2 and the source shorted of M2, the source electrode of M2 connects the output Vout1 of the drain electrode of NMOS pipe M3 as common mode electrical level translation circuit, the source ground of M3, and the grid of M4 and M3 connects fixed bias.
Vin|
min＝Vout1|
min+V
GS1+V
GS2
Vin|
Max＝VDD-(|V
GS4|-|V
thp|)
Wherein, Vin1 is the input of common mode electrical level translation circuit, Vin|
MinAnd Vin|
MaxRepresent minimum voltage and the peak pressure of Vin respectively, Vout1 is the output of common mode electrical level translation circuit, Vout1|
MinBe the minimum voltage of output Vout1, V
GS1, V
GS2Be respectively M1, the source-drain voltage of M2, VDD are supply voltage, V
GS4Be the source-drain voltage of M4, V
ThpBe threshold voltage, (| V
GS4|-| V
Thp|) be the overdrive voltage of transistor M4.
Because bulk effect has been eliminated with NMOS, V in two sources
GS1, V
GS2Diminish, under these process conditions, be generally below the 0.9V, suppose Vout1|
MinMinimum is 200mV, Vin| so
MinBe 2.0V, and if (| V
GS4|-| V
Thp|) overdrive voltage of transistor M4 is 200mV, Vin|
MaxFor about VDD-0.2V, if the amplitude of oscillation of Vin2 will arrive 500mV so, then the VDD minimum is wanted 2.7V, the VDD minimum voltage meets the index request of 2.7-2.8V like this, and eliminated the non-linear of bulk effect introducing, the traditional relatively connection of small signal gain can be more accurate, the synchronous signal gain also can approach 1 more because of the elimination of bulk effect, obtains bigger output voltage swing at the Vout1 place.
Description of drawings:
The NMOS source follower that Fig. 1 is traditional
Fig. 2 NMOS source follower of the present invention
Fig. 3 NMOS source follower of the present invention process structure figure
Fig. 4 adopts the common mode electrical level translation circuit of traditional source follower
Fig. 5 adopts the common mode electrical level translation circuit of source follower provided by the invention
Embodiment
Below in conjunction with accompanying drawing content of the present invention is further specified.
A kind of source follower as shown in Figure 2, comprises a nmos pass transistor and current source, and the grid that it is characterized in that described NMOS is as input, and drain electrode connects power supply, and source electrode connects current source, current source ground connection, the substrate of NMOS and nmos source short circuit.
A kind of process structure of source follower as shown in Figure 3, comprises P substrate, P trap, P diffusion and N diffusion, it is characterized in that adopting independently N trap, N buried regions, P buried regions that the P substrate is kept apart with the P diffusion, realizes the P trap potential of NMOS and being connected of source electrode.
Aforesaid source follower adopts BiCMOS technology.
Source follower is applied to the common mode electrical level translation circuit of telecar detection module, it is characterized in that of the input of the grid of NMOS pipe M0 as common mode electrical level translation circuit, the source ground of M0, the drain electrode of M0 connects the grid of NMOS M1 and the drain electrode of PMOS M4, the source electrode of M4 connects power supply, nmos pass transistor M1, the drain electrode of M2 connects power supply, the source electrode of M1 connects current source, current source ground connection, the source shorted of M1 substrate and M1, the grid of M2 connects the source electrode of M1, the substrate of M2 and the source shorted of M2, the source electrode of M2 connects the output Vout1 of the drain electrode of NMOS pipe M3 as common mode electrical level translation circuit, the source ground of M3, and the grid of M4 and M3 connects fixed bias.
Be to be understood that to be that the foregoing description is just to explanation of the present invention, rather than limitation of the present invention, anyly do not exceed the replacement of the unsubstantiality in the connotation scope of the present invention or the innovation and creation of modification all fall within the protection range of the present invention.
Claims (4)
1. a source follower comprises a nmos pass transistor and current source, and the grid that it is characterized in that described NMOS is as input, and drain electrode connects power supply, and source electrode connects current source, current source ground connection, the substrate of NMOS and nmos source short circuit.
2. the process structure of a source follower comprises P substrate, P trap, P diffusion and N diffusion, it is characterized in that adopting independently N trap, N buried regions, P buried regions that the P substrate is kept apart with the P diffusion, realizes the P trap potential of NMOS and being connected of source electrode.
3. the process structure of source follower as claimed in claim 2 is characterized in that adopting BiCMOS technology.
4. adopt a kind of common mode electrical level translation circuit of source follower as claimed in claim 1, it is characterized in that of the input of the grid of NMOS pipe MO as common mode electrical level translation circuit, the source ground of MO, the drain electrode of MO connects the grid of NMOS M1 and the drain electrode of PMOS M4, the source electrode of M4 connects power supply, nmos pass transistor M1, the drain electrode of M2 connects power supply, the source electrode of M1 connects current source, current source ground connection, the source shorted of M1 substrate and M1, the grid of M2 connects the source electrode of M1, the substrate of M2 and the source shorted of M2, the source electrode of M2 connects the output Vout1 of the drain electrode of NMOS pipe M3 as common mode electrical level translation circuit, the source ground of M3, and the grid of M4 and M3 connects fixed bias.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810121914A CN101728380A (en) | 2008-10-22 | 2008-10-22 | Source follower and process structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810121914A CN101728380A (en) | 2008-10-22 | 2008-10-22 | Source follower and process structure thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101728380A true CN101728380A (en) | 2010-06-09 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810121914A Pending CN101728380A (en) | 2008-10-22 | 2008-10-22 | Source follower and process structure thereof |
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| CN (1) | CN101728380A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1469476A (en) * | 2002-06-25 | 2004-01-21 | ������������ʽ���� | semiconductor integrated circuit device |
| CN1542946A (en) * | 2003-04-30 | 2004-11-03 | 上海贝岭股份有限公司 | Method for making semiconductor integrated circuit and products produced thereby |
| US6927460B1 (en) * | 2002-02-15 | 2005-08-09 | Fairchild Semiconductor Corporation | Method and structure for BiCMOS isolated NMOS transistor |
| US20070134854A1 (en) * | 2005-12-13 | 2007-06-14 | Chartered Semiconductor Manufacturing, Ltd | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process |
-
2008
- 2008-10-22 CN CN200810121914A patent/CN101728380A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6927460B1 (en) * | 2002-02-15 | 2005-08-09 | Fairchild Semiconductor Corporation | Method and structure for BiCMOS isolated NMOS transistor |
| CN1469476A (en) * | 2002-06-25 | 2004-01-21 | ������������ʽ���� | semiconductor integrated circuit device |
| CN1542946A (en) * | 2003-04-30 | 2004-11-03 | 上海贝岭股份有限公司 | Method for making semiconductor integrated circuit and products produced thereby |
| US20070134854A1 (en) * | 2005-12-13 | 2007-06-14 | Chartered Semiconductor Manufacturing, Ltd | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process |
Non-Patent Citations (1)
| Title |
|---|
| 毕查德拉扎维: "《模拟CMOS集成电路设计》", 28 February 2003 * |
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Application publication date: 20100609 |