CN101740619B - Nano-wire field effect transistor - Google Patents
Nano-wire field effect transistor Download PDFInfo
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- CN101740619B CN101740619B CN2008102265092A CN200810226509A CN101740619B CN 101740619 B CN101740619 B CN 101740619B CN 2008102265092 A CN2008102265092 A CN 2008102265092A CN 200810226509 A CN200810226509 A CN 200810226509A CN 101740619 B CN101740619 B CN 101740619B
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- 239000002070 nanowire Substances 0.000 title claims abstract description 35
- 230000005669 field effect Effects 0.000 title claims abstract description 33
- 239000011258 core-shell material Substances 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- 239000002210 silicon-based material Substances 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 abstract description 17
- 230000000694 effects Effects 0.000 description 33
- 238000005036 potential barrier Methods 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- 239000002159 nanocrystal Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- Thin Film Transistor (AREA)
Abstract
本发明公开一种纳米线场效应晶体管。该晶体管是由栅电极、源区、漏区、中心区和栅介质层组成；其中，中心区为芯-壳结构，该芯-壳结构同轴；栅介质层全包围中心区，栅电极全包围栅介质层；源区和漏区分别位于中心区的两侧。其中，中心区的芯结构为绝缘体材料，壳结构为半导体材料；该壳结构材料的掺杂类型及掺杂浓度可调。该芯-壳结构的长度、壳半径以及芯半径可调；另外，该晶体管中，栅介质层、栅电极层、源区和漏区的材料均可调，栅介质层的厚度、源区和漏区材料的掺杂类型及掺杂浓度均可调。绝缘体芯结构的引入能有效降低传统纳米线晶体管的关态电流，提高器件的电流开关比，同时该晶体管受短沟道效应引起的阈值电压漂移以及漏致势垒降低效应的影响更小，尺寸缩小的性能更加优良。The invention discloses a nanowire field effect transistor. The transistor is composed of a gate electrode, a source region, a drain region, a central region and a gate dielectric layer; wherein, the central region is a core-shell structure, and the core-shell structure is coaxial; the gate dielectric layer completely surrounds the central region, and the gate electrode is completely The gate dielectric layer is surrounded; the source region and the drain region are respectively located on both sides of the central region. Wherein, the core structure in the central region is an insulator material, and the shell structure is a semiconductor material; the doping type and doping concentration of the shell structure material are adjustable. The length, shell radius and core radius of the core-shell structure are adjustable; in addition, in the transistor, the materials of the gate dielectric layer, the gate electrode layer, the source region and the drain region are all adjustable, and the thickness of the gate dielectric layer, the source region and the The doping type and doping concentration of the material of the drain region can be adjusted. The introduction of the insulator core structure can effectively reduce the off-state current of the traditional nanowire transistor and improve the current switching ratio of the device. Reduced performance is even better.
Description
Technical field
The present invention relates to the semiconductor integrated circuit device, particularly relate to a kind of nano-wire field effect transistor.
Background technology
Making semiconductor device high-speed, low-power consumption is the actuating force that semi-conductor industry develops.The planar technique field-effect transistor is subjected to the restriction of short-channel effect and gate current increase in the trend of scaled down.New nonplanar device structure is suggested, and comprises silicon-on-insulator, double grid, three grid and nano-wire field effect transistor.Wherein nano-wire field effect transistor can provide high current on/off ratio, and it is less to be subjected to short-channel effect and leakage to cause potential barrier reduction effects simultaneously.Further improve current on/off ratio on the basis of existing nano-wire field effect transistor, improving size, to dwindle performance semiconductor integrated circuit high-speed to making, low-power consumption significant.
Summary of the invention
The purpose of this invention is to provide a kind of nano-wire field effect transistor.
Nano-wire field effect transistor provided by the invention is made up of gate electrode, source region, drain region, center and gate dielectric layer;
Wherein, the center is a core-shell structure, and this core-shell structure is coaxial; Gate dielectric layer surrounds the center entirely, gate electrode all-around-gate dielectric layer; Source region and drain region lay respectively at the both sides of center.
In the above-mentioned nano-wire field effect transistor, the cored structure of center is an insulating material, and shell structure is a semi-conducting material, and the doping type and the doping content of this shell structure material are adjustable, is 1 * 10 as boron doping concentration
11Cm
-3Boron doped silicon materials or boron doping concentration 2 * 10
12Cm
-3Boron doped germanium material.The length of this core-shell structure, shell radius and core radius all can be regulated as required; In addition, in this transistor, the material in gate dielectric layer, gate electrode layer, source region and drain region is all adjustable, as the silicon materials of the optional phosphorus doping in source region and drain region or the germanium material of arsenic doping; Wherein, in the silicon materials of phosphorus doping, the doping content of phosphorus is 1 * 10
20Cm
-3In the germanium material of arsenic doping, the doping content of arsenic is 1 * 10
20Cm
-3In addition, the doping type of the thickness of gate dielectric layer, source region and drain region material and doping content are all adjustable.
Nano-wire field effect transistor provided by the invention, has insulator core-semiconductor shell structure, compare with traditional nano-wire transistor, in identical grid material, channel material and doping content, source-drain area material and doping content, gate insulation layer material and thickness, under the condition of identical channel region length, channel region radius (core-shell structure is the shell radius), can effectively reduce the off-state current of device behind introducing insulator core-semiconductor shell structure, reduce the quiescent dissipation of device, improve the current on/off ratio of device.Under the condition that technology allows, suitably increase this advantage that the core-shell structure core radius can further be brought into play device.The introducing of insulator core-semiconductor shell structure simultaneously can make nano-wire field effect transistor be subjected to short-channel effect and leak and cause potential barrier and reduce the threshold voltage shift that effect causes and reduce, and improves the performance of device dimensions shrink.The present invention optimizes for the nano-wire field effect transistor device performance, and structure optimization has indicated a direction.
Description of drawings
Fig. 1 is the schematic cross-section of nano-wire field effect transistor provided by the invention.
Fig. 2 is the influence of core-shell structure to the silicon nano line transistor transfer characteristic curve.
Fig. 3 is that core-shell structure is to silicon nano line transistor on-off ratio Effect on Performance.
Fig. 4 is subjected to short-channel effect to cause the comparison of threshold voltage shift for core-shell structure to silicon nano line transistor.
Leakage under different channel lengths causes potential barrier reduction effect relatively to Fig. 5 to silicon nano line transistor for core-shell structure.
Fig. 6 is the influence of core-shell structure to Ge nanoline transistor transfer characteristic curve.
Fig. 7 compares Effect on Performance for core-shell structure to the Ge nanoline transistor switch.
Fig. 8 is subjected to short-channel effect to cause the comparison of threshold voltage shift for core-shell structure to the Ge nanoline transistor.
Leakage under different channel lengths causes potential barrier reduction effect relatively to Fig. 9 to the Ge nanoline transistor for core-shell structure.
Embodiment
The present invention is further elaborated below in conjunction with specific embodiment, but the present invention is not limited to following examples.
Nano-wire field effect transistor provided by the invention, its structure are by gate electrode 1 as shown in Figure 1, source region 2, and drain region 3, the core segment 4 of core-shell structure, the shell part 5 of core-shell structure and gate dielectric layer 6 are formed.The gate electrode 1 full channel region that surrounds device.Source, leakage two ends are positioned at the both sides of core-shell structure channel region.Core-shell structure is coaxial.
The silicon nanowires field-effect transistor and the Performance Detection thereof of embodiment 1, core shell structure
The structure of this nano-wire field effect transistor as shown in Figure 1, wherein, the work function of gate electrode 1 material is made as 4.61 electronvolt, source region 2 and drain region 3 are that phosphorus doping density is 1 * 10
20Cm
-3Silicon materials, core segment 4 is a silica, shell part 5 is a boron doping concentration 1 * 10
11Cm
-3Silicon materials, gate dielectric layer 6 is the silica of thickness 2nm.The shell radius of this core-shell structure is 10nm, and the length of core-shell structure is 0.1 micron, and core radius is adjustable.
Above-mentioned transistor can be prepared according to existing method, and preparation flow is summarized as follows:
1) on silicon wafer, etches the silicon post with circular silicon nitride hard mask; The silicon column dimension is dwindled in high-temperature oxydation, corrosion, reaches the core size of setting, and oxidation forms cored structure;
2) shell structure is made in the epitaxy technique autoregistration, and high-temperature oxydation, corrosion reduce shell structure thickness and reach set point; Heat growth gate oxide;
3) finish the preparation of grid structure; Wide-angle is injected phosphorus and annealing, the preparation source-drain area;
4) standard CMOS process is finished the metal electrode preparation.
Respectively electric current output characteristic, on-off ratio, threshold voltage and the leakage of this transistor device caused potential barrier and reduce effect and detect, the gained result is respectively as Fig. 2-shown in Figure 5.
Wherein, Fig. 2 is the influence curve figure of core radius to si-nanocrystals pipe transfer characteristic, and wherein, channel length is 100nm, and drain terminal voltage is 2V.As known in the figure, the nano-wire field effect transistor of introducing insulator core-semiconductor shell structure and traditional nano-wire transistor specific energy mutually effectively reduce off-state current, and ON state current only has faint reduction.The core radius that increases core-shell structure can further be brought into play this advantage.After core radius was adjusted into 8nm, the off-state current of device was reduced to 1/13rd of traditional nano-wire transistor off-state current.
Fig. 3 is that the core radius of core-shell structure is to si-nanocrystals pipe on-off ratio Effect on Performance.As known in the figure, along with the core-shell structure core radius increases from 0 (corresponding traditional nano-wire field effect transistor), the current on/off ratio of the nano-wire field effect transistor of insulator core-semiconductor shell is continuing to increase.After core radius increased to 8nm, the current on/off ratio of device had reached 3.6 * 10
10, to compare with traditional nano-wire field effect transistor, on-off ratio has increased 11 times.
Fig. 4 is subjected to short-channel effect to cause the comparison of threshold voltage shift for the core radius of core-shell structure to the si-nanocrystals pipe.As known in the figure, traditional nano-wire field effect transistor short-channel effect after channel length narrows down to 30nm is very obvious, and the relative 0.1 micron channel length devices drift value of threshold voltage is 26 millivolts.Can suppress the drift of threshold voltage to a great extent and introduce insulator core-semiconductor shell structure.When the core-shell structure core radius was made as 3nm, this drift value of threshold voltage was reduced to 19 millivolts.Increasing the core-shell structure core radius makes this advantage more obvious.When the core-shell structure core radius was made as 8nm, the drift value of threshold voltage only was 6 millivolts.Thereby show that insulator core-semiconductor shell structural nano field of line effect transistor can also suppress short-channel effect when increasing the device current on/off ratio, improve the performance of device dimensions shrink.
Leakage under different channel lengths causes potential barrier and reduces effect relatively Fig. 5 to the si-nanocrystals pipe for the core radius of core-shell structure.As known in the figure, traditional nano-wire field effect transistor after channel length narrows down to 30nm because of leakage cause potential barrier reduce the threshold voltage that causes reduce reached 140 millivolts.This is unfavorable at a high speed, the design of low consumption circuit.Insulator core-semiconductor shell structural nano field of line effect transistor can effectively reduce the influence of drain terminal voltage to the device source end under identical channel length, reduce to leak to cause potential barrier reduction effect.That this advantage can be brought into play behind the increase structural core radius is more obvious.Equaling 8nm with core radius is example, after channel length narrows down to 30nm, leak cause that potential barrier reduces threshold voltage that effect causes reduce to be almost 23 millivolts.
The Ge nanoline field-effect transistor and the Performance Detection thereof of embodiment 2, core shell structure
The structure of this nano-wire field effect transistor still as shown in Figure 1, wherein, the work function of gate electrode 1 material is made as 4.33 electronvolt, source region 2 and drain region 3 are that arsenic doping concn is 1 * 10
20Cm
-3Germanium, core segment 4 is a silica, shell part 5 is a boron doping concentration 2 * 10
12Cm
-3Germanium material, gate dielectric layer 6 is the silica of thickness 1.5nm.The shell radius of this core-shell structure is made as 10nm, and the length of core-shell structure is 100nm, and core radius is adjustable.
Respectively electric current output characteristic, on-off ratio, threshold voltage and the leakage of this transistor device caused potential barrier and reduce effect and detect, the gained result is respectively as Fig. 6-shown in Figure 9.
Wherein, Fig. 6 is the influence curve figure of core radius to Ge nanoline transistor transfer characteristic, and wherein, channel length is 100 nanometers, and drain terminal voltage is 2V.The result who shows with Fig. 2 is consistent, and the nano-wire field effect transistor of introducing insulator core-semiconductor shell structure can effectively reduce off-state current, and ON state current changes in very narrow scope.Increasing core radius can make the reduction of off-state current more obvious.After core radius was adjusted into 8nm, the off-state current of device was reduced to about 8% of traditional nano-wire transistor.
Fig. 7 be the core radius of core-shell structure to the Ge nanoline transistor switch than Effect on Performance, wherein, channel length is 100nm, raceway groove (shell) radius is 10nm.Consistent with the result of Fig. 3, along with the core-shell structure core radius increases since 0, the current on/off ratio of the nano-wire field effect transistor of insulator core-semiconductor shell is continuing to increase.After core radius increased to 8nm, the current on/off ratio of device had reached 2.14 * 10
7, to compare with traditional Ge nanoline field-effect transistor, on-off ratio has increased 11.6 times.
Fig. 8 is subjected to short-channel effect to cause the comparison of threshold voltage shift for the core radius of core-shell structure to the Ge nanoline transistor.Similar to Fig. 4, introduce insulator core-semiconductor shell structure and can suppress the drift of threshold voltage to a great extent.Equaling 30nm with channel length is example, and when the core-shell structure core radius was made as 3nm, the drift value of threshold voltage was 43 millivolts; When core radius was made as 8nm, the drift value of threshold voltage only was 8 millivolts.Thereby show that once more insulator core-semiconductor shell structural nano field of line effect transistor can effectively suppress short-channel effect when increasing the device current on/off ratio, improve the performance of device dimensions shrink.
Leakage under different channel lengths causes potential barrier reduction effect relatively to Fig. 9 to the Ge nanoline transistor for the core-shell structure core radius.Similar with Fig. 5 result, traditional nano-wire field effect transistor leaks after channel length narrows down to 30nm and causes potential barrier and reduce effect and reach 370 millivolts.Insulator core-semiconductor shell structural nano field of line effect transistor has effectively reduced to leak under identical channel length and has caused potential barrier reduction effect.Equaling 8nm with core radius is example, and leakage causes potential barrier reduction effect and is reduced to 60 millivolts after channel length narrows down to 30nm.
The nano-wire field effect transistor of insulator core provided by the invention-semiconductor shell structure can further reduce the device off-state current on the basis of traditional nano-wire field effect transistor, reduce quiescent dissipation, improve current on/off ratio, be fit to design high-speed, low power consumption integrated circuit.The all right more effective inhibition short-channel effect of this device suppresses leakage and causes potential barrier reduction effect simultaneously, improves the performance of device dimensions shrink.
Claims (9)
1. a nano-wire field effect transistor is made up of gate electrode, source region, drain region, center and gate dielectric layer;
Wherein, described center is a core-shell structure, and described core-shell structure is coaxial; Complete described center, the described gate dielectric layer of the full encirclement of described gate electrode of surrounding of described gate dielectric layer; Described source region and drain region lay respectively at the both sides of described center;
In the described core-shell structure, cored structure is an insulating material, and described shell structure is a semi-conducting material.
2. transistor according to claim 1 is characterized in that: described cored structure is a silica; Described shell structure is boron doped silicon materials or boron doped germanium material.
3. transistor according to claim 2 is characterized in that: in the described boron doped silicon materials, the doping content of boron is 1 * 10
11Cm
-3In the described boron doped germanium material, the doping content 2 * 10 of boron
12Cm
-3Germanium material.
4. according to the arbitrary described transistor of claim 1-3, it is characterized in that: described gate dielectric layer is a silica; Described source region and drain region are heavily doped semi-conducting material.
5. transistor according to claim 4 is characterized in that: described source region and drain region are the silicon materials of phosphorus doping or the germanium material of arsenic doping.
6. transistor according to claim 5 is characterized in that: in the silicon materials of described phosphorus doping, the doping content of phosphorus is 1 * 10
20Cm
-3In the germanium material of described arsenic doping, the doping content of arsenic is 1 * 10
20Cm
-3
7. according to the arbitrary described transistor of claim 1-3, it is characterized in that: the thickness of described gate dielectric layer is 1.5-3nm.
8. transistor according to claim 4 is characterized in that: the thickness of described gate dielectric layer is 1.5-3nm.
9. transistor according to claim 5 is characterized in that: the thickness of described gate dielectric layer is 1.5-3nm.
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| CN102544069A (en) * | 2012-02-16 | 2012-07-04 | 清华大学 | Tunneling transistor with horizontal alignment coaxial cable structure and method for forming tunneling transistor |
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| CN102544094B (en) * | 2010-12-15 | 2015-06-17 | 北京大学 | Nanowire field effect transistor with split-gate structure |
| CN102214586B (en) * | 2011-06-13 | 2013-05-22 | 西安交通大学 | Preparation method of silicon nanowire field effect transistor |
| CN102315129B (en) * | 2011-07-08 | 2013-01-16 | 北京大学 | Preparation method of vertical silicon nanowire field effect transistor |
| CN102969365A (en) * | 2012-12-11 | 2013-03-13 | 北京大学深圳研究院 | Core shell structure nanowire tunneling field effect device |
| CN102969359A (en) * | 2012-12-11 | 2013-03-13 | 深港产学研基地 | Independent grid controlled nano line tunneling field effect device and manufacturing method thereof |
| US9917169B2 (en) | 2014-07-02 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of formation |
| US9425324B2 (en) * | 2014-09-30 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and channel structure thereof |
| CN105304501B (en) * | 2015-10-27 | 2019-08-23 | 中国科学院物理研究所 | A method of preparing three-dimensional gate-all-around structure semiconductor FET device |
| CN108897945B (en) * | 2018-06-26 | 2022-06-21 | 深港产学研基地 | Method for calculating plasma wave velocity in channel of nanowire field effect transistor |
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| CN1839482A (en) * | 2003-08-21 | 2006-09-27 | 哈恩-迈特纳研究所柏林有限公司 | Vertical nanotransistor, its fabrication method and memory structure |
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