CN101741385A - Analog-to-digital converter of shared operational amplifier with adjustable front-stage and back-stage resolutions - Google Patents

Abstract

The present invention relates to a pipelined or cyclic analog-to-digital converter (ADC). The analog-to-digital converter includes at least one series-connected two-stage circuit having different resolution bits. The two stages share an amplifier and their operation is staggered. The front-and-back stage resolution-tunable (stage-resolution-tunable) shared operational amplifier technology can be applied to a pipelined or cyclic analog-to-digital converter, thereby greatly reducing power consumption and increasing operation speed.

Description

Analog-to-digital converter with adjustable front and rear stage resolution and shared operational amplifier

technical field

The present invention relates to an analog-to-digital converter (ADC, hereinafter referred to as ADC), in particular to a stage-resolution converter suitable for a pipelined ADC or a cyclic ADC. scalable) shared operational amplifier technology, thereby significantly reducing the number of operational amplifiers and their power consumption and increasing the speed of operation.

Background technique

In recent years, the rapid development of portable communication and audio-visual electronic devices makes it an urgent need to increase the operating time of the devices. However, since the growth of battery life is slow, reducing power consumption has become an alternative feasible solution to meet this demand.

In the current video application specifications, the pipelined analog-to-digital converter (ADC) is more commonly used than other ADC architectures. The main reason is that the hardware requirements of the pipelined ADC only grow linearly with the increase in resolution, unlike The hardware requirements for flash ADCs are growing exponentially. Taking the application of 10-bit resolution as an example, the hardware requirement of the pipelined ADC is much lower than that of other ADC architectures, which makes the pipelined ADC have advantages in terms of circuit area and power consumption.

Figure 1 shows a traditional pipelined ADC architecture1. The input signal V _in is first sampled by a front-end sample-and-hold amplifier (SHA) 11 to provide a stable hold signal to the subsequent circuit 12 . Each stage circuit 12 parses part of the bits (B) respectively. The analyzed partial bits are synchronized by a delay element 13 , and corrected and integrated by a digital correction circuit 14 to output a complete N-bit digital code (N is the resolution of the ADC). As shown in the expanded block in the figure, each stage circuit 12 includes a sub-analog-to-digital converter (sub-ADC, hereinafter referred to as sub-ADC) 121, a sub-digital-to-analog converter (sub-DAC, hereinafter referred to as sub-DAC) 122 , a sample-and-hold (S/H) circuit 123 , an analog subtractor 124 and an amplifier (G _i ) 125 . The sub-ADC 121 of each stage circuit 12 performs preliminary quantization on the input signal to generate a part of the digital code; the part of the digital code is then converted into a corresponding analog voltage value by the sub-DAC 122 . The converted analog voltage and the sampled input signal are subtracted by a subtractor 124 to generate a residual signal 126 , which represents the quantization error of a part of the digital code of the input signal resolved by the stage circuit. Next, the residual signal 126 is amplified by the amplifier 125 to conform to the signal range of the overall ADC 1 . In this way, the reference voltage of each circuit can be shared, so as to reduce the complexity of system design. Furthermore, since the number of bits to be analyzed by the later-stage circuit becomes smaller and the signal range remains fixed, the accuracy requirement of the later-stage circuit will be lower than that of the previous-stage circuit.

FIG. 2 shows a circuit diagram of a multiplying DAC (MDAC, hereinafter referred to as MDAC) 120 and its operation. The MDAC 120 includes the aforementioned sub-DAC 122 , sample-and-hold amplifier 123 , analog subtractor 124 and amplifier (G _i ) 125 (such as an operational amplifier). In this example, the MDAC 120 is implemented with a switched capacitor circuit as shown in the figure, and each stage resolves 1.5 bits (ie, 1.5 bits/stage). When the clock signal clk1 becomes a high potential ("1"), the MDAC 120 enters the sampling stage. At this time, the amplifier 125 has a unity gain, and its offset (offset) V _os is stored in the capacitors C _f , C The upper plate of _s (ie, near the amplifier 125 input). Then, when the clock signal clk2 becomes a high potential (“1”), the MDAC 120 enters the amplification stage, and at this time, the capacitor C _f is used as a feedback capacitor, and the lower plate of the capacitor C _s is connected to the output voltage V of the sub-DAC 122 _R , thereby amplifying the residual signal and correcting the offset. The accuracy of the MDAC 120 will determine the accuracy of the overall ADC 1 , while the accuracy of the MDAC 120 itself will depend on the performance parameters of the amplifier 125 (eg, gain and bandwidth). Since the amplifier 125 is the largest source of power consumption for the overall DAC 1 , reducing the power consumption of the amplifier 125 will reduce the power consumption of the overall DAC 1 . As mentioned above, the precision requirements of the rear-stage circuit are lower than those of the previous-stage circuit. Therefore, if the amplifier 125 with lower gain and bandwidth is used to implement the latter-stage circuit, the power consumption of the overall circuit can be greatly reduced. However, in this way, the designer must design various operational amplifiers, which will increase the time for circuit design.

Generally speaking, the pipelined ADC 1 with the digital correction circuit 14 can tolerate a relatively large offset; therefore, as long as the tolerance range of the digital correction is not exceeded, the linearity of the overall ADC 1 will not be affected. Therefore, the implementation of MDAC 120 does not require offset correction. For example, when the clock signal clk1 is high (“1”), the amplifier 125 does not need to be connected in a single-gain configuration to store the offset. In other words, the amplifier 125 is idle during the sampling phase, as shown in FIG. 3 . If the idle amplifier 125 can be properly used in the sampling stage, the power consumption of the overall circuit can be further reduced, such as the conventional technique described below.

(1) Double sampling technology

Figure 4 shows a dual-channel TDMA ADC architecture 4 to speed up the operation of the overall ADC. Since the sampling phase and the amplifying phase are mutually staggered, when the channel 40 is in the sampling phase, the other channel 41 is in the amplifying phase, so the two channels do not use the amplifier 42 at the same time. In this way, the operational amplifier 42 can be shared (shared), so that the operation speed of each stage of the circuit can be doubled, or the bandwidth of the amplifier 42 can be halved, thereby greatly reducing the power consumption of the circuit. However, this technique must add an additional set of capacitors (and increase the circuit area) for channel switching. Furthermore, additional circuitry (and its power consumption) needs to be added to overcome channel mismatch issues (eg, timing, offset, gain mismatch).

(2) Shared operational amplifier technology

Since the operations of the front and rear stages of the pipelined ADC are staggered (when one stage is sampling, the other stage is amplified), therefore, the front and rear stages of the circuit can share one operational amplifier, which will reduce the number of operational amplifiers by half , as shown in Figure 5. Each stage of the ADC architecture 5 has the same resolution. The specifications of the shared operational amplifier 52 must meet the precision requirements of the previous stage circuit. Since the accuracy requirement of the subsequent stage (for example, the second stage) circuit will be lower than that of the previous stage (for example, the first stage), this will cause waste of the latter stage circuit. The shared op amp technique consumes more power than the oversampling technique because the bandwidth of the oversampling technique can be cut in half and each stage can be power optimized for the accuracy requirements of that stage. However, on the other hand, the shared operational amplifier technique does not have the channel mismatch problem, so no related correction mechanism is needed, so its circuit design is simpler than that of the oversampling technique.

In view of the disadvantages of various traditional ADC architectures, it is urgent to propose a novel ADC architecture to maintain the advantages of the traditional ADC architecture and avoid its disadvantages.

It can be seen that the above-mentioned existing analog-to-digital converter obviously still has inconveniences and defects in structure and use, and needs to be further improved urgently. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above-mentioned problems. This is obviously the relevant industry. urgent problem to be solved. Therefore, how to create a new type of shared operational amplifier technology suitable for the front and rear stages of the pipeline or loop analog-to-digital converter with adjustable resolution is indeed one of the current important research and development topics, and it has also become a goal that the industry needs to improve. .

In view of the defects of the above-mentioned existing analog-to-digital converters, the inventor actively researches and innovates based on his rich practical experience and professional knowledge in the design and manufacture of such products for many years, and cooperates with the application of academic theories, in order to create a new type of analog-to-digital converter. The shared operational amplifier technology applicable to the front and rear stages of the pipeline or circular analog-to-digital converter with adjustable resolution can improve the general existing analog-to-digital converter and make it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.

Contents of the invention

The main purpose of the present invention is to overcome the defects of existing analog-to-digital converters, and provide a new type of shared operational amplifier technology suitable for the adjustable resolution of the front and rear stages of pipelined or circular analog-to-digital converters. The technical problem solved is to make it greatly reduce the number of operational amplifiers and their power consumption and increase the operating speed, which is very suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. An analog-to-digital converter proposed according to the present invention includes: at least one set of secondary circuits connected in series, wherein the secondary circuits have different resolution bits; and a first amplifier shared by the secondary circuits, wherein The operations of the secondary circuits are staggered from each other.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned analog-to-digital converter, when one of the secondary circuits of the group is sampling, the other stage is amplifying, and the secondary circuit does not use the amplifier at the same time.

In the above-mentioned analog-to-digital converter, the front-stage circuits of the second-stage circuits of the group resolve fewer bits than the latter-stage circuits of the same group, and the front-end stage circuits of the analog-to-digital converter have different resolutions.

In the foregoing analog-to-digital converter, the secondary circuits of the group have different amplification ratios.

For the aforementioned analog-to-digital converter, each stage circuit of the secondary circuit of the group includes: a sub-analog-to-digital converter, which performs preliminary quantization on the input signal of the stage circuit; a sub-digital-to-analog converter, which The output of the converter is converted into a corresponding analog signal; a sample-and-hold amplifier is used to sample and hold the input signal of the stage circuit; an analog subtractor subtracts the sampled input signal from the analog signal to generate a residual value signal; and a second amplifier for amplifying the residual signal.

The aforementioned analog-to-digital converter further includes a front-end sample-and-hold amplifier for providing the input signal to the set of secondary circuits.

The aforementioned analog-to-digital converter further includes a digital correction circuit for correcting and integrating the output of the set of secondary circuits.

The aforementioned analog-to-digital converter further includes a delay element connected between the output of the set of secondary circuits and the digital correction circuit for synchronizing the output of the set of secondary circuits.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. According to the present invention, a pipelined analog-to-digital converter with adjustable front and rear resolutions and a shared operational amplifier includes: multiple sets of circuits connected in series, and each set of circuits in the multiple sets of circuits includes a series-connected two-stage circuit, wherein the front-stage circuit of each group of circuits resolves fewer bits than the subsequent-stage circuit of the same group; and a plurality of operational amplifiers, each of which is shared by a group of circuits, wherein the second-stage circuits of the same group The operations are staggered so that when one stage of the group is sampling, the other stage is amplifying, and the second stage does not use the operational amplifier at the same time.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned pipelined analog-to-digital converter with adjustable front and rear stage resolutions and shared operational amplifiers, each stage of the secondary circuit in this group includes: a sub-analog-to-digital converter for preliminary quantization of the input signal of the stage of the circuit ; A sub-DAC, which converts the output of the sub-ADC into a corresponding analog signal; a sample-and-hold amplifier, which is used to sample and hold the input signal of the stage circuit; an analog subtractor, which converts the sampled The analog signal is subtracted from the input signal to generate a residual signal; and an amplifier is used to amplify the residual signal.

The aforesaid pipelined analog-to-digital converter with adjustable front and back stage resolution sharing operational amplifiers is characterized in that it further includes a front-end sample-and-hold amplifier for providing the input signal to the first group of circuits, and the front-end sample-and-hold amplifier and The first group of circuits shares an amplifier.

The purpose of the present invention and the solution to its technical problem are realized by adopting the following technical solutions in addition. According to the present invention, a circular analog-to-digital converter sharing an operational amplifier with adjustable front and rear resolutions includes: a set of series-connected secondary circuits, and the front-stage circuit of the group of secondary circuits has a higher resolution than the rear-stage circuit. The number of bits is less; an operational amplifier is shared by the secondary circuit, and the operations of the secondary circuits are staggered from each other, so that when one of the primary circuits is sampling, the other stage is amplifying, and the secondary circuits are amplified. The stage circuit does not use the operational amplifier at the same time; and an analog multiplexer, when an analysis cycle ends, the output of the subsequent stage circuit is fed back to the front stage circuit through the analog multiplexer.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

As for the circular analog-to-digital converter with adjustable front and rear stage resolutions and shared operational amplifiers, each stage circuit of this group includes: a sub-analog-to-digital converter for preliminary quantization of the input signal of the stage circuit; a sub-digital converter An analog converter, which converts the output of the sub-analog-to-digital converter into a corresponding analog signal; a sample-and-hold amplifier, which is used to sample and hold the input signal of the stage circuit; an analog subtractor, which subtracts the sampled input signal The analog signal is used to generate a residual signal; and an amplifier is used to amplify the residual signal.

The aforesaid cyclic analog-to-digital converter with adjustable front-end resolution and shared operational amplifier further includes a front-end sample-and-hold amplifier for providing the input signal to the group of secondary circuits.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from above technical scheme, main technical content of the present invention is as follows:

In order to achieve the above object, according to an embodiment of the present invention, the pipelined analog-to-digital converter (pipelined ADC) of the shared operational amplifier with adjustable front and rear stage resolution (stage-resolution scalable) includes multiple sets of circuits connected in series, and each set of circuits Contains secondary circuits connected in series. The resolution bits (for example, 1.5 bits/level) of the front-stage circuits of each group of circuits are less than the resolution bits (for example, 2.5 bits/level) of the same group of subsequent-stage circuits. The secondary circuits of each group share an operational amplifier, and the operations of the secondary circuits are staggered from each other, so that when one of the primary circuits is sampling, the other stage is amplifying, so the secondary circuits will not Use an op amp at the same time. The pipelined ADC of this embodiment uses fewer operational amplifiers and consumes less power than conventional ADC architectures.

In addition, in order to achieve the above object, according to another embodiment of the present invention, the cyclic analog-to-digital converter (cyclic ADC) of the shared operational amplifier with adjustable stage-resolution scalable (stage-resolution scalable) comprises a set of series-connected secondary circuits , the resolution bits (for example, 1.5 bits/level) of the front-stage circuit are less than the resolution bits (for example, 2.5 bits/level) of the same group of subsequent-stage circuits. The operations of the two-stage circuits are mutually staggered, so that when one of the two-stage circuits is sampling, the other-stage circuit is amplifying, so the two-stage circuits do not use operational amplifiers at the same time. At the end of each analysis cycle, the output of the subsequent circuit is fed back to the previous circuit through the analog multiplexer. The operation speed of the cyclic ADC in this embodiment is faster than that of the conventional cyclic ADC architecture.

By virtue of the above technical solutions, the present invention is applicable to the shared operational amplifier technology with adjustable front and rear resolutions of pipelined or circular analog-to-digital converters and has at least the following advantages and beneficial effects:

The present invention relates to a pipelined or cyclic analog-to-digital converter (ADC). The analog-to-digital converter includes at least one set of series-connected secondary circuits, which have different resolution bits. The secondary circuits share an amplifier, and their operations are staggered from each other. This stage-resolution scalable shared operational amplifier technology can be applied to pipelined or looped analog-to-digital converters, thereby greatly reducing power consumption and increasing operating speed. The present invention has significant progress in technology, and has obvious positive effects, and is a novel, progressive and practical new design.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

Figure 1 is a schematic diagram showing a traditional pipelined ADC architecture.

FIG. 2 is a schematic diagram showing the circuit and operation of a product digital-to-analog converter (MDAC) with an offset correction mechanism.

FIG. 3 is a schematic diagram showing the circuit and operation of a product digital-to-analog converter (MDAC) without an offset correction mechanism.

FIG. 4 is a schematic diagram showing a dual-channel TDMA ADC.

FIG. 5 is a schematic diagram showing a pipelined ADC sharing an operational amplifier.

FIG. 6 shows a schematic diagram of a stage-resolution scalable shared operational amplifier applicable to a pipelined ADC according to an embodiment of the present invention.

7A to 7D are diagrams comparing the power consumption of the conventional pipelined ADC (FIG. 1), the conventional oversampling technique (FIG. 4), the conventional shared operational amplifier technique (FIG. 5) and the embodiment of the present invention (FIG. 6).

FIG. 8 is a schematic diagram showing another embodiment of a stage-resolution scalable shared operational amplifier applicable to a pipelined ADC.

FIG. 9 is a schematic diagram showing another embodiment of the present invention, which is suitable for a shared operational amplifier with stage-resolution scalable front and rear stages of a cyclic ADC.

1: Traditional pipelined ADC architecture 11: Front-end sample-and-hold amplifier

12: ADC circuit at all levels 120: Product DAC

121: sub-analog-to-digital converter (sub-ADC)

122: Sub-Digital-to-Analog Converter (sub-DAC)

123: Sample and hold (S/H) circuit 124: Analog subtractor

125: Amplifier 126: Residual value signal

13: Delay element 14: Digital correction circuit

4: Dual channel time division multiple access ADC architecture

40: Channel 41: Channel

42: Operational amplifier

5: Pipelined ADC with shared operational amplifier

52: Operational amplifier

6: Pipeline ADC of one of the embodiments of the present invention

61: ADC circuit at all levels 62: Amplifier

9: Cyclic ADC according to another embodiment of the present invention

91: First-level circuit 92: Second-level circuit

93: Multiplexer 94: Amplifier

95: Digital correction circuit C _s , C _f : capacitance

clk1, clk2: clock signal

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the following is an analysis of the front and rear stages suitable for pipelined or circular analog-to-digital converters proposed according to the present invention in conjunction with the accompanying drawings and preferred embodiments. The specific implementation, structure, features and efficacy of the adjustable-degree shared operational amplifier technology are described in detail below.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of the specific implementation mode, when the technical means and functions adopted by the present invention to achieve the predetermined purpose can be obtained a deeper and more specific understanding, but the accompanying drawings are only for reference and description, and are not used to explain the present invention be restricted.

FIG. 6 shows a stage-resolution scalable shared operational amplifier technology according to an embodiment of the present invention, which is applicable to a pipelined analog-to-digital converter (ADC) 6 . In this embodiment, each stage of the ADC 6 has a different resolution. Adjacent stages (such as stage 1 and stage 2 in the figure) share an amplifier 62 (such as an operational amplifier). The operations of the adjacent stage circuits are staggered (when one stage is sampling, the other stage is amplifying), therefore, two adjacent stage circuits will not use the amplifier 62 at the same time, thereby saving half of the power consumption. The components of each stage circuit 61 and their connection configurations are similar to the sub-analog-to-digital converter (sub-ADC), sub-digital-to-analog converter (sub-DAC), sample-and-hold (S/H) circuit and The analog subtracter, wherein the sub-DAC, the sample-and-hold amplifier and the analog subtracter together form a product digital-to-analog converter (MDAC). The ADC 6 shown in FIG. 6 can additionally add delay elements as shown in FIG. 1 , and can also additionally add a front-end sample-and-hold amplifier (SHA) as shown in FIG. 1 . The connection and operation of these constituent elements will not be described in detail.

In the embodiment of the present invention, the resolution bits of the previous stage (for example, stage 1) among adjacent secondary circuits are lower than those of the subsequent stage (for example, stage 2). Since the magnifications of the front and rear stages are different, the feedback factor of the MDAC will be different, which will cause the error of the subsequent stage circuit to increase. However, since the subsequent stage circuit can tolerate a larger error than the previous stage circuit, the error of the latter stage circuit will not affect the overall performance.

In an exemplary embodiment, the preceding stage circuit resolves 1.5 bits (that is, 1.5 bits/level) and the subsequent stage circuit resolves 2.5 bits (that is, 2.5 bits/level), therefore, the feedback coefficient of the preceding stage is 1/2 (C _f =C _s ) and the feedback coefficient of the subsequent stage is 1/4 (C _s =3×C _f ). Although this embodiment takes the parsing bits of 1.5/2.5 as an example, those familiar with this technical field can make other changes. The difference in the feedback coefficient will cause the following issues.

1. Different feedback errors

The feedback error (e) is inversely proportional to the product of the operational amplifier gain (A) and the feedback coefficient (β), that is

$\mathrm{<span\; class="notranslate">\; e</span>}<span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; A\&beta;</span>}}<span\; class="notranslate">\; .</span>$

Since the subsequent stage circuit has a smaller feedback coefficient, the latter stage circuit will experience a larger feedback error. As mentioned above, since the accuracy requirement of the downstream circuit of the pipelined ADC is lower than that of the previous circuit, the feedback error is tolerable.

2. Circuit stabilization time is different

In a feedback system, a smaller feedback coefficient will result in a smaller loop bandwidth or a longer settling time. In this embodiment, compared with the previous circuit, the subsequent circuit has a longer stabilization time and more stabilization errors. However, since the accuracy requirement of the downstream circuit of the pipelined ADC is lower than that of the preceding circuit, this stability error is tolerable.

3. The phase margin of the circuit is different

In the feedback system, different feedback coefficients will cause different phase boundaries, thus affecting the stability of the circuit. Systems with larger feedback coefficients are less stable and thus require larger phase boundaries to maintain their stability. In this embodiment, since there is only one bit difference between the resolutions of the front and rear circuits, the difference in the feedback coefficient is not large; it is not difficult to provide a sufficient phase boundary, so the stability of the circuit can be easily ensured.

In view of the above discussion, the present embodiment does not require much extra cost to overcome these issues. Compared with the traditional shared operational amplifier technique, the embodiment of the present invention can resolve more bits. In other words, for the same resolution bits, the embodiments of the present invention use fewer stages than the conventional shared operational amplifier technique. The power consumption of the embodiment of the present invention is equivalent to that of the conventional oversampling technique, but there is no channel mismatch problem.

Figures 7A to 7D compare the power consumption of the traditional pipelined ADC (Figure 1), the traditional oversampling technique (Figure 4), the traditional shared operational amplifier technique (Figure 5) and the embodiment of the present invention (Figure 6), and the comparison results are listed in Table 1.

For the traditional pipelined ADC shown in FIG. 7A, each stage uses an amplifier. Every time a circuit passes through, the resolution requirement is reduced by one bit, and the power consumption rate is also reduced by half. The total power consumption is the sum of the power consumption of the twelve stages of circuits. For the conventional oversampling technique shown in FIG. 7B, the power consumption is half that of FIG. 7A since the operation speed of each stage is doubled. For the conventional shared operational amplifier technique shown in FIG. 7C , only six shared amplifiers are needed, thus saving significant power consumption. For the embodiment of the present invention shown in FIG. 7D , each amplifier is shared by two adjacent stages to resolve three bits; in contrast, FIG. 7C can only resolve two bits. In this embodiment, only four amplifiers are required. According to Table 1, the power consumption of the conventional oversampling technique is the smallest, and that of the embodiment is next. However, traditional oversampling techniques require additional circuitry to compensate for channel mismatch, thus consuming more power and increasing the complexity of circuit design.

Table I

FIG. 8 is a schematic diagram showing another embodiment of a stage-resolution scalable shared operational amplifier applicable to a pipelined ADC. In this embodiment, a front-end sample-and-hold amplifier (SHA) is used to provide a high input bandwidth of the circuit. The operations of the front-end sample-and-hold amplifier (SHA) and the first-stage circuit are staggered and share one amplifier; while the second-stage and the third-stage circuit share another amplifier, and so on to other stage circuits.

FIG. 9 is a schematic diagram showing a stage-resolution scalable shared operational amplifier according to another embodiment of the present invention, which is suitable for a circular ADC 9 . In this embodiment, the first-level circuit parses part of the bits (eg, two bits). Next, the first stage 91 generates a residual signal and feeds it back to the second stage 92, which then parses other partial bits (eg, three bits). The residual signal generated by the second stage 92 is fed back to the first stage 91 via the multiplexer 93, thus completing a cycle. During this cycle of operation, an amplifier 94 is shared. The cyclic ADC 9 further includes a digital correction circuit 95 for correcting and integrating the analyzed bits, and finally outputs an N-bit digital code. Compared with FIG. 6, since the secondary circuit is reused in the cyclic ADC 9, the circuit area can be greatly saved, but the operation speed will be slower. Compared with the traditional cyclic ADC, the cyclic ADC 9 of this embodiment resolves more bits in each cycle, so its operation speed is faster than the traditional cyclic ADC.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but all the content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence still belong to the scope of the technical solution of the present invention.

Claims (14)

1. An analog-to-digital converter, characterized in that it comprises: At least one set of secondary circuits in series, wherein the secondary circuits have different resolution bits; and a first amplifier shared by the secondary circuits, wherein the operations of the secondary circuits are mutually staggered. 2. The analog-to-digital converter according to claim 1, characterized in that, when one of the secondary circuits of the group performs sampling, the other secondary circuit performs amplification, and the secondary circuit does not simultaneously use the amplifier. 3. analog-to-digital converter according to claim 1, is characterized in that, the bit unit that the preceding stage circuit of the secondary circuit of this group resolves is less than the subsequent stage circuit of the same group, the front and rear stage circuits of this analog-to-digital converter with different resolutions. 4. The analog-to-digital converter according to claim 3, wherein the secondary circuits of the group have different amplification ratios. 5. The analog-to-digital converter according to claim 1, wherein each stage circuit of the set of secondary circuits comprises: A sub-analog-to-digital converter for preliminary quantization of the input signal of the stage circuit; A sub-ADC, converting the output of the sub-ADC into a corresponding analog signal; A sample-and-hold amplifier for sampling and holding the input signal of the stage circuit; an analog subtractor that subtracts the analog signal from the sampled input signal to generate a residual signal; and A second amplifier is used to amplify the residual signal. 6. The analog-to-digital converter according to claim 5, further comprising a front-end sample-and-hold amplifier for providing the input signal to the set of secondary circuits. 7. The analog-to-digital converter according to claim 1, further comprising a digital correction circuit for correcting and integrating outputs of the set of secondary circuits. 8. The analog-to-digital converter according to claim 7, further comprising a delay element connected between the output of the set of secondary circuits and the digital correction circuit for synchronizing the set of secondary circuits output of the circuit. 9. A pipelined analog-to-digital converter of a shared operational amplifier with adjustable front and rear resolutions, characterized in that it comprises: Multiple sets of circuits in series, each set of circuits in the multiple sets of circuits includes a series of secondary circuits, wherein the preceding stage circuit of each set of circuits resolves fewer bits than the subsequent stage circuit of the same set; and A plurality of operational amplifiers, each of which is shared by a group of circuits, wherein the operations of the secondary circuits of the same group are staggered from each other, so that when one of the circuits of the group is sampling, the other circuit is To amplify, the secondary circuit does not use the op amp at the same time. 10. The pipelined analog-to-digital converter of the shared operational amplifier with adjustable front and rear resolutions according to claim 9, wherein each stage circuit of the group of secondary circuits comprises: A sub-analog-to-digital converter for preliminary quantization of the input signal of the stage circuit; A sub-ADC, converting the output of the sub-ADC into a corresponding analog signal; A sample-and-hold amplifier for sampling and holding the input signal of the stage circuit; an analog subtractor that subtracts the analog signal from the sampled input signal to generate a residual signal; and An amplifier is used to amplify the residual signal. 11. The pipelined analog-to-digital converter with adjustable front-rear stage resolution and shared operational amplifier according to claim 10, characterized in that it further comprises a front-end sample-and-hold amplifier for providing the input signal to the first group of circuits , the front-end sample-and-hold amplifier shares an amplifier with the first group of circuits. 12. A circular analog-to-digital converter of a shared operational amplifier with adjustable front and rear resolutions, characterized in that it comprises: A group of secondary circuits connected in series, the former circuit of this group of secondary circuits has fewer bits to resolve than the latter circuit; An operational amplifier shared by the secondary circuits, wherein the operations of the secondary circuits are staggered from each other, so that when one of the primary circuits is sampling, the other stage is amplifying, and the secondary circuits will not simultaneously using the operational amplifier; and An analog multiplexer, at the end of an analysis cycle, the output of the subsequent stage circuit is fed back to the previous stage circuit through the analog multiplexer. 13. The circular analog-to-digital converter of the shared operational amplifier with adjustable front and rear resolutions according to claim 12, wherein each stage circuit of the group comprises: A sub-analog-to-digital converter for preliminary quantization of the input signal of the stage circuit; A sub-ADC, converting the output of the sub-ADC into a corresponding analog signal; A sample-and-hold amplifier for sampling and holding the input signal of the stage circuit; an analog subtractor that subtracts the analog signal from the sampled input signal to generate a residual signal; and An amplifier is used to amplify the residual signal. 14. The circulating analog-to-digital converter with adjustable front and rear stage resolutions and shared operational amplifiers according to claim 13, characterized in that it further comprises a front-end sample-and-hold amplifier for providing the input signal to the group of secondary circuit.

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