CN101770981A - Zero drift compensation method of Hall magnetic sensor - Google Patents

Abstract

The method for compensating the zero point drift of the Hall magnetic sensor. At present, when the external magnetic field B=0 of the known Hall magnetic sensor, due to factors such as asymmetrical geometric position of the Hall electrode, poor ohmic contact of the electrode, uneven resistivity, and uneven temperature Make the Hall output voltage VH not equal to zero, resulting in a zero error VHO. In order to eliminate the zero error, an external compensation circuit is mainly used to compensate the zero drift. This method is not easy for the magnetic sensor to develop in the direction of miniaturization and intelligence. In the present invention, the resistance values of the four equivalent resistances of the channels of the MOSFET Hall Hall magnetic sensor manufactured by a CMOS process change with the external grid voltage. The invention is applied in the fields of medicine, automobile and the like.

Description

The Method of Compensating the Zero Drift of Hall Magnetic Sensor

Technical field:

The invention relates to a zero compensation method for the MOSFET Hall magnetic sensor by adjusting the equivalent resistance of the conduction channel of the MOSFET Hall magnetic sensor through a gate bias voltage.

Background technique:

At present, when the known Hall magnetic sensor is applied with a magnetic field B=0, the Hall output voltage VH is not equal to zero due to factors such as geometric asymmetry of the Hall electrode, poor ohmic contact of the electrode, uneven resistivity, and uneven temperature, resulting in zero Bit Error VHO. In order to eliminate the zero error, an external compensation circuit is mainly used to compensate the zero drift. This method is not easy for the magnetic sensor to develop in the direction of miniaturization and intelligence.

Invention content:

The purpose of the present invention is to provide a method for compensating the zero-point drift that overcomes the influence of external compensation circuits and other methods on the performance of MOSFET Hall magnetic sensors.

Above-mentioned purpose realizes by following technical scheme:

The method of compensating the zero-point drift of the Hall magnetic sensor is to manufacture the MOSFET Hall Hall magnetic sensor through the CMOS process. The resistance values of the four equivalent resistances of the channel of the Hall magnetic sensor change with the external gate voltage.

The method for compensating the zero-point drift of the Hall magnetic sensor: the CMOS process includes flushing, first oxidation, first photolithography, second oxidation, P-type doping, third oxidation, two- Five photolithography;

The flushing is to boil the N-type double-sided polished high-resistance (ρ>100Ω·cm) single crystal silicon wafer with a thickness of 450 μm in concentrated sulfuric acid until white smoke is emitted, rinse it with a large amount of deionized water after cooling, and then use electronic Cleaning solution DZ-1 and DZ-2 are washed twice respectively, rinsed with a large amount of deionized water, and dried in a spin dryer;

The first oxidation is to put the cleaned single crystal silicon wafer into a high-temperature oxidation furnace, and use a thermal oxidation process to grow a _SiO2 layer. The temperature of the oxidation furnace is 1180 ° C, and the thickness of the grown _SiO2 layer is 650 nm;

The first photolithography is to use a photolithography machine to carry out photolithography. The photolithography process is glue coating, pre-baking, exposure, development, film hardening, corrosion and degumming, and the active area window is photoetched. The silicon wafer cleaning method cleans the silicon wafer;

The second oxidation is to grow a _SiO2 layer by thermal oxidation process on the silicon wafer after cleaning, and re-grow a _SiO2 layer with a thickness of 50nm in the active area window of a photolithography;

P-type doping is made by implanting B ions with an ion implanter, the implantation energy is 40KeV, and the implantation dose is 6.0×10 ¹³ to obtain P-type doping; the SiO ₂ layer with a thickness of 50nm is removed by wet etching;

The third oxidation is to clean the silicon wafer by the above-mentioned cleaning method, perform three oxidations, and grow a grid oxide layer with a thickness of 50nm; use LPCVD to grow a polysilicon gate and perform polysilicon gate phosphorus diffusion;

The second photolithography is to use the above photolithography method to perform photolithography, etch the polysilicon, form the polysilicon gate and perform boron implantation, and realize the MOSFET source, drain and two through the polysilicon gate self-alignment technology Hall output terminal impurity doping;

The third photolithography is carried out by the above photolithography method, and the substrate impurity doped window is photoetched;

Phosphorus is implanted with an ion implanter, and N ⁺ is formed on the substrate; the polysilicon gate is oxidized by the H ₂ +O ₂ synthesis oxidation method, and a SiO ₂ layer is grown with a thickness of 200nm;

The fourth photolithography is to etch the source, drain, gate, substrate, and Hall output contact holes of the MOSFET Hall magnetic sensor; the aluminum electrode is magnetron sputtered on the front side of the silicon wafer, and the thickness of the aluminum electrode is 1 μm;

The fifth photolithography is to reverse-etch aluminum to form the source, drain, substrate, gate and two Hall output terminals respectively; put the silicon wafer into a high-temperature vacuum furnace and carry out alloying at 400°C. chemical treatment for 30 minutes to form a good ohmic contact between the source, drain, substrate, and Hall output terminals.

The method for compensating the zero drift of the Hall magnetic sensor can use a P-type substrate silicon chip to make an n-MOSFET Hall magnetic sensor, or use an N-type substrate silicon chip to make a p-MOSFET Hall magnetic sensor.

In the method for compensating the zero-point drift of the Hall magnetic sensor, the two ohmic-contact Hall output terminals have a concave structure on the polysilicon gate and are not located in the center of the channel.

This technical solution has the following beneficial effects:

1. The present invention realizes that when the applied magnetic field is equal to zero, the output voltage of the channel equivalent circuit bridge of the MOSFET Hall magnetic sensor channel with the external grid voltage changes, and under a certain grid voltage, the zero drift compensation of the MOSFET Hall magnetic sensor is realized.

2. The purpose of the present invention is to overcome the impact of methods such as external compensation circuits on the performance of MOSFET Hall magnetic sensors.

3. The present invention adjusts the conductive channel equivalent resistance to make the bridge arms symmetrical by adopting the MOSFET Hall magnetic sensor gate bias voltage V _GS , so that when the applied magnetic field B=0, the magnetic sensor unequal potential V _HO is close to zero Output to realize intelligent zero compensation of MOSFET Hall magnetic sensor.

Description of drawings:

Accompanying drawing 1 is the lithography layout of MOSFET Hall magnetic sensor mask among the present invention. The figure shows the source (S), drain (D), gate (G), substrate (B) and Hall output terminals VH1 and VH2 of the MOSFET Hall magnetic sensor respectively.

Accompanying drawing 2 is the equivalent circuit diagram of MOSFET Hall magnetic sensor channel among the present invention.

The specific embodiment of the present invention:

Example 1:

The method of compensating the zero-point drift of the Hall magnetic sensor is to manufacture the MOSFET Hall Hall magnetic sensor through the CMOS process. The resistance values of the four equivalent resistances of the channel of the Hall magnetic sensor change with the external gate voltage.

The CMOS process includes flushing, first oxidation, first photolithography, second oxidation, P-type doping, third oxidation, and 215 photolithography.

Referring to Figure 1, N-type double-sided polished high-resistance (ρ>100Ω·cm) monocrystalline silicon wafers with a thickness of 450 μm are boiled with concentrated sulfuric acid until white smoke is emitted, rinsed with a large amount of deionized water after cooling, and then cleaned with Liquids DZ-1 and DZ-2 were washed twice respectively, rinsed with a large amount of deionized water, and dried in a spin dryer;

Put the cleaned monocrystalline silicon wafer into a high-temperature oxidation furnace for primary oxidation, and use a thermal oxidation process to grow a SiO2 layer. The temperature of the oxidation furnace is 1180°C, and the thickness of the grown SiO2 layer is 650nm;

Use a photolithography machine to perform one-time photolithography. The photolithography process is glue coating, pre-baking, exposure, development, film hardening, corrosion and degumming. Photolithography is used to form the active area window, and the silicon wafer is cleaned by the above-mentioned silicon wafer cleaning method;

The cleaned silicon wafer is subjected to secondary oxidation, and the thermal oxidation process is used to grow the SiO2 layer, and the SiO2 layer with a thickness of 50nm is re-grown in the active area window of the primary photolithography to improve the uniformity of ion implantation;

Use an ion implanter to implant B ions, the implantation energy is 40KeV, and the implantation dose is 6.0×1013 to obtain P-type doping;

The SiO2 layer with a thickness of 50nm is removed by wet etching;

The silicon wafer is cleaned by the above cleaning method, and then oxidized three times to grow a gate oxide layer with a thickness of 50nm;

Using LPCVD to grow the polysilicon gate and perform polysilicon gate phosphorus diffusion to reduce the polysilicon gate resistivity;

The above photolithography method is used for secondary photolithography, polysilicon is etched, polysilicon gate is formed and boron is implanted, and the source, drain and two Hall output terminals of MOSFET are impurity doped through self-alignment technology of polysilicon gate ;

Perform photolithography three times by the above photolithography method, and photoetch out the substrate impurity-doped window;

Phosphorus is implanted with an ion implanter, and N+ is formed on the substrate; the polysilicon gate is oxidized by the H2+O2 synthesis oxidation method, and the SiO2 layer is grown with a thickness of 200nm to realize multi-polysilicon gate protection;

Through four photolithography, etch the MOSFET Hall magnetic sensor source, drain, gate, substrate and Hall output contact holes;

Magnetron sputtering aluminum electrodes on the front of the silicon wafer, the thickness of the aluminum electrodes is 1 μm;

Five times of photolithography, anti-etch aluminum, respectively form the source, drain, substrate, gate and two Hall output electrodes;

Put the silicon wafer into a high-temperature vacuum furnace, and carry out alloying treatment at 400°C for 30 minutes, so that the source, drain, substrate, Hall output terminal, etc. form a good ohmic contact.

Use P-type substrate silicon wafers to make n-MOSFET Hall magnetic sensors, or use N-type substrate silicon wafers to make p-MOSFET Hall magnetic sensors.

The Hall output ends of the two ohmic contacts have a concave structure on the polysilicon gate and are not located in the center of the channel.

working principle:

Between the MOSFET Hall magnetic sensor source (S), drain (D) and Hall output terminals VH1, VH2, the channel is equivalent to four resistors R1, R2, R3 and R4. R1, R2, R3 and R4 change with the external grid voltage, resulting in the adjustment of the output voltage of the bridge.

Claims (6)

1. A method for compensating the zero-point drift of a Hall magnetic sensor is characterized in that: the four equivalent resistance resistances of the channel of the MOSFET Hall Hall magnetic sensor made by a CMOS process vary with the grid voltage applied. 2. The method for compensating the zero drift of the Hall magnetic sensor according to claim 1, characterized in that: the CMOS process includes flushing, first oxidation, first photolithography, second oxidation, fabrication P-type doping, third oxidation, two-fifth photolithography. 3. The method for compensating the zero-point drift of the Hall magnetic sensor according to claim 1, characterized in that: the flushing is a N-type double-sided polished high-resistance p>100Ω·cm single crystal silicon wafer with a thickness of 450 μm Boil with concentrated sulfuric acid until white smoke comes out, rinse with a large amount of deionized water after cooling, and then use electronic cleaning fluid DZ-1 and DZ-2 to wash twice respectively, rinse with a large amount of deionized water, and put it in a spin dryer. Dry; The first oxidation is to put the cleaned single crystal silicon wafer into a high-temperature oxidation furnace, and use a thermal oxidation process to grow a _SiO2 layer. The temperature of the oxidation furnace is 1180 ° C, and the thickness of the grown _SiO2 layer is 650 nm; The first photolithography is to use a photolithography machine to carry out photolithography. The photolithography process is glue coating, pre-baking, exposure, development, film hardening, corrosion and degumming, and the active area window is photoetched. The silicon wafer cleaning method cleans the silicon wafer; The second oxidation is to grow a _SiO2 layer by thermal oxidation process on the silicon wafer after cleaning, and re-grow a _SiO2 layer with a thickness of 50nm in the active area window of a photolithography; P-type doping is made by implanting B ions with an ion implanter, the implantation energy is 40KeV, and the implantation dose is 6.0×10 ¹³ to obtain P-type doping; the SiO ₂ layer with a thickness of 50nm is removed by wet etching; The third oxidation is to clean the silicon wafer by the above-mentioned cleaning method, perform three oxidations, and grow a grid oxide layer with a thickness of 50nm; use LPCVD to grow a polysilicon gate and perform polysilicon gate phosphorus diffusion; The second photolithography is to use the above photolithography method to perform photolithography, etch the polysilicon, form the polysilicon gate and perform boron implantation, and realize the MOSFET source, drain and two through the polysilicon gate self-alignment technology Hall output terminal impurity doping; The third photolithography is carried out by the above photolithography method, and the substrate impurity doped window is photoetched; Phosphorus is implanted with an ion implanter, and N ⁺ is formed on the substrate; the polysilicon gate is oxidized by the H ₂ +O ₂ synthesis oxidation method, and a SiO ₂ layer is grown with a thickness of 200nm; The fourth photolithography is to etch the source, drain, gate, substrate, and Hall output contact holes of the MOSFET Hall magnetic sensor; the aluminum electrode is magnetron sputtered on the front side of the silicon wafer, and the thickness of the aluminum electrode is 1 μm; The fifth photolithography is to reverse-etch aluminum to form the source, drain, substrate, gate and two Hall output terminals respectively; put the silicon wafer into a high-temperature vacuum furnace and carry out alloying at 400°C. chemical treatment for 30 minutes to form a good ohmic contact between the source, drain, substrate, and Hall output terminals. 4. The method for compensating the zero-point drift of the Hall magnetic sensor according to claim 1 or 2 is characterized in that: the n-MOSFET Hall magnetic sensor is made by using a P-type substrate silicon chip, or it is made by using an N-type substrate silicon chip p-MOSFET Hall magnetic sensor. 5. The method for compensating the zero-point drift of the Hall magnetic sensor according to claim 1 or 2, wherein the Hall output terminals of the two ohmic contacts have a concave structure on the polysilicon gate, and are not located in the center of the channel . 6. The method for compensating the zero point drift of the Hall magnetic sensor according to claim 4, characterized in that: the two ohmic-contact Hall output terminals have a concave structure on the polysilicon gate and are not located in the center of the channel.

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