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CN101807579A - Charge-captured non-volatilization semiconductor memory and manufacturing method thereof - Google Patents

Charge-captured non-volatilization semiconductor memory and manufacturing method thereof Download PDF

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CN101807579A
CN101807579A CN201010125663A CN201010125663A CN101807579A CN 101807579 A CN101807579 A CN 101807579A CN 201010125663 A CN201010125663 A CN 201010125663A CN 201010125663 A CN201010125663 A CN 201010125663A CN 101807579 A CN101807579 A CN 101807579A
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charge
semiconductor memory
metal
semiconductor substrate
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吴东平
张世理
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Fudan University
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Fudan University
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Abstract

The invention provides a charge-captured non-volatilization semiconductor memory and a manufacturing method thereof. The charge-captured non-volatilization semiconductor memory comprises a semiconductor substrate, a source electrode region, a drain electrode region as well as a tunnel insulating layer, a charge capturing layer, an obstruction insulating layer and a grid electrode which are sequentially formed on the semiconductor substrate. The drain electrode region and the source electrode region respectively comprise a mixed semiconductor junction, and the mixed semiconductor junctions comprise metal semiconductor junctions and P-N junctions. The charge-captured non-volatilization semiconductor memory has the advantages of low programming voltage, high programming speed, lower power consumption and higher reliability.

Description

Charge-captured non-volatilization semiconductor memory and manufacture method thereof
Technical field
The present invention relates to a kind of nonvolatile memory, relate in particular to a kind of charge-captured non-volatilization semiconductor memory and preparation method thereof.
Background technology
Nonvolatile memory (Non-volatile Memory) has in fields such as mobile communication, data terminal, multimedia, consumer electronics and national defence electronics widely and uses owing to having low-power consumption, small size, high density, can repeating characteristics such as erasable.
Nonvolatile memory mainly comprises floating boom (Floating Gate) non-volatile semiconductor memory and electric charge capture (Charge Trapping) non-volatile semiconductor memory.Non-volatile semiconductor memory with floating gate is to utilize polysilicon to form floating boom, and charge storage is in floating boom, if therefore have any defective in the described polysilicon, then charge retention time will significantly reduce.On the contrary, charge-captured non-volatilization semiconductor memory is to use nitride layer to replace described polysilicon, and charge storage is in nitride layer, and is therefore relatively low to the sensitiveness of defective.In addition, compared to non-volatile semiconductor memory with floating gate, charge-captured non-volatilization semiconductor memory has better can miniature property.In addition, charge-captured non-volatilization semiconductor memory also has discrete storage medium, thin tunnel oxide, good data retention performance and fully and advantages such as microelectronic technique compatibility is arranged.Therefore, charge-captured non-volatilization semiconductor memory is considered to will replace non-volatile semiconductor memory with floating gate gradually below 30 nanometers at present.
Generally speaking, the programming of charge-captured non-volatilization semiconductor memory and scrub techniques derive from channel hot electron emission (Channel Hot-Election Injection) and raceway groove hot hole emission (Channel Hot-HoleInjection).The programming of charge-captured non-volatilization semiconductor memory (Program) is to finish near being transmitted in drain terminal by traditional channel hot electron, wipes (Erase) and finishes near then being transmitted in drain terminal by the raceway groove hot hole.At present, the source electrode of charge-captured non-volatilization semiconductor memory and drain electrode are all the P-N junction structure.
Yet along with size of devices is more and more littler, the channel length of described charge-captured non-volatilization semiconductor memory is also corresponding constantly to be shortened.Inject in order to produce sufficient drain terminal hot hole, source electrode and drain electrode are all this feature of P-N junction structure and cause program voltage very difficult reduced, and the hot electron injection efficiency is low, and program speed is slow, and power consumption is bigger.
Summary of the invention
At the problem that described charge-captured non-volatilization semiconductor memory exists, be necessary to provide that a kind of program voltage is low, program speed fast, power consumption is low and the higher charge-captured non-volatilization semiconductor memory of reliability.
Simultaneously, also be necessary to provide a kind of described non-volatile semiconductor memory preparation method.
A kind of charge-captured non-volatilization semiconductor memory, it comprises Semiconductor substrate, source region, drain region, is formed on tunnel insulation layer, electric charge capture layer, barrier insulating layer and gate electrode on the described Semiconductor substrate successively.Described drain region and source region include the semiconductor junction of mixing, and the semiconductor junction of described mixing comprises metal semiconductor junction and P-N knot.
Preferably, the metal of the metal semiconductor junction of described source region is a metal silicide, described metal silicide be in cobalt silicide, nickle silicide, titanium silicide, tungsten silicide, the platinum silicide any one.
Preferably, described Semiconductor substrate has described drain region and source region, and described P-N knot is to contact formation respectively with described Semiconductor substrate after the part of corresponding drain electrode of described Semiconductor substrate and source region is mixed.
Preferably, described charge-captured non-volatilization semiconductor memory further comprises the first metal layer that is formed on the described gate electrode, and described the first metal layer is metal tungsten layer or tungsten silicide layer.
Preferably, described charge-captured non-volatilization semiconductor memory further comprises the hard mask layer that is formed on the described the first metal layer.
Preferably, described tunnel insulation layer is formed on the zone except that described source region and described drain region on the described Semiconductor substrate, and described electric charge capture layer, barrier insulating layer, gate electrode, the first metal layer and hard mask layer are formed on the described tunnel insulation layer successively.
Preferably, described charge-captured non-volatilization semiconductor memory further comprises side wall, the space of corresponding described drain region and described source region forms first opening and second opening respectively on the described Semiconductor substrate, described side wall is respectively formed in described first, second opening, and lays respectively at the side of described tunnel insulation layer to hard mask layer.
A kind of manufacture method of charge-captured non-volatilization semiconductor memory, it comprises the steps: to provide Semiconductor substrate, forms tunnel insulation layer, electric charge capture layer, barrier insulating layer, gate electrode, the first metal layer and hard mask layer on described Semiconductor substrate successively; The described hard mask layer of etching, described the first metal layer, described gate electrode, described barrier insulating layer, described electric charge capture layer and described tunnel insulation layer successively, formation is corresponding to first opening of drain region and corresponding to second opening of source region, and described first, second opening all exposes described Semiconductor substrate; Form described first dielectric layer of first dielectric layer and etching and keep described first opening and first dielectric layer of the second opening madial wall; In described Semiconductor substrate, inject ion, make described drain region and described source region all form the P-N knot; Remove remaining described first dielectric layer and deposit second dielectric layer and described second dielectric layer formation of etching side wall, described side wall lays respectively in described first, second opening, and is positioned at the both sides of described tunnel insulation layer to hard mask layer; And forming second metal level, described second metal level and the reaction of described Semiconductor substrate make described drain region and described source region form the corresponding metal semiconductor junction.
Preferably, described second metal level is any one or its mixture in titanium layer, cobalt layer, nickel dam, the platinum layer.
Preferably, the thickness of described second dielectric layer is less than the thickness of described first dielectric layer, and the thickness of described first dielectric layer is less than the width of described first opening and described second opening in half less.
Preferably, described first dielectric layer is silicon dioxide layer, silicon nitride layer or both mixed layers.
Preferably, utilize annealing process that Semiconductor substrate in described second metal level and described first opening and second opening is reacted and form metal silicide.
Preferably, the contact of the Semiconductor substrate of the source region that drain region that described metal silicide is corresponding with described first opening and described second opening are corresponding forms metal semiconductor junction, and the Semiconductor substrate contact formation ohmic contact of the corresponding source region of its drain region corresponding with described first opening and described second opening.
Preferably, described manufacture method further comprise removal not with second metal level of described Semiconductor substrate reaction.
The drain region of the charge-captured non-volatilization semiconductor memory of manufacture method manufacturing of the present invention and the semiconductor junction of source region comprise the semiconductor junction of mixing respectively, and the semiconductor junction of described mixing comprises P-N knot and schottky junction.Any one or its mixture and Semiconductor substrate form metal silicide in Titanium, cobalt, nickel, the platinum.Described metal silicide portion contacts with described Semiconductor substrate and forms schottky junction, and it is part and the Semiconductor substrate formation ohmic contact of mixing in addition.Described schottky junction needs lower electronic barrier height, could the more effective source region hot electron injection programming pattern of finishing.When using described charge-captured non-volatilization semiconductor memory, only need under lower grid voltage and lower drain voltage, just can produce the particular thermal electronics in the source region, hot electron injection efficiency height, program voltage is low, program speed is fast and low in energy consumption.In addition, the source electrode of described charge-captured non-volatilization semiconductor memory, drain region comprise the semiconductor structure of mixing, can reduce the backward diode leakage current of drain electrode and source electrode, the device reliability height.
Description of drawings
Fig. 1 is the schematic cross-section of charge-captured non-volatilization semiconductor memory of the present invention.
Fig. 2 is preparation method's flow chart of charge-captured non-volatilization semiconductor memory one better embodiment shown in Figure 1.
Fig. 3 to Figure 13 is the schematic cross-section of each key step of the manufacture method of charge-captured non-volatilization semiconductor memory shown in Figure 1.
Embodiment
See also Fig. 1, Fig. 1 is the schematic cross-section of charge-captured non-volatilization semiconductor memory of the present invention.Described charge-captured non-volatilization semiconductor memory 10 comprises Semiconductor substrate 11, tunnel insulation layer 12, electric charge capture layer 13, barrier insulating layer 14, gate electrode 15, the first metal layer 16, hard mask layer 17 and side wall 18.Described Semiconductor substrate 11 surfaces have drain region 110 and source region 111.Described tunnel insulation layer 12, electric charge capture layer 13, barrier insulating layer 14, gate electrode 15, the first metal layer 16 and hard mask layer 17 are formed on the zone except that described drain region 110 and described source region 111 on the described Semiconductor substrate 11 successively.
The space of corresponding described drain region 110 and described source region 111 forms first opening 112 and second opening 113 respectively on the described Semiconductor substrate 11.Described side wall 18 is formed in described first, second opening 112,113, and lays respectively at the side of described tunnel insulation layer 12 to hard mask layer 17.Described drain region 110 comprises a contact hole (indicating), is filled with metal and and bit line (Bitline, figure does not show) connection in it.Described gate electrode 15 and described the first metal layer 16 form word line (Wordline, figure does not show) together.
See also Fig. 2 to Figure 13, Fig. 2 is the flow chart of manufacture method one better embodiment of described charge-captured non-volatilization semiconductor memory 10.Fig. 3 to Figure 13 is the schematic cross-section of each key step of the manufacture method of charge-captured non-volatilization semiconductor memory 10 shown in Figure 1.The manufacture method of described charge-captured non-volatilization semiconductor memory 10 comprises the steps:
Step S1 sees also Fig. 3, and Semiconductor substrate 11 is provided, and forms tunnel insulation layer 12, electric charge capture layer 13, barrier insulating layer 14 and gate electrode 15 on described Semiconductor substrate 11 in regular turn.The structure of described sandwich construction from described Semiconductor substrate 11 to described gate electrode 15 is polycrystalline silicon-oxide-nitride--oxide-polysilicon semiconductor (Silicon-Oxide-Nitride-Oxide-Silicon, SONOS) structure (not indicating).Described Semiconductor substrate 11 can be the P type semiconductor substrate.Described tunnel insulation layer 12 and barrier insulating layer 14 can adopt silicon dioxide (SiO2) to form.Described electric charge capture layer 13 can adopt silicon nitride (Si3N4) to form.Described gate electrode 15 can be polysilicon layer.
Described tunnel insulation layer 12 can form by wet oxidation or free-radical oxidation method.Described electric charge capture layer 13 and barrier insulating layer 14 can be implemented rapid thermal annealing (RTA) then by atomic layer deposition method (ALD), plasma enhancing ALD method (PE-ALD) or chemical vapour deposition technique (CVD) and form.
Step S2 sees also Fig. 4, forms the first metal layer 16 and hard mask layer 17 on the surface of described gate electrode 15 successively.Described the first metal layer 16 can be metal tungsten layer or metal silication tungsten layer.Described hard mask layer 17 can be silicon dioxide layer or silicon oxide layer.
Step S3, described hard mask layer 17 is carried out photoetching, afterwards described hard mask layer 17 to stacked each layer of described tunnel insulation layer 12 carried out etching till described Semiconductor substrate 11 comes out, thereby form first opening 112 shown in Figure 5 and second opening 113.The width of described first opening 112 is consistent with the width of described second opening 113.
Step S4 sees also Fig. 6, and at Semiconductor substrate 11 surface depositions first dielectric layer 19 of described mask layer 17 and exposure, described first dielectric layer 19 is silicon dioxide layer, silicon nitride layer or both mixed layers.The thickness of described first dielectric layer 19 is less than half of described first opening, 112 width.
Step S5, see also Fig. 7, utilize described first dielectric layer 19 of anisotropic dry etch, first dielectric layer 19 that covers on described hard mask layer 17, described first opening 112 and described second opening, the 113 pairing Semiconductor substrate 11 is etched away, keep first dielectric layer 19 of described first opening, 112 madial walls and first dielectric layer 19 of described second opening, 113 madial walls.
Step S6, see also Fig. 8,11 inject high dose N type foreign ion on the Semiconductor substrate with described hard mask layer 17 and first dielectric layer 19, and adopting annealing process to form the P-N knot of drain electrode and source electrode respectively in the source region 111 of the drain region 110 of described first opening, 112 correspondences and second opening, 113 correspondences, the border span that described P-N ties is less than the width of first, second opening 112,113 of correspondence.Described P-N knot is contacted respectively by described higher-doped Semiconductor substrate 11 and more low-doped Semiconductor substrate 11 and forms.Described N type impurity can be phosphorus (P), arsenic (As) etc.
Step S7 sees also Fig. 9, utilizes anisotropic dry etch to fall remaining first dielectric layer 19.
Step S8 sees also Figure 10, deposition second dielectric layer 21 on Semiconductor substrate shown in Figure 9 11 and hard mask layer 17.Described second dielectric layer 21 can be silicon dioxide layer, silicon nitride layer or both mixed layers.The thickness of described second dielectric layer 21 is less than the thickness of described first dielectric layer 19.
Step S9, utilize anisotropic dry etch to fall second dielectric layer 21 on hard mask layer 17 surfaces and part second dielectric layer 21 on described Semiconductor substrate 11 surfaces, keep second dielectric layer of the madial wall of described first, second opening 112,113, thereby form side wall shown in Figure 11 18.
Step S10, see also Figure 12, deposition second metal level 22 and utilizes annealing process on Semiconductor substrate shown in Figure 11 11 and hard mask layer 17, described second metal level 22 and two openings 112,113 interior Semiconductor substrate 11 are reacted and forms metal silicide.Described second metal level 22 can be titanium layer, cobalt layer, nickel dam, platinum layer or its mixed layer.The more low-doped Semiconductor substrate 11 of the drain region 110 that described metal silicide is corresponding with first opening 112 forms metal semiconductor junctions (schottky junction), promptly is positioned at the both sides of the P-N boundary of described drain region 110.Simultaneously, more low-doped Semiconductor substrate 11 contacts of the source region 111 that described metal silicide is corresponding with described second opening 113 form metal semiconductor junctions (schottky junction), promptly are positioned at the P-N knot both sides of described source region 111, as shown in figure 13.
Step S 11, please consult Figure 13 once more, utilize wet etching, remove unreacted second metal level 22, and deposit the 3rd dielectric layer (figure do not show), form contact hole (figure does not show) in described first opening 112 zones, in described contact hole, fill metal (figure does not show), and be connected with the bit line (Bitline) of follow-up formation.At last, described gate electrode 15 and the described the first metal layer 16 common word lines (figure does not show) that form, just formed the charge-captured non-volatilization semiconductor memory 10 that described drain region 110 and source region 111 comprise the semiconductor junction of mixing respectively, wherein, the semiconductor junction of described mixing comprises schottky junction and P-N knot.In addition, because described the first metal layer 16 resistivity are lower than described gate electrode 15, so described word line is mainly formed by described gate electrode 15.
In the present embodiment, Semiconductor substrate 11 zones of described first opening, 112 correspondences are described drain regions 110, and described second opening, 113 pairing Semiconductor substrate 11 zones are described source regions 111.Be understandable that the position of described drain region 110 and described source region 111 can exchange.
In addition, the width of described first opening 112 is consistent with the width of described second opening 113, be understandable that, the width of described first opening 112 and described second opening 113 can be different, as long as the thickness that guarantees described first dielectric layer 19 is less than in half of the A/F of described first opening 112, second opening 113 less one.
The drain region 110 of the charge-captured non-volatilization semiconductor memory 10 of manufacture method manufacturing of the present invention and the semiconductor junction of source region 111 comprise the semiconductor junction of mixing respectively, and the semiconductor junction of described mixing comprises P-N knot and schottky junction.Any one or its mixture and Semiconductor substrate 11 form metal silicides in Titanium, cobalt, nickel, the platinum.The part of described metal silicide contacts with described Semiconductor substrate 11 and forms schottky junction, and it is the part Semiconductor substrate 11 formation ohmic contact higher with doping content in addition.Described schottky junction needs lower electronic barrier height, could the more effective source region hot electron injection programming pattern of finishing.When using described charge-captured non-volatilization semiconductor memory 10, only need just can produce the particular thermal electronics in the source region under lower grid voltage and lower drain voltage, hot electron injection efficiency height, program voltage is low, program speed is fast and low in energy consumption.
In addition, the source electrode of described charge-captured non-volatilization semiconductor memory 10, drain electrode include the semiconductor junction of mixing, the semiconductor junction of described mixing comprises schottky junction and P-N knot, can reduce the backward diode leakage current of described drain electrode and source electrode, the device reliability height.
Only be preferred case study on implementation of the present invention below, be not limited to the present invention, for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (14)

1.一种电荷俘获非挥发半导体存储器，其包括半导体衬底、源极区域、漏极区域、依次形成在所述半导体衬底上的隧道绝缘层、电荷俘获层、阻挡绝缘层和栅电极，其特征在于：所述漏极区域及源极区域均包括混合的半导体结，所述混合的半导体结包括金属半导体结和P-N结。1. A charge trapping non-volatile semiconductor memory, comprising a semiconductor substrate, a source region, a drain region, a tunnel insulating layer, a charge trapping layer, a blocking insulating layer and a gate electrode formed sequentially on the semiconductor substrate, It is characterized in that: both the drain region and the source region include mixed semiconductor junctions, and the mixed semiconductor junctions include metal-semiconductor junctions and P-N junctions. 2.根据权利要求1所述的电荷俘获非挥发半导体存储器，其特征在于：所述源极区域的金属半导体结的金属为金属硅化物，所述金属硅化物为硅化钴、硅化镍、硅化钛、硅化钨、硅化铂中任意一种。2. The charge-trapping non-volatile semiconductor memory according to claim 1, characterized in that: the metal of the metal-semiconductor junction in the source region is metal silicide, and the metal silicide is cobalt silicide, nickel silicide, titanium silicide , tungsten silicide, platinum silicide in any one. 3.根据权利要求1所述的电荷俘获非挥发半导体存储器，其特征在于：所述半导体衬底具有所述漏极区域及源极区域，所述P-N结是所述半导体衬底对应漏极及源极区域的部分掺杂之后与所述半导体衬底分别接触形成。3. The charge-trapping non-volatile semiconductor memory according to claim 1, characterized in that: the semiconductor substrate has the drain region and the source region, and the P-N junction is the corresponding drain and the source region of the semiconductor substrate Partial doping of the source region is then formed in contact with the semiconductor substrate respectively. 4.根据权利要求3所述的电荷俘获非挥发半导体存储器，其特征在于：所述电荷俘获非挥发半导体存储器进一步包括形成在所述栅电极上的第一金属层，所述第一金属层是金属钨层或者硅化钨层。4. The charge-trapping non-volatile semiconductor memory according to claim 3, wherein the charge-trapping non-volatile semiconductor memory further comprises a first metal layer formed on the gate electrode, and the first metal layer is Metal tungsten layer or tungsten silicide layer. 5.根据权利要求4所述的电荷俘获非挥发半导体存储器，其特征在于：所述电荷俘获非挥发半导体存储器进一步包括形成在所述第一金属层上的硬掩膜层。5. The charge-trapping non-volatile semiconductor memory according to claim 4, wherein the charge-trapping non-volatile semiconductor memory further comprises a hard mask layer formed on the first metal layer. 6.根据权利要求5所述的电荷俘获非挥发半导体存储器，其特征在于：所述隧道绝缘层形成在所述半导体衬底上除所述源极区域和所述漏极区域以外的区域，所述电荷俘获层、阻挡绝缘层、栅电极、第一金属层及硬掩膜层依次形成在所述隧道绝缘层上。6. The charge-trapping non-volatile semiconductor memory according to claim 5, wherein the tunnel insulating layer is formed on the semiconductor substrate except the source region and the drain region, so The charge trapping layer, blocking insulating layer, gate electrode, first metal layer and hard mask layer are sequentially formed on the tunnel insulating layer. 7.根据权利要求6所述的电荷俘获非挥发半导体存储器，其特征在于：所述电荷俘获非挥发半导体存储器进一步包括侧墙，所述半导体衬底上对应所述漏极区域和所述源极区域的空间分别形成第一开口及第二开口，所述侧墙分别形成在所述第一、第二开口内，并且分别位于所述隧道绝缘层至硬掩膜层的侧边。7. The charge-trapping non-volatile semiconductor memory according to claim 6, characterized in that: the charge-trapping non-volatile semiconductor memory further comprises spacers corresponding to the drain region and the source on the semiconductor substrate The spaces in the regions respectively form a first opening and a second opening, and the sidewalls are respectively formed in the first and second openings, and are respectively located on the sides from the tunnel insulating layer to the hard mask layer. 8.一种电荷俘获非挥发半导体存储器的制造方法，其包括如下步骤：8. A method for manufacturing a charge-trapping non-volatile semiconductor memory, comprising the steps of: 提供半导体衬底，在所述半导体衬底上依次形成隧道绝缘层、电荷俘获层、阻挡绝缘层、栅电极、第一金属层及硬掩膜层；A semiconductor substrate is provided, and a tunnel insulating layer, a charge trapping layer, a blocking insulating layer, a gate electrode, a first metal layer and a hard mask layer are sequentially formed on the semiconductor substrate; 依次刻蚀所述硬掩膜层、所述第一金属层、所述栅电极、所述阻挡绝缘层、所述电荷俘获层及所述隧道绝缘层，形成对应于漏极区域的第一开口及对应于源极区域的第二开口，所述第一、第二开口都暴露出所述半导体衬底；sequentially etching the hard mask layer, the first metal layer, the gate electrode, the blocking insulating layer, the charge trapping layer and the tunnel insulating layer to form a first opening corresponding to the drain region and a second opening corresponding to the source region, both of the first and second openings expose the semiconductor substrate; 形成第一介质层并刻蚀所述第一介质层并保留所述第一开口及第二开口内侧壁的第一介质层；forming a first dielectric layer, etching the first dielectric layer and retaining the first dielectric layer on the inner sidewall of the first opening and the second opening; 向所述半导体衬底中注入离子，使所述漏极区域和所述源极区域均形成P-N结；implanting ions into the semiconductor substrate, so that both the drain region and the source region form a P-N junction; 除去剩余的所述第一介质层并沉积第二介质层并刻蚀所述第二介质层形成侧墙，所述侧墙分别位于所述第一、第二开口内，并且位于所述隧道绝缘层至硬掩膜层的两侧；及removing the remaining first dielectric layer, depositing a second dielectric layer, and etching the second dielectric layer to form sidewalls, the sidewalls are respectively located in the first and second openings and located in the tunnel insulation layer to both sides of the hard mask layer; and 形成第二金属层，所述第二金属层与所述半导体衬底反应，使所述漏极区域及所述源极区域形成相应的金属半导体结。A second metal layer is formed, and the second metal layer reacts with the semiconductor substrate so that the drain region and the source region form corresponding metal-semiconductor junctions. 9.根据权利要求7所述电荷俘获非挥发半导体存储器的制造方法，其特征在于：所述第二金属层是钛层、钴层、镍层、铂层中任意一种或者其混合物。9. The method for manufacturing a charge-trapping non-volatile semiconductor memory according to claim 7, wherein the second metal layer is any one of a titanium layer, a cobalt layer, a nickel layer, a platinum layer or a mixture thereof. 10.根据权利要求7所述电荷俘获非挥发半导体存储器的制造方法，其特征在于：所述第二介质层的厚度小于所述第一介质层的厚度，且所述第一介质层的厚度小于所述第一开口与所述第二开口的宽度一半中较小的一个。10. The method for manufacturing a charge-trapping non-volatile semiconductor memory according to claim 7, characterized in that: the thickness of the second dielectric layer is smaller than the thickness of the first dielectric layer, and the thickness of the first dielectric layer is smaller than The smaller one of half the widths of the first opening and the second opening. 11.根据权利要求7所述电荷俘获非挥发半导体存储器的制造方法，其特征在于：所述第一介质层为二氧化硅层、氮化硅层或两者的混合层。11. The method for manufacturing a charge-trapping non-volatile semiconductor memory according to claim 7, wherein the first dielectric layer is a silicon dioxide layer, a silicon nitride layer or a mixed layer of the two. 12.根据权利要求7所述电荷俘获非挥发半导体存储器的制造方法，其特征在于：利用退火工艺使所述第二金属层与所述第一开口及第二开口内的半导体衬底发生反应而形成金属硅化物。12. The method for manufacturing a charge-trapping non-volatile semiconductor memory according to claim 7, wherein an annealing process is used to make the second metal layer react with the semiconductor substrate in the first opening and the second opening. Formation of metal silicides. 13.根据权利要求13所述电荷俘获非挥发半导体存储器的制造方法，其特征在于：所述金属硅化物与所述第一开口对应的漏极区域及所述第二开口对应的源极区域的半导体衬底接触形成金属半导体结，且其与所述第一开口对应的漏极区域及所述第二开口对应的源极区域的半导体衬底接触形成欧姆接触。13. The method for manufacturing a charge-trapping non-volatile semiconductor memory according to claim 13, characterized in that: the metal silicide and the drain region corresponding to the first opening and the source region corresponding to the second opening are The semiconductor substrate contact forms a metal-semiconductor junction, and it forms an ohmic contact with the semiconductor substrate contact of the drain region corresponding to the first opening and the source region corresponding to the second opening. 14.根据权利要求14所述电荷俘获非挥发半导体存储器的制造方法，其特征在于：所述制造方法进一步包括去除未与所述半导体衬底反应的第二金属层。14. The manufacturing method of the charge-trapping non-volatile semiconductor memory according to claim 14, characterized in that: the manufacturing method further comprises removing the second metal layer that does not react with the semiconductor substrate.
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