CN101800226B

CN101800226B - Polysilicon storage unit

Info

Publication number: CN101800226B
Application number: CN201010123727.0A
Authority: CN
Inventors: 顾靖
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-03-12
Filing date: 2010-03-12
Publication date: 2014-02-19
Anticipated expiration: 2030-03-12
Also published as: CN101800226A

Abstract

The invention provides a polysilicon storage unit which comprises a substrate, a first drain electrode region, a source electrode region, a second drain electrode region, a first drain electrode, a source electrode and a second drain electrode, a silicon nitride layer, a control grid, a first selection grid and a second selection grid, wherein the first drain electrode region, the source electrode region and the second drain electrode region are arranged in the substrate; the source electrode region is positioned between the first drain electrode region and the second drain electrode region; the first drain electrode, the source electrode and the second drain electrode are respectively educed from the first drain electrode region, the source electrode region and the second drain electrode region; the silicon nitride layer is positioned above the source electrode and used for storing electric charges; the control grid is positioned above the silicon nitride layer; the first selection grid is positioned between the first drain electrode and the source electrode; and the second selection grid is positioned between the source electrode and the second drain electrode. The provided storage unit has smart structural design and can effectively reduce the size of the storage unit.

Description

Polysilicon storage unit

Technical field

The present invention relates to a kind of semiconductor storage unit, and be particularly related to a kind of polysilicon storage unit.

Background technology

The advantages such as flash memory is convenient with it, and storage density is high, good reliability become the focus of studying in non-volatility memorizer.Since first flash memory products appearance 1980s, development and the demand of each electronic product to storage along with technology, flash memory is widely used in mobile phone, notebook, in the movement such as palmtop PC and USB flash disk and communication apparatus, flash memory is a kind of non-volatility memory, its operation principles is by changing switch that the critical voltage of transistor or memory cell controls gate pole passage to reach the object of storage data, the data that make to be stored in memory can not disappear because of power interruptions, and flash memory is a kind of special construction of electric erasable and programmable read-only memory.

Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, become non-volatile semiconductor memory with fastest developing speed, yet existing flash memory, in the high storage density of marching toward more, improves storage density by reduction of device size and will face very large challenge.Yet existing flash memory is in the high storage density of marching toward more, owing to being subject to the restriction of program voltage, by reduction of device size, improve storage density and will face very large challenge, thereby the flash memory of development high storage density is the important impetus of flash memory technology development.Traditional flash memory is in the high storage density of marching toward more, and owing to being subject to the restriction of structure, the program voltage of realizing device further reduces to be faced with very large challenge.

Generally speaking, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is due to its special structure, compare stacking gate flash memory and all embody its unique performance advantage in programming with when wiping, yet, in current prior art, thereby gate-division type flash memory with respect to stacking gate flash memory many word line make the area change of chip, in addition, even the gate-division type flash memory of shared word line, need apply larger program voltage (being generally greater than 3V) in source electrode or drain electrode and could realize the programming to memory cell, this just need extra in source region or drain region increase high-voltage tube, thereby cause the increase of chip area, be unfavorable for the further raising of flash memory storage density.

Summary of the invention

In order overcoming in prior art, by reduction of device size, to improve the problem that storage density runs into, to the invention provides the memory that a kind of volume is little, memory capacity is large.

To achieve these goals, the present invention proposes a kind of polysilicon storage unit, comprising: substrate and be formed at the first drain region, source area and the second drain region in described substrate, and described source area is between described the first drain region and described the second drain region; Respectively from described the first drain region, described source area and described the second drain region the first drain electrode, source electrode and second drain electrode of drawing; Silicon nitride layer, is positioned on described source electrode, and described silicon nitride layer is for stored charge; Control gate, is positioned on described silicon nitride layer; First selects grid, between described the first drain electrode and described source electrode; Second selects grid, between described source electrode and described the second drain electrode.

Optionally, described source electrode is connected with described the first drain electrode, described the second drain electrode respectively by metal lead wire.

Optionally, described the first drain electrode, described source electrode, described the second drain electrode, described control gate, described first select grid and described second to select all with oxide, to fill isolation between grid.

Optionally, when described memory is carried out to read operation, the voltage applying on described the first selection grid is 2.5V, the voltage applying on described the second selection grid is 0V, in described the first drain electrode and described the second drain electrode, applying voltage is 0.8V, on described control gate, applying voltage is 2.1V, and it is 0V that described source electrode applies voltage.

Optionally, when described memory is carried out to programming operation, the voltage applying on described the first selection grid is 2.5V, the voltage applying on described the second selection grid is 0V, in described the first drain electrode and described the second drain electrode, applying voltage is 10V, on described control gate, applying voltage is 10V, and it is 5V that described source electrode applies voltage.

Optionally, when described memory is carried out to erase operation, described first selects grid, described second to select the voltage applying in grid, described the first drain electrode, source electrode and described the second drain electrode to be 6V, and the voltage applying on described control gate is-5V.

Owing to having adopted technique scheme, compared with prior art, polysilicon storage unit of the present invention has the following advantages: in flash memory structure provided by the invention, two drain electrodes share a source electrode, with general CMOS process compatible, can be by changing the internal structure of memory in the situation that not changing manufacturing process technology, reduce the volume of memory, can effectively reduce the size of memory.

Accompanying drawing explanation

Fig. 1 is the structural representation of polysilicon storage unit of the present invention.

Embodiment

Below, the present invention is described further by reference to the accompanying drawings.

First, please refer to Fig. 1, Fig. 1 is the structural representation of polysilicon storage unit of the present invention, from scheming, can find out, polysilicon storage unit of the present invention comprises substrate 11 and is formed at the first drain region 12 in described substrate 11, source area 13 and the second drain region 14, described source area 13 is between described the first drain region 12 and described the second drain region 14, respectively from described the first drain region 12, the first drain electrode 15 that draw described source area 13 and described the second drain region 14, source electrode 10 and the second drain electrode 16, the first drain region 12, source area 13 and the second drain region 14 are by formation that substrate 11 is adulterated, silicon nitride layer 19, is positioned on described source electrode 10, and described silicon nitride layer 19 is to use as floating boom, for stored charge, in actual fabrication process, is to etch a shallow trench, then in this shallow trench, fills up silicon nitride, thereby forms the silicon nitride layer 19 in Fig. 1, control gate 20, is positioned on described silicon nitride layer 19, and from figure, silicon nitride layer 19 is between control gate 20 and source electrode 10, first selects grid 17, between described the first drain electrode 15 and described source electrode 10, second selects grid 18, between described source electrode 10 and described the second drain electrode 16.Described source electrode 10 is connected with described the first drain electrode 15, described the second drain electrode 16 respectively by metal lead wire, when they have electrical potential difference each other, just has electric current and flow through in lead-in wire.Described the first drain electrode 15, described source electrode 10, described the second drain electrode 16, described control gate 20, described first select grid 17 and described second to select all with oxide 21, to fill isolation between grid 18, are mainly in order to prevent conduction, to guarantee insulation each other.

During practical operation, for to memory programming, therefore must inject electronics to silicon nitride layer 19, the voltage applying on described the first selection grid 17 is 2.5V, the voltage applying on described the second selection grid 18 is 0V, in described the first drain electrode 15 and described the second drain electrode 16, applying voltage is 10V, and on described control gate 20, applying voltage is 10V, and it is 5V that described source electrode 13 applies voltage.

When described memory is carried out to read operation, the voltage applying on described the first selection grid 17 is 2.5V, the voltage applying on described the second selection grid 18 is 0V, in described the first drain electrode 15 and described the second drain electrode 16, applying voltage is 0.8V, on described control gate 20, applying voltage is 2.1V, and it is 0V that described source electrode 13 applies voltage.

When described memory is carried out to erase operation, described first selects grid 17, described second to select the voltage applying in grid 18, described the first drain electrode 15, source electrode 13 and described the second drain electrode 16 to be 6V, and the voltage applying on described control gate 20 is-5V.

Although the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.In technical field of the present invention, have and conventionally know the knowledgeable, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on claims person of defining.

Claims

1. a polysilicon storage unit, is characterized in that comprising:

Substrate and be formed at the first drain region, source area and the second drain region in described substrate, described source area is between described the first drain region and described the second drain region;

Respectively from described the first drain region, described source area and described the second drain region the first drain electrode, source electrode and second drain electrode of drawing;

Silicon nitride layer, is positioned on described source electrode, and described silicon nitride layer is that floating boom is for stored charge;

Control gate, is positioned on described silicon nitride layer, and described control gate is quadrilateral structure, and the bottom surface of described control gate is less than the described silicon nitride layer surface being in contact with it;

First selects grid, between described the first drain electrode and described source electrode;

Second selects grid, between described source electrode and described the second drain electrode;

Described the first drain electrode, described source electrode, described the second drain electrode, described control gate, described first select grid and described second to select all with oxide, to fill isolation between grid.

2. polysilicon storage unit according to claim 1, is characterized in that: described source electrode is connected with described the first drain electrode, described the second drain electrode respectively by metal lead wire.

3. polysilicon storage unit according to claim 1, it is characterized in that: when described memory is carried out to read operation, the voltage applying on described the first selection grid is 2.5V, the voltage applying on described the second selection grid is 0V, in described the first drain electrode and described the second drain electrode, applying voltage is 0.8V, on described control gate, applying voltage is 2.1V, and it is 0V that described source electrode applies voltage.

4. polysilicon storage unit according to claim 1, it is characterized in that: when described memory is carried out to programming operation, the voltage applying on described the first selection grid is 2.5V, the voltage applying on described the second selection grid is 0V, in described the first drain electrode and described the second drain electrode, applying voltage is 10V, on described control gate, applying voltage is 10V, and it is 5V that described source electrode applies voltage.

5. polysilicon storage unit according to claim 1, it is characterized in that: when described memory is carried out to erase operation, described first selects grid, described second to select the voltage applying in grid, described the first drain electrode, source electrode and described the second drain electrode to be 6V, and the voltage applying on described control gate is-5V.