CN101814460A - Active element array substrate and manufacturing method thereof - Google Patents

Abstract

The embodiment of the invention provides an active element array substrate and a manufacturing method thereof, wherein the active element array substrate is provided with at least one patterned conductive layer, the patterned conductive layer comprises a copper layer, the section of the copper layer in the direction parallel to the normal line of the copper layer is composed of a first trapezoid and a second trapezoid overlapped on the first trapezoid, and the bottom angle of the first trapezoid and the bottom angle of the second trapezoid are acute angles with the angle difference between 5 degrees and 30 degrees. Through the embodiment of the invention, better electrical performance can be provided, and the wire breakage rate is effectively improved.

Description

Active element array substrate and manufacturing method thereof

technical field

The present invention relates to an active device array substrate (Active Device Array Substrate), in particular to an active device array substrate with a copper conductive layer.

Background technique

As the size of the thin film transistor liquid crystal display (TFT-LCD) panel becomes larger and larger, it is accompanied by the resistance capacitance (RC) delay effect caused by the resistance of the metal wire not being low enough, thus causing distortion and distortion of the signal during transmission. , which affects the presentation of panel quality. Using a single-layer copper metal with low resistance to form a metal wire can effectively reduce the RC delay effect. However, when the copper metal is manufactured, copper oxide will be formed on the surface of the copper metal. Since the etching rate of the copper oxide on the copper surface layer is different from that of copper, the problem of disconnection is likely to occur during the etching manufacturing process.

Contents of the invention

The invention provides an active element array substrate, which has better electrical performance.

The invention provides a manufacturing method of an active element array substrate, through which the disconnection rate can be effectively improved.

The present invention proposes an active element array substrate, the active element array substrate has at least one patterned conductive layer, the patterned conductive layer includes a copper layer, and the section of the copper layer in the normal direction parallel to the copper layer is composed of a first trapezoid and a stack The second trapezoid is formed on the first trapezoid, and the base angle of the first trapezoid and the base angle of the second trapezoid are acute angles with an angle difference between 5° and 30°.

In an embodiment of the present invention, the angle difference between the base angle of the first trapezoid and the base angle of the second trapezoid is, for example, 7° to 13°.

In an embodiment of the present invention, the angle difference between the base angle of the first trapezoid and the base angle of the second trapezoid is, for example, 10°.

In an embodiment of the present invention, the above-mentioned patterned conductive layer further includes a barrier layer, and the copper layer is stacked on the barrier layer.

In an embodiment of the present invention, the material of the barrier layer is at least one selected from the group consisting of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminum alloy and copper alloy.

In an embodiment of the present invention, the height of the above-mentioned first trapezoid is, for example, greater than the height of the second trapezoid.

In an embodiment of the present invention, the height of the above-mentioned first trapezoid is, for example, between 1500 angstroms and 5000 angstroms, and the height of the second trapezoid is, for example, between 50 angstroms and 1500 angstroms.

In an embodiment of the present invention, the above-mentioned patterned conductive layer is a plurality of gates forming a plurality of active devices.

In an embodiment of the present invention, the above-mentioned patterned conductive layer is a plurality of sources and/or drains constituting a plurality of active devices.

The invention provides a method for manufacturing an active element array substrate, which includes the following steps. Firstly, a first copper layer is deposited on the substrate at a first deposition rate. Next, a second copper layer is deposited on the first copper layer at a second deposition rate, wherein the first deposition rate is greater than the second deposition rate. Then, the first copper layer and the second copper layer are patterned.

In an embodiment of the present invention, after the above-mentioned patterning of the first copper layer and the second copper layer, the first cross section of the first copper layer parallel to the normal direction of the first copper layer is, for example, a first trapezoid, and the first copper layer The second cross section of the second copper layer parallel to the normal direction of the first copper layer is, for example, a second trapezoid, and the base angle of the first trapezoid and the base angle of the second trapezoid are an acute angle, for example, between 5° and 30°. .

In an embodiment of the present invention, the above-mentioned method for depositing the first copper layer and the second copper layer includes a sputtering method.

In an embodiment of the present invention, the above-mentioned first deposition rate is more than twice of the second deposition rate.

In an embodiment of the present invention, before depositing the first copper layer, depositing a barrier layer on the substrate is further included, and the first copper layer is deposited on the barrier layer.

The beneficial effect of the embodiment of the present invention is that, in the active element array substrate proposed by the present invention, since the base angle of the first trapezoid and the base angle of the second trapezoid in the cross section of the copper layer have an angle difference between 5° and 30° The sharp angle, so it has a better appearance structure, so it can effectively avoid the generation of structural defects, and then improve the electrical performance.

In addition, in the manufacturing method of the active device array substrate proposed by the present invention, since the first deposition rate is greater than the second deposition rate, the second copper layer has better atomic arrangement, less film defects and lower oxidation speed, so it can effectively improve the broken wire ratio.

Description of drawings

1A to 1G are cross-sectional views of the manufacturing process of an active device array substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the patterned conductive layer 122 in FIG. 1E along another cross-sectional direction, wherein the cross-sectional direction in FIG. 2 is perpendicular to the cross-sectional direction in FIG. 1E .

[Description of main component symbols]

100: Substrate

102, 102a, 116, 116a: barrier layer

104, 104a, 106, 106a, 118, 118a, 120, 120a: copper layer

108, 122: patterned conductive layer

110: dielectric layer

112: Channel layer

114, 114a: ohmic contact layer

124: thin film transistor

126: protective layer

128: opening

130: pixel electrode

N: normal direction

T1, T2, T3, T4: trapezoidal

θ1, θ2, θ3, θ4: angles

Detailed ways

1A to 1G are cross-sectional views of the manufacturing process of an active device array substrate according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the patterned conductive layer 122 in FIG. 1E along another cross-sectional direction, wherein the cross-sectional direction in FIG. 2 is perpendicular to the cross-sectional direction in FIG. 1E .

First, referring to FIG. 1A , a substrate 100 is provided. The material of the substrate 100 is, for example, a transparent material, an opaque material, a flexible material, or a combination of the above materials.

Next, a barrier layer 102 can be optionally formed on the substrate 100 . The material of the barrier layer 102 is, for example, at least one selected from the group consisting of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminum alloy and copper alloy. The formation method of the barrier layer 102 is, for example, physical vapor deposition.

Then, a copper layer 104 is deposited on the barrier layer 102 at a first deposition rate. The method of forming the copper layer 104 is, for example, sputtering.

Next, a copper layer 106 is deposited on the copper layer 104 at a second deposition rate, wherein the first deposition rate is greater than the second deposition rate, and the first deposition rate is, for example, more than twice the second deposition rate. The method of forming the copper layer 106 is, for example, sputtering.

Afterwards, referring to FIG. 1B , the copper layer 106 , the copper layer 104 and the barrier layer 102 are patterned, and a patterned conductive layer 108 used as a gate is formed on the substrate 100 . The patterned conductive layer 108 includes a copper layer 106 a , a copper layer 104 a and a barrier layer 102 a formed by patterning the copper layer 106 , the copper layer 104 and the barrier layer 102 .

In addition, the section of the copper layer 104a parallel to the normal direction N of the copper layer 104a is, for example, a trapezoid T1, the section of the copper layer 106a parallel to the normal direction N of the copper layer 104a is, for example, a trapezoid T2, and the base angle θ1 of the trapezoid T1 is the same as that of the trapezoid The base angle θ2 of T2 is an acute angle with an angle difference, for example, between 5° and 30°. In one embodiment, the angle difference between the base angle θ1 of the trapezoid T1 and the base angle θ2 of the trapezoid T2 is, for example, 7° to 13°, for example, 10°. Wherein, the base angle θ1 is, for example, smaller than the base angle θ2. The bottom angle θ1 is, for example, smaller than 70°, and the bottom angle θ2 is, for example, smaller than 80°.

In addition, the height of the trapezoid T1 is, for example, greater than the height of the trapezoid T2. Wherein, the height of the trapezoid T1 is, for example, between 1500 angstroms and 5000 angstroms, and the height of the trapezoid T2 is, for example, between 50 angstroms and 1500 angstroms.

It should be noted that the so-called trapezoid in this embodiment refers to the situation that it is "substantially" a trapezoid, that is, as long as it is similar to a trapezoid in appearance, it belongs to the trapezoid referred to in this case. In addition, in this embodiment, the bottom angle of the trapezoid is what is called a "taper angle" in the prior art.

Then, referring to FIG. 1C , a dielectric layer 110 is formed on the substrate 100 to cover the patterned conductive layer 108 . The dielectric layer 110 is formed by, for example, chemical vapor deposition (CVD) or other suitable film deposition techniques, but not limited thereto. The dielectric layer 110 can be a single-layer structure or a multi-layer structure, and its material is, for example, an inorganic material, other dielectric materials, or a combination thereof. The material of the dielectric layer 110 in this embodiment is described by taking a dielectric material such as silicon oxide, silicon nitride or silicon oxynitride as an example.

Next, a stacked channel layer 112 and an ohmic contact layer 114 are formed on the dielectric layer 110 above the patterned conductive layer 108 . The channel layer 112 and the ohmic contact layer 114 are, for example, semiconductor layers with different doping concentrations. The channel layer 112 and the ohmic contact layer 114 are formed by, for example, using a suitable deposition method and patterning method, which will not be repeated here.

After that, referring to FIG. 1D , a barrier layer 116 covering the dielectric layer 110 and the ohmic contact layer 114 may be optionally formed on the substrate 100 . The material of the barrier layer 116 is, for example, at least one selected from the group consisting of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminum alloy and copper alloy. The formation method of the barrier layer 116 is, for example, physical vapor deposition.

Then, a copper layer 118 is deposited on the barrier layer 116 at a third deposition rate. The method of forming the copper layer 118 is, for example, sputtering.

Next, a copper layer 120 is deposited on the copper layer 118 at a fourth deposition rate, wherein the third deposition rate is greater than the fourth deposition rate, and the third deposition rate is, for example, more than twice the fourth deposition rate. The method for forming the copper layer 120 is, for example, sputtering.

Afterwards, referring to FIG. 1E , the copper layer 120, the copper layer 118 and the barrier layer 116 are patterned, and the patterned conductive layer 122 serving as the source and the drain is respectively formed above the channel layer 112 on both sides of the patterned conductive layer 108. , and after forming the patterned multi-layer conductive layer 122, part of the ohmic contact layer 114 can be removed to form the ohmic contact layer 114a. The patterned conductive layer 122 includes a copper layer 120 a , a copper layer 118 a and a barrier layer 116 a formed by patterning the copper layer 120 , the copper layer 118 and the barrier layer 116 .

In addition, please refer to FIG. 2 together, the section of the copper layer 118a parallel to the normal direction N of the copper layer 118a is, for example, a trapezoid T3, and the section of the copper layer 120a parallel to the normal direction N of the copper layer 118a is, for example, a trapezoid T4. The base angle θ3 of T3 and the base angle θ4 of the trapezoid T4 are acute angles with an angle difference between, for example, 5° to 30°. In one embodiment, the angle difference between the base angle θ3 of the trapezoid T3 and the base angle θ4 of the trapezoid T4 is, for example, 7° to 13°, for example, 10°. Wherein, the base angle θ3 is, for example, smaller than the base angle θ4. The bottom angle θ3 is, for example, smaller than 70°, and the bottom angle θ4 is, for example, smaller than 80°.

In addition, the height of the trapezoid T3 is, for example, larger than that of the trapezoid T4. Wherein, the height of the trapezoid T3 is, for example, between 1500 angstroms and 5000 angstroms, and the height of the trapezoid T4 is, for example, between 50 angstroms and 1500 angstroms.

So far, the fabrication of the thin film transistor 124 has been preliminarily completed. The thin film transistor 124 includes the patterned conductive layer 108 (serving as the gate), the channel layer 112 , the ohmic contact layer 114 a and the patterned conductive layer 122 (serving as the source and drain).

Next, referring to FIG. 1F , a protective layer 126 is formed on the thin film transistor 124 , wherein the protective layer 126 has an opening 128 , and the opening 128 exposes a portion of the patterned conductive layer 122 that is used as a drain. Wherein, the protection layer 126 can be a single-layer structure or a multi-layer structure, and its material includes inorganic materials, organic materials, other dielectric materials, or a combination thereof. When the material of the protective layer 126 is an inorganic material such as silicon nitride or silicon oxide, the formation method of the protective layer 126 having the opening 128 is, for example, to form a protective material layer (not shown) on the substrate 100 comprehensively by chemical vapor deposition first. shown), and then the protective material layer is formed by a patterned manufacturing process.

Afterwards, please refer to FIG. 1G , a pixel electrode 130 is formed on the protection layer 126 , and the pixel electrode 130 is electrically connected to the drain portion of the patterned conductive layer 122 of the thin film transistor 124 through the opening 128 . The pixel electrode 130 can be a single-layer structure or a multi-layer structure, and its material is, for example, a transparent material, a non-transparent material, or a combination thereof. This embodiment is described by taking the transparent material of indium tin oxide and/or indium zinc oxide as an example, but is not limited thereto. The method for forming the pixel electrode 130 is, for example, to form a pixel electrode layer (not shown) on the protective layer 126 by sputtering, and then pattern the pixel electrode layer.

It can be known from the above embodiments that compared with the deposition rate of the copper layers 104a, 118a, since the deposition rates of the copper layers 106a, 120a respectively covering the copper layers 104a, 118a are relatively slow, the copper layers 106a, 120a have better The arrangement of atoms, fewer film defects and lower oxidation speed can greatly reduce the disconnection rate in the active element array substrate.

It should be noted that, although in the above embodiment, the method for forming the patterned conductive layer is used to form the gate (patterned conductive layer 108 ), source and drain (patterned) in the active device array substrate respectively. The conductive layer 122) is described as an example, but not limited thereto. That is to say, as long as any one of the gates, scan lines, source electrodes, drain electrodes, data lines, other metal wires, and other metal electrodes in the active element array substrate is manufactured using the above-mentioned method for forming the patterned conductive layer , all belong to the scope covered by the manufacturing method of the active element array substrate of the present invention.

Hereinafter, an active device array substrate according to an embodiment of the present invention will be described with reference to FIG. 1G . The active device array can basically be applied to liquid crystal display (LCD), liquid crystal display-organic light emitting diode (TFT-OLED), electronic paper or other products.

Referring to FIG. 1G , the active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. The copper layer in the patterned conductive layer can be a single-layer structure or a multi-layer structure, as long as the cross-section of the copper layer in the normal direction parallel to the copper layer is composed of two stacked trapezoids, and the base angle of the two trapezoids is an angle An acute angle with a difference between 5° and 30° falls within the range covered by the active device array substrate of the present invention.

Taking the active device array substrate in FIG. 1G as an example, the patterned conductive layer in the active device array substrate is, for example, the patterned conductive layer 108 used as a gate and the patterned conductive layer 122 used as a source and a drain. Wherein, the copper layer in the patterned conductive layer 108 is, for example, a two-layer structure formed by stacking copper layers 104a, 106a, while the copper layer in the patterned conductive layer 122 is, for example, formed by stacking copper layers 118a, 120a. Two-layer structure, but not to limit the present invention.

The section of the copper layer of the patterned conductive layer 108 in the normal direction N parallel to the copper layer is, for example, composed of a trapezoid T1 (section of the copper layer 104a) and a trapezoid T2 (section of the copper layer 106a) stacked on the trapezoid T1. The base angle θ1 of T1 and the base angle θ2 of the trapezoid T2 are acute angles with an angle difference between, for example, 5° to 30°. In one embodiment, the angle difference between the base angle θ1 of the trapezoid T1 and the base angle θ2 of the trapezoid T2 is, for example, 7° to 13°, for example, 10°. Wherein, the base angle θ1 is, for example, smaller than the base angle θ2. The bottom angle θ1 is, for example, smaller than 70°, and the bottom angle θ2 is, for example, smaller than 80°. In addition, the height of the trapezoid T1 is, for example, greater than that of the trapezoid T2. Wherein, the height of the trapezoid T1 is, for example, between 1500 angstroms and 5000 angstroms, and the height of the trapezoid T2 is, for example, between 50 angstroms and 1500 angstroms.

Please refer to FIG. 2 together. The cross section of the copper layer of the patterned conductive layer 122 in the normal direction N parallel to the copper layer is, for example, composed of a trapezoid T3 (section of the copper layer 118a) and a trapezoid T4 (copper layer) stacked on the trapezoid T3. 120a), the base angle θ3 of the trapezoid T3 and the base angle θ4 of the trapezoid T4 are acute angles with an angle difference of, for example, 5° to 30°. In one embodiment, the angle difference between the base angle θ3 of the trapezoid T3 and the base angle θ4 of the trapezoid T4 is, for example, 7° to 13°, for example, 10°. Wherein, the base angle θ3 is, for example, smaller than the base angle θ4. The bottom angle θ3 is, for example, smaller than 70°, and the bottom angle θ4 is, for example, smaller than 80°. In addition, the height of the trapezoid T3 is, for example, greater than that of the trapezoid T4. Wherein, the height of the trapezoid T3 is, for example, between 1500 angstroms and 5000 angstroms, and the height of the trapezoid T4 is, for example, between 50 angstroms and 1500 angstroms.

In addition, the patterned conductive layers 108, 122 may further include barrier layers 102a, 116a, respectively. Copper layer 104a overlies barrier layer 102a, and copper layer 118a overlies barrier layer 116a. The material of the barrier layers 102a and 116a is, for example, at least one selected from the group consisting of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminum alloy and copper alloy.

In addition, the active device array substrate also includes components such as a substrate 100, a dielectric layer 110, a channel layer 112, an ohmic contact layer 114a, a protective layer 126, and a pixel electrode 130. It has been described in detail in the previous embodiments, so it will not be repeated here.

Based on the above, in the active element array substrate proposed by the present invention, since the bottom angle θ1 (or θ3) of the trapezoid T1 (or T3) and the bottom angle θ2 (or θ4) of the trapezoid T2 (or T4) in the section of the copper layer ) is an acute angle with an angle difference ranging from 5° to 30°, so it has a better appearance structure, and thus can effectively prevent the occurrence of structural defects, thereby improving electrical performance.

Although the patterned conductive layer in this embodiment is described as the gate (patterned conductive layer 108 ), source and drain (patterned conductive layer 122 ) in the active array substrate as an example, as long as the active Any one of the gates, scan lines, source electrodes, drain electrodes, data lines, other metal wires, and other metal electrodes in the array substrate is the structure of the above-mentioned patterned conductive layer, which belongs to the scope of the present invention. scope.

Table 1 is a comparative table of the disconnection rate of copper wires of the prior art and the present invention.

Table 1

In Table 1, in Comparative Examples 1 and 2, when the copper metal film is formed, the copper layer is formed by only one rapid deposition with high power. Therefore, after the copper layer is patterned to form a copper wire, the cross-section is a single trapezoid, and The disconnection rate is high.

Experimental examples 1, 2, and 3, when the copper metal film is formed, first perform a rapid deposition with high power to form the lower copper layer, and then perform a slow deposition with low power (its power is 1/3 of the high power) The upper copper layer is deposited to form an upper copper layer, and the upper copper layer is laminated on the lower copper layer to form a copper stack layer. Therefore, after the copper stack layer is patterned to form a copper wire, the cross-section is a double overlapping trapezoid, and the disconnection rate is low.

In summary, the above embodiment has at least the following advantages:

1. The manufacturing method of the above-mentioned active device array substrate can effectively improve the disconnection rate.

2. The above-mentioned active device array substrate has better electrical performance.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the patent application.

Claims (14)

1. active component array base board, it is characterized in that, described active component array base board has at least one patterned conductive layer, described patterned conductive layer comprises a bronze medal layer, described copper layer a section of a normal direction of parallel copper layer be by one first trapezoidal be stacked in first one second on trapezoidal and trapezoidally constitute, the described first trapezoidal base angle and the described second trapezoidal base angle are angle difference between 5 ° to 30 ° acute angle.

2. active component array base board according to claim 1 is characterized in that, the angle difference at the described first trapezoidal base angle and the described second trapezoidal base angle is between 7 ° to 13 °.

3. active component array base board according to claim 1 is characterized in that, the angle difference at the described first trapezoidal base angle and the described second trapezoidal base angle is 10 °.

4. active component array base board according to claim 1 is characterized in that described patterned conductive layer also comprises a barrier layer, and described copper is layered on the described barrier layer.

5. active component array base board according to claim 4 is characterized in that, the material of described barrier layer is to be selected from the group that is made up of molybdenum, molybdenum alloy, titanium, titanium alloy, aluminium alloy and copper alloy at least one.

6. active component array base board according to claim 1 is characterized in that, described first is trapezoidal tall and big in the described second trapezoidal height.

7. active component array base board according to claim 1 is characterized in that, the described first trapezoidal height is between 1500 dust to 5000 dusts, and the described second trapezoidal height is between 50 dust to 1500 dusts.

8. active component array base board according to claim 1 is characterized in that, described patterned conductive layer is a plurality of grids that constitute a plurality of active members.

9. active component array base board according to claim 1 is characterized in that, described patterned conductive layer is a plurality of source electrodes and/or the drain electrode that constitutes a plurality of active members.

10. a manufacture method of initiative element array is characterized in that, described manufacture method comprises:

Deposit one first bronze medal layer on a substrate with one first deposition rate;

Deposit one second bronze medal layer on the described first bronze medal layer with one second deposition rate, wherein said first deposition rate is greater than described second deposition rate; And

Described first bronze medal layer of patterning and the described second bronze medal layer.

11. manufacture method of initiative element array according to claim 10, it is characterized in that, behind described first bronze medal layer of patterning and the described second bronze medal layer, the described first bronze medal layer is one first trapezoidal at one first section of a normal direction of the parallel first bronze medal layer, the described second bronze medal layer is one second trapezoidal at one second section of the normal direction of the parallel first bronze medal layer, and the described first trapezoidal base angle and the described second trapezoidal base angle are angle difference between 5 ° to 30 ° acute angle.

12. manufacture method of initiative element array according to claim 10 is characterized in that, the method that deposits described first bronze medal layer and the described second bronze medal layer comprises sputtering method.

13. manufacture method of initiative element array according to claim 10 is characterized in that, described first deposition rate is more than the twice of described second deposition rate.

14. manufacture method of initiative element array according to claim 10 is characterized in that, before the deposition first bronze medal layer, also comprise deposition one barrier layer on substrate, and the described first bronze medal layer is to be deposited on the described sun barrier layer.

Images