CN101834170B - Chip structure capable of suppressing outside high-frequency noise - Google Patents
Chip structure capable of suppressing outside high-frequency noise Download PDFInfo
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- CN101834170B CN101834170B CN 201010146898 CN201010146898A CN101834170B CN 101834170 B CN101834170 B CN 101834170B CN 201010146898 CN201010146898 CN 201010146898 CN 201010146898 A CN201010146898 A CN 201010146898A CN 101834170 B CN101834170 B CN 101834170B
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- ground
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Filters And Equalizers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention discloses a chip structure capable of suppressing outside high-frequency noise, which is characterized by comprising at least two ground bonding pads, wherein one of the ground bonding pads is connected with the internal circuit of a chip to form 'clean ground', and the other ground bonding pads are connected with an anti-static protection circuit of the bonding pad with a high-frequency interference source to form 'dirty ground'; an isolation resistor is arranged between the 'clean ground' and the 'dirty ground'; and a filtering circuit is arranged between the internal circuit and the bonding pad with the high-frequency interference source. By additionally providing a 'clean' ground bonding pad and a filtering structure consisting of a resistor, a capacitor and a parasitic inductor on a binding line, the invention achieves better filtering effect at a certain frequency and effectively suppresses the high-frequency noise.
Description
Technical field
The present invention relates to the Electro Magnetic Compatibility field, relate in particular to a kind of chip structure that can suppress the electromagnetic interference in the particular frequency range.
Background technology
Along with the development of wireless communication technique and the raising of circuit work frequency, the electromagnetic interference phenomenon is more and more serious, and (Electro Magnetic Compatibility, design EMC) is also more and more important for Electro Magnetic Compatibility.Generally speaking, the design of Electro Magnetic Compatibility is on circuit board, to improve mostly, in the periphery of chip filter circuit is set, and these circuit are made up of devices such as magnetic bead, electric capacity, inductance, resistance usually.But, when being used for the high-frequency noise inhibition, can cause the increase of cost, it is bigger that board area also becomes.In some application scenario, the control ratio of area is crucial especially, and at this moment, this method just can't meet the demands.Therefore, need to consider how to improve the structure of chip, rather than filter circuit is set in the periphery of chip.
In the prior art, shown in Figure 1 is common chip power supply pad pin configuration sketch map, is provided with anti-static protection circuit between pad VDD and the GND, between VDD and GND, has produced a parasitic capacitance inevitably.Similarly, between other pad and GND, perhaps, (for the anti-static protection circuit structure that is total to VDD) also can produce parasitic capacitance between other pad and VDD.
Shown in Figure 2 is the chip power supply circuit structured flowchart, and the VDD pad links to each other with the GND pad through anti-static protection circuit ESD.The high-frequency noise EMI that VDD pad place exists will inject internal circuit through connecting line, reduce the service behaviour of chip.
Even if in chip, be provided with filter, as shown in Figure 3, noise still can flow into circuit board through the lead-in wire that is connected with the ground pad of chip, to form the loop.For common line footpath 25um, be about the lead-in wire of 0.8mm-2mm, stray inductance is approximately 0.5nH to 2nH, and under the 2.4GHz frequency, its impedance is about 9ohm-33ohm.And general anti-static protection circuit has the parasitic capacitance of 2pF-3pF at least from the pad to the substrate, and under the 2.4GHz frequency, its impedance is about 33ohm-22ohm.As shown in Figure 3, the noise signal of 2.4GHz can be easy to through the parasitic capacitance in the anti-static protection circuit, arrives the ground pad of chip, and then flows into circuit board through lead-in wire.In this process, noise is introduced into the ground pad of chip, and the ground of chip has just become one " dirty ground ", and thus, the performance of the internal circuit that is connected with " dirty ground " will descend.
And if add low pass filter before the anti-static protection circuit; Repid discharge meeting to anti-static protection circuit produces very big influence so; Make high-pressure electrostatic not obtain in the short time discharging at the utmost point; Thereby can influence the effect of anti-static protection circuit, even cause the anti-static protection circuit disabler.
Therefore, if can improve chip structure, make it that high-frequency noise is had good inhibition effect, the peripheral circuit with the ability facilitating chip effectively reduces the shared area of circuit.
Summary of the invention
The object of the invention provides a kind of improved chip structure, with effective inhibition high-frequency noise, thus the Electro Magnetic Compatibility of improvement chip.
For achieving the above object, the technical scheme that the present invention adopts is: a kind of chip structure that suppresses outside high-frequency noise,
Be provided with at least 2 ground pads (PAD); One of them ground pad is connected with the internal circuit of chip; Be called " neatly " (clean ground), other ground pad is connected with the anti-static protection circuit of the pad that the High-frequency Interference source is arranged, and is called " dirty ground " (dirty ground);
Be provided with isolation resistance between said " neatly " and " dirty ground ";
Between said pad that the High-frequency Interference source arranged and internal circuit, be provided with filter circuit.
In the technique scheme, said isolation resistance is made up of the clear area between said " neatly " and " dirty ground ".
In the technique scheme, the resonance frequency of the stray inductance on the parasitic capacitance of said anti-static protection circuit and " dirty ground " lead-in wire drops near the noise frequency.
Also can on said anti-static protection circuit, be parallel with electric capacity, the equivalent capacity of the electric capacity of the parasitic capacitance of anti-static protection circuit and parallel connection and the resonance frequency of the stray inductance on " dirty ground " lead-in wire drop near the noise frequency.
In the technique scheme, said filter circuit is made up of the resistance between pad that is serially connected in the High-frequency Interference source and the internal circuit, the stray inductance that is connected across on resistance and the electric capacity between " neatly ", " neatly " lead-in wire.
The resonance frequency of said filter circuit drops near the noise frequency, constitutes the trap circuit to high-frequency noise.
When on some o pads the High-frequency Interference source being arranged; Optimized technical scheme; Be provided with 3 ground pads; Wherein first ground pad is connected with the internal circuit of chip, and second ground pad is connected with the anti-static protection circuit of the input pad that the High-frequency Interference source is arranged, and the 3rd ground pad is connected with the anti-static protection circuit of the o pads that the High-frequency Interference source is arranged.
Ground in the technique scheme also can be reference level, and at this moment, the technical scheme that can adopt is, a kind of chip structure that suppresses outside high-frequency noise,
Be provided with at least 2 reference level pads; One of them reference level pad is connected with the internal circuit of chip; Be called " clean level ", other reference level pad is connected with the anti-static protection circuit of the pad that the High-frequency Interference source is arranged, and is called " dirty level ";
Be provided with isolation resistance between said " clean level " and " the dirty level ";
Between said pad that the High-frequency Interference source arranged and internal circuit, be provided with filter circuit.
Reference level wherein also can be power supply, specifically looks the chip internal syndeton and decides.
Because the technique scheme utilization, the present invention compared with prior art has advantage:
1. the invention provides a kind of effective high-frequency filter circuit, through one of extra increase pad " clean ", and the filter structure formed of the stray inductance on the resistance, electric capacity, nation's alignment, reaching has filter effect preferably on a certain frequency; The anti-static protection circuit structure that possibly introduce the pad of High-frequency Interference only links to each other with " dirty ground ", and separates " neatly " and " dirty ground ", can better High-frequency Interference be kept apart.
2. when having noisy o pads, the noise on other pad injects o pads, and the present invention can be provided with 2 or more " dirty ground ", has further guaranteed the performance of chip, has good Electro Magnetic Compatibility.
Description of drawings
Fig. 1 is a chip power supply pad pin configuration sketch map common in the prior art;
Fig. 2 is a prior art chips power supply circuit construction block diagram;
Fig. 3 is the chip circuit block diagram that has inner filter portion circuit in the background technology;
Fig. 4 is a kind of chip circuit structural representation in the embodiment of the invention;
Fig. 5 is the layout and the pin configuration sketch map of a kind of chip structure among the embodiment.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further described:
Embodiment:
Shown in Figure 4 is the chip circuit structural representation of the embodiment of the invention, in common chip structure, increases pad second a ground 3a, between interference source 1 and internal circuit 5, adds one by resistance R
LP, capacitor C
2, the stray inductance L on the lead-in wire
GND1The filter circuit 3 that constitutes, and internal circuit 5 is connected to the second ground 3a, and the anti-static protection circuit of VDD pad (ESD) is connected to the first ground 2b, and between the first ground 2b and the second ground 3a, an isolation resistance 4 is set.Through at sizeable electric capacity of anti-static protection circuit structure side parallel connection, perhaps regulate the parasitic capacitance size of anti-static protection circuit, make C
ESD(perhaps C
ESDWith C
1The equivalent capacity of parallel connection) and L
GND0Resonance frequency drop near the noise frequency.When resonance frequency, the impedance theory value of oscillation circuit is zero, promptly from interference source 1 to having a low impedance path the circuit board through the first ground 2b.And because R
LPWith R
ParaExistence, make from interference source 1 to be a high impedance path to circuit board through the second ground 3a.Thereby most of noise current passes through from the first ground 2b, and the noise on the second ground 3a is weakened greatly.Below, claiming that the first ground 2b is " dirty ground ", the second ground 3a is " neatly ".
Referring to Fig. 4, filter circuit 3 also has the another one function: through control capacittance C
2Size, make C
2With L
GND1Resonance frequency near noise frequency, filter circuit 3 becomes a desirable trap circuit at the noise frequency place so, can greatly be suppressed at a noise at 3b place.
So in Fig. 4, no matter be the second ground 3a in inside, still at the access point 3b of interference source 1 to internal circuit 5, the high-frequency noise of CF has all been suppressed greatly.
Referring to Fig. 4, for the pad 7 in noiseless source, it is last that its anti-static protection circuit 6 is connected to " neatly " 3a.
Similarly, a plurality of structures can be set, to suppress high-frequency noise respectively from different pads.Two kinds of situation can be arranged: 1. many have the pad of interference source to be connected to one " dirty ground " through anti-static protection circuit, and internal circuit is connected to one " neatly ".2. if some noisy o pads are arranged, the noise on other pad injects o pads, and another " dirty ground " of connecting noisy o pads need be set.Both of these case is application example of the present invention equally.
Fig. 5 is the layout and the pin configuration sketch map of the embodiment of the invention.Wherein isolation resistance is through between " dirty ground " and " neatly ", staying one section clear area to realize; In this clear area any contact hole is not set; Just " dirty ground " and " neatly " are coupled together through substrate; To form dead resistance, its resistance size can be regulated through the width of clear area.
Such as for common circuit and pin configuration: lead-in wire line footpath: 25um; Lead-in wire is about 1.5mm, and the parasitic capacitance of anti-static protection circuit approximately is 2.5pF, places the filter capacitor of different sizes; Noise to 1GHz, from the interference source to ground, have only-3dB is to the decay of-6dB.And in chip of the present invention, get R
LPBe 100ohm, R
ParaBe 100ohm, C
2Be 10pF, the decay in " neatly " approximately is-21dB is to-24dB, and more can reach at a 3b-decay more than the 40dB.It is thus clear that the present invention can effectively suppress high-frequency noise.
Claims (8)
1. chip structure that can suppress outside high-frequency noise is characterized in that:
Be provided with at least 2 ground pads, one of them ground pad is connected with the internal circuit of chip, is called " neatly ", and other ground pad is connected with anti-static protection circuit on the pad that is connected the High-frequency Interference source, is called " dirty ground ";
Be provided with isolation resistance between said " neatly " and " dirty ground ";
Between said pad that the High-frequency Interference source arranged and internal circuit, be provided with filter circuit.
2. the chip structure that suppresses outside high-frequency noise according to claim 1 is characterized in that: said isolation resistance is made up of the clear area between said " neatly " and " dirty ground ".
3. the chip structure that suppresses outside high-frequency noise according to claim 1 is characterized in that: the parasitic capacitance (C of said anti-static protection circuit
ESD) with " dirty ground " lead-in wire on stray inductance (L
GND0) resonance frequency drop on the noise frequency place.
4. the chip structure that suppresses outside high-frequency noise according to claim 1 is characterized in that: be parallel with electric capacity (C on the said anti-static protection circuit
1), the parasitic capacitance (C of anti-static protection circuit
ESD) and parallelly connected electric capacity (C
1) equivalent capacity and " dirty ground " lead-in wire on stray inductance (L
GND0) resonance frequency drop on the noise frequency place.
5. the chip structure that suppresses outside high-frequency noise according to claim 1 is characterized in that: said filter circuit is by the resistance (R between pad that is serially connected in the High-frequency Interference source and the internal circuit
LP), be connected across resistance (R
LP) and " neatly " between electric capacity (C
2), the stray inductance (L on " neatly " lead-in wire
GND1) constitute.
6. the chip structure that suppresses outside high-frequency noise according to claim 5 is characterized in that: the resonance frequency of said filter circuit drops on the noise frequency place, constitutes the trap circuit to high-frequency noise.
7. the chip structure that suppresses outside high-frequency noise according to claim 1; It is characterized in that: be provided with 3 ground pads; Wherein first ground pad is connected with the internal circuit of chip; Second ground pad is connected with the anti-static protection circuit of the input pad that the High-frequency Interference source is arranged, and the 3rd ground pad is connected with the anti-static protection circuit of the o pads that the High-frequency Interference source is arranged.
8. chip structure that can suppress outside high-frequency noise is characterized in that:
Be provided with at least 2 reference level pads; One of them reference level pad is connected with the internal circuit of chip; Be called " clean level ", other reference level pad is connected with anti-static protection circuit on the pad that is connected the High-frequency Interference source, is called " dirty level ";
Be provided with isolation resistance between said " clean level " and " the dirty level ";
Between said pad that the High-frequency Interference source arranged and internal circuit, be provided with filter circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010146898 CN101834170B (en) | 2010-04-15 | 2010-04-15 | Chip structure capable of suppressing outside high-frequency noise |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010146898 CN101834170B (en) | 2010-04-15 | 2010-04-15 | Chip structure capable of suppressing outside high-frequency noise |
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| CN101834170A CN101834170A (en) | 2010-09-15 |
| CN101834170B true CN101834170B (en) | 2012-07-25 |
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| CN 201010146898 Expired - Fee Related CN101834170B (en) | 2010-04-15 | 2010-04-15 | Chip structure capable of suppressing outside high-frequency noise |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5668894B2 (en) * | 2012-04-25 | 2015-02-12 | 株式会社村田製作所 | Wireless IC device and wireless communication terminal |
| CN102842898B (en) * | 2012-09-10 | 2014-10-29 | 广州润芯信息技术有限公司 | Electrostatic discharge protection circuit |
| CN112859983B (en) * | 2021-01-06 | 2022-04-12 | 深圳市紫光同创电子有限公司 | Chip power regulation circuit and method |
| CN114496999B (en) * | 2021-09-06 | 2023-10-24 | 上海芯圣电子股份有限公司 | Chip packaging structure for reducing parasitic resistance |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1073208A2 (en) * | 1999-07-29 | 2001-01-31 | Murata Manufacturing Co., Ltd. | High frequency switching component |
| CN101542924A (en) * | 2007-05-10 | 2009-09-23 | 株式会社村田制作所 | Composite high-frequency component |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007214226A (en) * | 2006-02-08 | 2007-08-23 | Oki Electric Ind Co Ltd | ESD protection circuit |
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2010
- 2010-04-15 CN CN 201010146898 patent/CN101834170B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1073208A2 (en) * | 1999-07-29 | 2001-01-31 | Murata Manufacturing Co., Ltd. | High frequency switching component |
| CN101542924A (en) * | 2007-05-10 | 2009-09-23 | 株式会社村田制作所 | Composite high-frequency component |
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| CN101834170A (en) | 2010-09-15 |
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Owner name: KUODA ELECTRONIC (SHANGHAI) CO., LTD. Free format text: FORMER OWNER: SUZHOU KONTEL MICROELECTRONICS CO., LTD. Effective date: 20130122 |
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Free format text: CORRECT: ADDRESS; FROM: 215021 SUZHOU, JIANGSU PROVINCE TO: 201803 JIADING, SHANGHAI |
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Effective date of registration: 20130122 Address after: 201803, room 337, 301 Shahe Road, Shanghai, Jiading District Patentee after: Da Da electronic (Shanghai) Co., Ltd. Address before: Suzhou City, Jiangsu Province, Suzhou Industrial Park 215021 Xinghu Street No. 328 B9-401-1 Patentee before: Suzhou Kuoda Microelectronics Co., Ltd. |
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Granted publication date: 20120725 Termination date: 20160415 |