CN101839941B - Signal sensing amplifier - Google Patents

Abstract

The invention discloses a signal sensing amplifier, which comprises a differential transconductance input circuit, a differential cascode transconductance amplifying circuit and an active load circuit; the differential transconductance input circuit is a symmetrical structure capable of realizing a wide common-mode input range The voltage-to-current differential input stage; the differential cascode transconductance amplifier circuit includes transistors M ₅ and M ₆ of the same type and size, C _B3 and C _B4 are respectively connected to the sources of M ₅ and M ₆ and provide DC current bias. The present invention provides a wide common-mode input that can preferentially support CMOS technology, especially a high-speed, high-precision, low-voltage, low-power sense amplifier that can be wider than the power supply voltage rail. The circuit is not affected by technology, power supply voltage, The effect of temperature (PVT) drift can be implemented as either a comparator function or an amplifier function to implement a current sensing or sensing circuit.

Description

signal sense amplifier

Technical field

The present invention relates to a signal sense amplifier, in particular, a high-speed sense amplifier circuit with low voltage, low power consumption, and a common-mode input range that can be extended beyond the power supply voltage rail, which is used for the current transmission channel of power supply equipment Detect the current state of the channel or sense the magnitude of the channel current.

Background technique

At present, in many consumer electronics, communication equipment, and computer equipment power supplies, DC conversion processing is often required to meet the power supply voltage requirements of different loads. In these applications, the typical converter is a DC-DC converter, which occupies a large amount of volume, power consumption and cost of electronic equipment. The future development trend of electronic equipment is low voltage, low power consumption, miniaturization and low cost, which requires the DC-DC converter circuit design to develop towards low voltage, low power consumption and high efficiency, and the switching frequency of the DC-DC converter towards High-frequency development (DC-DC converters with a switching frequency of ten megahertz is the future development trend), and the manufacturing process is developing towards low-cost CMOS processes. Because the current-controlled DC-DC converter has fast transient response, simple control, easy compensation, high-precision output voltage and inherent control and limitation capabilities of the power switch current, DC-DC converters mostly use current control. mode, but in the face of the future development trend of electronic equipment, the current detection or current sensing circuit necessary for current control has been greatly challenged in terms of low voltage, low power consumption, high speed, and high precision.

In the current control mode, the controller needs to know the current state information of the current channel before determining the control signal to the power switch. This requires real-time sensing of the current magnitude of the current channel, or current detection of the current state of the channel (such as peak current state detection, valley current state detection, or zero current state detection). For the sensing of current magnitude, the output waveform is the voltage or current waveform after the channel waveform is scaled by a proportional constant. For the detection of the current state, the output waveform is a digital level, and when the detected current reaches the preset threshold, the detected waveform will jump to the corresponding digital level state.

Taking the low-cost CMOS process as an example, in theory, the current detection or sensing circuit has two modes of gate signal input and source signal input. The structure using the gate input signal is limited by the narrow common-mode input range, and cannot effectively operate outside its power supply voltage rail. Its application is limited when the common-mode detection or sensing voltage is within the supply voltage rail or slightly wider. occasions. This situation can be better described through Figure 1a. In Figure 1a, a traditional amplifier with a folded cascode structure is described. The gain of the amplifier is relatively high, but its input common-mode range needs to ensure that the differential input tube M ₁ , If _M2 does not enter the linear region, it must also ensure that its current bias sources C _B2 and C _B3 work normally, so that there is an upper limit for its common-mode input range, and the maximum value of its common-mode input range is:

V _{CM_MAX} ＝V _DD +V _TH -V _CB23 (1)

in:

V _DD is the supply voltage;

V _TH is the threshold voltage of the differential pair tubes M1 and M2;

V _CB23 is the minimum voltage difference required across the current sources C _B2 and C _B3 for normal operation.

It can be seen from formula (1) that the maximum common-mode input voltage of the circuit is limited by its supply voltage, the threshold voltage of the differential pair crystal, and the minimum operating voltage drop of the current source. In terms of speed, most common-source circuits will affect their response speed due to the Miller phenomenon of the differential pair tube.

Therefore, for common-mode detection or sensing voltage operation outside the power supply voltage rail, the common-gate method of inputting signals from the source is generally used. Although the general common-gate input method can produce differential Low, but the asymmetry of its structure, especially in the CMOS process, makes its performance seriously affected by process, power supply voltage and temperature (PVT) drift, and its robustness is poor, especially its simple structure, it is difficult to improve its Gain-bandwidth product, which limits its speed and accuracy. This situation can be better described by Figure 1b, which depicts a double-ended to single-ended differential amplifier with a source input signal, where _M1 is diode-connected to couple the _V1N signal to the gate of _M2 and The source signal V _IP of M ₂ forms a differential mode operation, but due to the asymmetry of the structure, on the one hand, when the circuit is used as a comparator, its threshold value is seriously affected by PVT drift; on the other hand, when the structure is used as a When the amplifier is used, since the drain of _M2 is used as the output, the DC fluctuation of the output voltage will cause the DC operating point mismatch of the drain voltage of _M1 and _M2 , which will deteriorate the input offset voltage. Moreover, the common-mode admittance from the output to the input of the structure is equal to the transconductance of _M2 , resulting in a very low common-mode rejection ratio. Its gain characteristic is limited by the highest gain characteristic of M ₂ , which is M _2's own transconductance g _m (M ₂ ) divided by its source-drain admittance g _ds (M ₂ ), if you want to enhance its gain or common-mode rejection ratio or M The matching of ₁ and M ₂ needs to be connected with a common source amplifier in the rear stage, but this will seriously limit its bandwidth due to the Miller phenomenon introduced by the common source.

Contents of the invention

In view of the disadvantages of the prior art, the object of the present invention is to provide a wide common-mode input range that can preferentially support CMOS technology, especially a high-speed, high-precision, low-voltage, low-power sense amplifier that can be wider than the supply voltage rail , the circuit is not affected by process, power supply voltage, and temperature (PVT) drift, and can be used not only as a comparator to implement a current detection circuit, but also as an amplifier to implement a current sensing circuit.

Therefore, the technical solution of the sense amplifier of the present invention is shown in FIG. 2 , which includes a differential transconductance input circuit, a differential cascode transconductance amplifier circuit and an active load circuit. The differential transconductance input circuit is a voltage-to-current differential input stage with a symmetrical structure capable of realizing a wide common-mode input range, including (M ₁ , M ₂ ) for generating a differential current, and (M ₃ , M ₄ ) Another branch for generating differential currents, M ₁ -M ₄ are transistors of the same type, wherein M ₁ and M ₄ have the same size, and M ₂ and M ₃ have the same size. And M ₁ and M ₄ are both connected by diodes and provided with DC current bias by C _B1 and C _B2 respectively, the sources (or emitters) of M ₁ and M ₃ are connected together to form an input end of the differential input stage, The source (or emitter) of M ₄ and M ₂ are connected together to form another input terminal of the differential input stage, and the drains (or collectors) of M ₂ and M ₃ are used as the output terminal of the differential current and the next stage The input terminals are connected; the differential cascode transconductance amplifying circuit includes transistors M ₅ and M ₆ of the same type and size, C _B3 and C _B4 are respectively connected to the sources (or emitters) of M ₅ and M ₆ and Provide DC current bias, this connection point is used as the differential current input terminal of this stage, the gates (or bases) of _M5 and _M6 have a common DC voltage bias V _B , the respective drains of _M5 and _M6 are connected to The active load circuit is connected to form the signal amplification as the output terminal of the sense amplifier of the present invention.

The invention uses the source (or emitter) to input the differential signal, has a wide range of common-mode input voltage, and the circuit adopts a symmetrical structure with better robustness, and the internal signal is transmitted in the form of current, which can realize high gain bandwidth with low power Accumulated, fast response. In the following, specific embodiments will be described in detail with reference to the accompanying drawings, so as to make it easier to understand the purpose, technical content, features and effects of the present invention.

Description of drawings

Figure 1a Folded cascode amplifier with conventional gate input signal

Figure 1b Conventional Sense Amplifier for Source Input Signals

Fig. 2 sense amplifier block diagram of the present invention

An example circuit diagram of the sense amplifier of the present invention in Fig. 3a

Another example circuit diagram of the sense amplifier of the present invention that can be used as a comparator in Fig. 3b

Figure 4a One of the typical applications of the current sensing circuit using the example circuit of Figure 3a

Fig. 4b adopts the simulated waveform of one of the typical applications of the current sensing circuit of the example circuit in Fig. 3a Embodiments of the present invention

(1) Technical Description of Invention Block Diagram

The technical solution of the sense amplifier of the present invention is shown in FIG. 2 , which includes a differential transconductance input circuit, a differential cascode transconductance amplifier circuit and an active load circuit. The differential transconductance input circuit is a voltage-to-current differential input stage with a symmetrical structure capable of realizing a wide common-mode input range, including (M ₁ , M ₂ ) for generating a differential current, and (M ₃ , M ₄ ) The other branch that generates the differential current, M ₁ to M ₄ are transistors of the same type, wherein M ₁ and M ₄ have the same size, M ₂ and M ₃ have the same size, M ₁ or M ₄ and M The equivalent width-to-length ratio of ₂ or _M3 is M:N. And M ₁ and M ₄ are both connected by diodes and provided with DC current bias by C _B1 and C _B2 respectively, and the sources (or emitters) of M ₁ and M ₃ are connected together to form an input terminal V of the differential input stage _IP , M ₄ and the source (or emitter) of M ₂ are connected together to form another input terminal V _IN of the differential input stage. At this time, the AC part of V _IP is directly coupled to the gate of M ₂ through M ₁ (or Base), the AC part of V _IN is directly coupled to the gate (or base) of _M3 through _M4 , and the drains (or collectors) of _M2 and _M3 are output as differential current (Δi _D1 , Δi _D2) end, and satisfy:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&Delta;v</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="m"\; filenames="HSA00000126362900032.png"\; state="\{\{state\}\}">m</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

为M₂和M₃的跨导；in:

is the transconductance of M ₂ and M ₃ ;

Δv is the differential pressure at the input.

The advantage of using the source (emitter) input signal for this input stage is that it can get a theoretically unlimited common-mode input range, and its minimum common-mode input voltage is:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; CM</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; MIN</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; SG</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 1.2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

in:

是M₁，M₄的源-栅(或发射极-基极)驱动电压；

is the source-gate (or emitter-base) driving voltage of M ₁ and M ₄ ;

是电流源C_B1和C_B2正常工作时其两端需要的最小电压差。

It is the minimum voltage difference between the two ends of the current sources C _B1 and C _B2 when they work normally.

The output end of the differential current (Δi _D1 , Δi _D2 ) is connected to the input end of the differential cascode transconductance amplifier circuit, including transistors M ₅ and M ₆ of the same type and size, and C _B3 and C _B4 are respectively connected to M The sources (or emitters, preferably FETs) of ₅ and _M6 are connected and provide DC current bias. This connection point is used as the differential current input terminal of this stage, and the gates (or bases) of _M5 and _M6 have a common DC voltage biases V _B , especially when V _B adopts a gain-enhanced cascode structure, making the node impedance of the active poles of M ₅ and M ₆ lower, so that the sub-pole of this point is at high frequency , so as to obtain a good frequency response. The respective drains of _M5 and _M6 are connected to the active load circuit to form signal amplification as the output terminal of the sense amplifier of the present invention. Active loads generally adopt the current mirror method, especially the cascode structure or gain-enhanced cascode interface can obtain high output impedance and high output gain. The DC bias current of each branch is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; active</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; load</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 3.4</span>}}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 1.2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

为C_B1和C_B2的偏置电流in:

Bias currents for C _B1 and C _B2

为C_B3和C_B4的偏置电流

Bias currents for C _B3 and C _B4

So the bias currents of C _B3 and C _B4 must be large enough to meet the DC bias requirements of the active load.

The bias voltage V _B must be high enough for the cascode transconductance amplifier to work properly. Relative to the power rail V _PS2 , the conditions that V _B needs to meet are:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}<span\; class="notranslate">\; ></span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5,6</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; 3.4</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

in:

V _{GS(M5, 6)} is the gate-source (base-emitter) driving voltage of M ₅ and M ₆

为C_B3，C_B4的最小工作电压

Minimum operating voltage for C _B3 , C _B4

At the same time, the analog output range of the sense amplifier is limited by _V and the active load circuit structure, and its minimum output voltage is limited by _V as:

V _O(min) =V _B -V _TH (5)

in:

V _TH is the threshold voltage of the MOSFET.

(2) Example illustration of the sense amplifier shown in Figure 3a and its typical application in current sensing (Figure 4)

Figure 3a shows an example of a sense amplifier. In Figure 3a, PMOS transistors M ₁₃ , M ₁₄ , and M ₁₅ of the same size are used as the current bias part, and the bias currents are 1uA, M ₁₆ and M ₅ , respectively. M ₆ , M ₇ , and M ₈ are paired to form the bias current sources C _B1 , C _B2 , C _B3 , and C _B4 in Figure 2, where M ₁₆ , M ₅ , and M ₆ have the same size, and M ₇ and M ₈ are equivalent The width-to-length ratio is twice that of M ₁₆ in order to provide a current bias of 1uA for the active load behind; PMOS transistors M ₁ ~ M ₄ correspond to M ₁ ~ M ₄ in Figure 2, all of which have the same size, and the input terminals are vip and vin. NMOS transistors M ₉ and M ₁₀ with the same size constitute M ₅ and M ₆ in Figure 2, and their gate bias is provided by NMOS transistor M _17. The equivalent width ratio of M ₁₇ is 1/12 of M ₁₆ ; the size is the same The PMOS transistors _M11 and _M12 constitute a current mirror load.

The circuit is a single-ended output, the output range is only 0.2V lower than the power supply voltage, and its DC gain is equal to 2g _{m(M2, 3)} × r _o(M12) , where g _{m(M2, 3)} is M ₂ and M ₃ The transconductance, r _o(M12) is the output impedance of M ₁₂ .

Figure 4a is an example of a typical application in current sensing using the amplifier in Figure 3a, where the dotted box s is the same as the amplifier in Figure 3a; the power supply voltage V _DD is 5V, M _SW is the current switch, and M _P1 is the current sense The measuring tube, the ratio of the size of M _P1 to M _SW is 2:10 ⁵ , they are controlled by the driving signal V _DRV , when V _DRV =5V, the current is closed, and when V _DRV =0, the current _IL passes. The quiescent input current of the amplifier is I _B = 2uA, _MP2 is connected to the output of the amplifier and then connected to the negative terminal input vin of the amplifier to form a negative feedback, _MP2 can also make M ₁₁ and M ₁₂ in Figure 3a more symmetrical, when V _DRV =0, force the voltage at both ends of M _P1 and M _SW to be the same, and through the compensation of I _C , the sensed current I _sens is 2/10 ⁵ of I _L , and this current is applied to the filter R _S and C _S The output voltage V _sense is shown in Figure 4b, and the waveform establishment time is less than 50ns, which can meet the needs of high-frequency switching power supply.

(3) Example illustration of the sense amplifier shown in Figure 3b

Figure 3b shows another example of a sense amplifier. The current biasing part based on PMOS transistors M ₁₅ , M ₁₆ , and M ₁₇ of the same size in Figure 3b has a bias current of 1uA, M ₁₈ and M ₅ respectively. , M ₆ , M ₇ , and M ₈ are paired to form the bias current sources C _B1 , C _B2 , C _B3 , and C _B4 in Figure 2, where M ₁₈ , M ₅ , and M ₆ have the same size, and M ₇ and M ₈ , etc. The effective width-to-length ratio is twice that of M ₁₆ in order to provide a current bias of 1uA for the subsequent active load; PMOS transistors M ₁ to M ₄ correspond to M ₁ to M ₄ in Figure 2, and their dimensions are all the same, and the input terminals are respectively vip and vin. NMOS transistors _M9 and _M10 with the same size constitute _M5 and _M6 in Figure 2, and their gate bias is provided by NMOS transistor _M19 . The equivalent width ratio of _M19 is 1/12 of _M18 ; the size is the same The PMOS transistors M ₁₁ and M ₁₂ , M ₁₃ , M _14A and M _14B form a cascode load, and the bias circuit of M _14A and M _14B is 1uA.

The circuit is a single-ended output with a symmetrical structure and a gain of g _{m(M2, 3)} r _o(M12) g _m(m13) r _o(m13) , suitable as a comparator in current detection such as peak current detection, valley value It is used in current detection and zero-crossing detection.

The above shows that the beneficial results of the circuit include:

(a) The common-mode input range is large. In theory, the minimum value of the common-mode input voltage is V _TH +2V _OV . There is no upper limit, and it can reach any high voltage supported by the process, where V _TH is the threshold voltage of the transistor (0.7 V or so), V _OV is its overdrive voltage (analog design generally takes 0.1V ~ 0.2V);

(b), the entire signal flow is input by the source or emitter stage of the differential mode, which reduces the Miller phenomenon, has a fast response speed, and can achieve a large gain-bandwidth product at low power, and the differential mode can make the input DC offset The voltage is less affected by process, supply voltage, and temperature (PVT) drift, which also makes the entire circuit have a strong common-mode rejection capability.

Claims (1)

1. A signal sensing amplifier, used for real-time sensing of the current magnitude of the current channel, or current detection of the current state of the channel, including a differential transconductance input circuit, a differential cascode transconductance amplifier circuit and an active Load circuit; the differential transconductance input circuit is a voltage-to-current differential input stage with a symmetrical structure that can realize a wide common-mode input range, including a branch that generates a differential current composed of transistors M ₁ and M ₂ , and a transistor that generates a differential current M ₃ and M ₄ constitute another branch that generates differential currents. Transistors M ₁ and M ₄ are connected by diodes and provided with DC current bias by current sources C _B1 and C _B2 respectively. M ₁ is connected to the source of M ₃ Together, they constitute one input terminal of the differential input stage, the sources of _M4 and _M2 are connected together to form the other input terminal of the differential input stage, and the drains of transistors _M2 and _M3 serve as the output terminal of the differential current and The input terminals of the next stage are connected; the differential cascode transconductance amplifier circuit includes transistors _M5 and M6 of the same type and size, and current sources C _B3 and _{C B4 are} respectively connected to the sources of transistors _M5 and _M6 And provide a DC current bias, this connection point is used as the differential current input terminal of this stage, the transistor _M5 and _M6 gates have a common DC voltage bias V _B , the respective drains of _M5 and _M6 are connected to the active load The circuits are connected to form signal amplification as the output terminal of the sense amplifier; the transistors M ₁ , M ₂ , M ₃ , and M ₄ are transistors of the same type; the transistors M ₁ and M ₄ have the same size, and the transistors M ₂ and M ₃ are the same size.

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