CN101833523B - Data access method - Google Patents

Abstract

The invention discloses a data access method, which can effectively solve the problem of mutual data access between computer interface devices by adopting the method of direct transmission or direct reading for data access between master-end controllers. The data must be temporarily stored in the memory, which causes a waste of time, and effectively improves the efficiency of data access.

Description

data access method

technical field

The invention relates to a data access method, in particular to a direct data access method between master-end controllers.

Background technique

So far, most of the data access between computer interface devices depends on the central processing unit (CPU) or microprocessor (MCU) to communicate with the host controller (Hostcontroller) through the host bridge (HostBridge). However, the way of communication between the central processing unit and the host controller not only increases the load on the central processing unit itself, but also reduces the efficiency of data access between computer interface devices.

Please refer to FIG. 1 for a schematic diagram of a circuit between a traditional central processing unit, a main end bridge and an interface device. Generally speaking, the host controllers 110 and 120 have a direct memory access (DMA) function, that is, when the data of the interface device A is to be moved to the interface device B, the host controller 110 can first The data of the interface device A is moved to the local system memory (local system memory) 130 through the memory controller 125 , and then the data of the interface device A temporarily stored in the memory 130 is moved to the interface device B by the master controller 120 .

In this DMA mode, the central processing unit 140 only needs to initialize the master controllers 110, 120 and prepare some work instructions for the master controllers 110, 120, and the master controllers 110, 120 can start to transfer the interface device A The data is moved to the work of the interface device B. And when the main-end controllers 110, 120 complete the assigned work, the main-end controllers 110, 120 will notify the central processing unit 140 to wait for the next job. Therefore, the central processing unit 140 can directly access the local system memory 130 through the master controllers 110 and 120 in the DMA mode to reduce the load on its use.

However, the data access process of this DMA mode does have its shortcomings. Taking FIG. 1 as an example, when the data of the interface device A must be moved to the interface device B, the central processing unit 140 needs to arrange the master end bridge 150 After the end controller 110 first moves the data of the interface device A to the space in the memory 130 through the memory controller 125, the central processing unit 140 then arranges the master end controller 120 to transfer the data temporarily stored in the memory 130 through the master end bridge 150 The data of the interface device A is transferred to the interface device B through the memory controller 125 .

The above-mentioned data processing flow will waste a lot of time in moving data to the memory and moving data out of the memory. Jointly, if the memory is in a very busy state, this includes the central processing unit, the main end bridge, The system composed of the host controller, the memory and the interface devices will become very slow in data access operation, that is, the data access efficiency will be low.

In view of this, the present invention proposes a data access method, which can effectively solve the problem that when computer interface devices want to access data from each other, the data must first be temporarily stored in the memory and cause a waste of time, so as to effectively improve the data access time. s efficiency.

Contents of the invention

The main purpose of the present invention is to solve the problem that the data must be temporarily stored in the memory when the computer interface devices want to access each other's data. In order to achieve the purpose of the present invention, the present invention proposes a data access method, which is characterized in that: the data temporarily stored in the first master-end controller is directly transmitted to the second master-end controller.

In a preferred embodiment of the present invention, the method includes operation modes such as initial state, programming state and transmission state.

The initial state includes that the central processing unit programs an arithmetic register in the first master controller to ensure normal operation of the first master controller.

The programming state can include that when the data needs to be transmitted from the first master controller to the second master controller, the central processing unit can program the operation register to set the length of the data, the type of the data, and the starting address of the data , the status of the first master controller, etc.

The transfer status also includes a single-master write situation, a single-master read situation, a two-master write situation, and a two-master read situation.

The single master writing condition mainly includes that when data needs to be transmitted from the first master controller to the second master controller, the first master controller sends a master cycle signal to read and confirm the second master controller’s Transfer status to determine whether to actively transfer data.

The single master read condition mainly includes when the data needs to be transmitted from the first master controller to the second master controller, the direct memory access function of the second master controller is activated, and the second master controller sends a master The periodic signal is used to read the transmission status of the first master-end controller to determine whether to actively access the data temporarily stored by the first master-end controller.

In the two-master writing condition, when the data needs to be transmitted from the first master controller to the second master controller, a direct memory access function of the first master controller and the second master controller is activated at the same time, A master cycle signal is sent by the second master controller to notify the first master controller of the transmission status of the second master controller, so as to determine whether the first master controller can start to transmit data.

The two-master read condition includes simultaneously enabling a DMA function of the first master controller and the second master controller when data needs to be transferred from the first master controller to the second master controller , the first master controller sends a master period signal to notify the second master controller of the transmission status of the first master controller, so as to determine whether the second master controller can start to read data.

In order to further understand the characteristics, purpose and functions of the present invention, the present invention will be described in detail below in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is a schematic circuit diagram between a conventional central processing unit, a main end bridge and an interface device;

FIG. 2A is a schematic diagram of a data access method in a preferred embodiment of the present invention;

2B is a schematic diagram of a data access method in an initial state operating mode in a preferred embodiment of the present invention;

FIG. 2C is a schematic diagram of a data access method in a programmed state operating mode according to a preferred embodiment of the present invention;

2D is a schematic diagram of the operation mode of the data access method in a single write transfer state according to a preferred embodiment of the present invention;

FIG. 2E is a schematic diagram of the operation mode of the data access method in a single master read transfer state according to a preferred embodiment of the present invention.

Description of reference numerals: 110, 120 master controller; 125 memory controller; 130 regional system memory; 140 central processing unit; 150 master bridge; 213, 223 arithmetic register; 215, 225 transmission state; data buffer.

detailed description

Please refer to FIG. 2 which is a schematic diagram of a data access method according to a preferred embodiment of the present invention. In FIG. 2A , the present invention mainly changes the data access method between the main-end controller 110 and the main-end controller 120 on the current motherboard, and instead uses the data between the main-end controller 110 and the main-end controller 120 to be able to direct access. In other words, data between the external buses 230 and 240 respectively coupled between the host controller 110 and the host controller 120 can be directly accessed.

The data access method between the host controller 110 and the host controller 120 of the present invention can be divided into several operation modes, such as initial state, programming state, and transmission state.

Please refer to FIG. 2B , which is a schematic diagram of the data access method in the initial state operation mode of the preferred embodiment of the present invention. During the initial state, the central processing unit 140 programs the operation register 213 of the host controller 110 to ensure that the host controller 110 can operate normally. For example, the central processing unit 140 programs the operation register 213 so that the operation register 213 activates some functions of the master-side register, such as start, suspend, restart, stop and so on. Assuming that the central processing unit 140 intends to program the operation register 213 to enable the direct memory access function (DMA), the central processing unit 140 sends a main cycle signal of the DMA function to the operation register 213 .

And when there is data to be transmitted from the host controller 110 to the host controller 120, the operation mode of the programming state is entered. Please refer to FIG. 2C , which is a schematic diagram of the data access method in the programmed state operation mode of the preferred embodiment of the present invention. The central processing unit 140 programs the arithmetic register 213 of the master-end controller 110 to set the length, type, start address, state of the master-end controller, etc. of the data to be transmitted, that is, to establish the transmission of the master-end controller 110 Status 215. That is, the host controller 110 can establish the transfer state 215 corresponding to the host controller 120 .

In a preferred embodiment of the present invention, the transmission status of the data access method includes a single main write situation, a single main read situation, a double main write situation and a double main read situation. Please refer to FIG. 2D , which is a schematic diagram of the operation mode of the data access method in the single write transfer state of the preferred embodiment of the present invention. When data needs to be transmitted from the master controller 110 to the master controller 120 , the master controller 110 sends a master cycle signal to read and confirm the transmission status 225 of the master controller 120 to determine whether to actively transmit data. Of course, the transmission status 225 of the master controller 120 includes the capacity of the transmission data buffer 227 of the master controller 120 , the capacity status of the transmission data buffer 227 , the start address of the transmission data buffer 227 and the like.

If the transmission state of the master controller 120 belongs to the ready-to-transmit state, the master controller 110 prepares to transmit the data of the external bus 230 from its own transfer data buffer 217 to the transfer data buffer 227 of the master controller 120 . And when the host controller 120 receives the data, the host controller 120 moves the data from the transmission data buffer 227 to the external bus 240 corresponding to the host controller 120 to complete the data transmission.

In addition, after the data transmission is completed, the master-end controller 110 and the master-end controller 120 automatically update their internal transmission status, and as required, the master-end controller 110 can also update the master-end The transmission status of the controller 120.

If the transmission status 225 of the master controller 120 is a state where the capacity of the transmission buffer 227 is insufficient, the master controller 110 may choose to transmit the data to the transmission data buffer 227 of the master controller 120 in a divided manner. And the host controller 110 can continuously transmit data to the host controller 120 when the external bus 230 is ready for the next data transmission.

On the contrary, if the transmission status 225 of the host controller 120 is not ready for transmission, the host controller 110 reads and confirms the transmission status 225 of the host controller 120 again later.

Please continue to refer to FIG. 2E , which is a schematic diagram of the operation mode of the data access method in the single master read transfer state of the preferred embodiment of the present invention. The way of data transmission, in addition to using the master controller 110 to actively transmit data to the master controller 120 in the single master write transfer state, there is also a single master controller 120 that actively reads data from the master controller 110. The mode of operation in which the master reads the status of the transfer.

When the data still needs to be transmitted from the master controller 110 to the master controller 120, the central processing unit 140 starts the direct memory access function of the master controller 120, and the master controller 120 sends a master cycle signal to read the master The transmission status 215 of the controller 110 is used to determine whether to actively access the data temporarily stored by the master controller 110 .

If the transmission status 215 of the master-end controller 110 is ready to transmit and the capacity of the transmission data buffer 227 of the master-end controller 120 is a sufficient state, then the master-end controller 120 reads the data temporarily stored in the master-end controller 110 The data. Similarly, if the transmission data buffer 227 of the master-end controller 120 is in a state of insufficient capacity, the master-end controller 120 can still choose to read data from the master-end controller 110 in batches in a split manner. Moreover, the host controller 120 can continue to read data from the host controller 110 when the transmit data buffer 227 has space.

On the contrary, if the transmission state of the main-end controller 110 is not yet ready for transmission, the main-end controller 120 confirms the transmission state 215 of the main-end controller 110 again later.

And when the master-end controller 120 reads the data temporarily stored in the master-end controller 110 and the reading is completed, both the master-end controller 110 and the master-end controller 120 automatically update their internal transmission states 215, 225, and as required, The host controller 120 can also update the transmission status 215 of the host controller 110 according to the state of the contents of the operation register 223 .

The biggest difference between the operation mode of the two masters writing the transfer state and the operation mode of the aforementioned transfer state is that when the data needs to be transmitted from the master controller 110 to the master controller 120, the master controller 110 and the master controller are started at the same time. The direct memory access function of the end controller 120, and the master cycle signal is sent by the master controller 120 to notify the master controller 110 of the transfer status 225 of the master controller 120, so as to determine whether the master controller 110 starts active transmit data to the host controller 120 .

The operation mode of the two masters reading the transfer state is just opposite to the operation mode of the two masters writing the transfer state. When the data needs to be transmitted from the master controller 110 to the master controller 120, the master controller 110 is started at the same time. And in the case of the direct memory access function of the master controller 120, the master cycle signal is sent by the master controller 110 to notify the master controller 120 of the transmission status of the master controller 110, so as to determine whether the master controller 120 Start to actively read the data of the master controller 110 .

According to the concept of the data access method of the present invention, that is, the data exchange between the master-side controllers 110 and 220 is directly transmitted. Therefore, extending the operation mode of the aforementioned transmission state, an operation mode with mixed direct read and write transmission states is also proposed. That is, when the data needs to go back and forth between the master controller 110 and the master controller 120, the direct memory access functions of the master controller 110 and the master controller 120 are activated at the same time, and the data is actively transferred from the source of the data Transfer to the destination of the data, or actively read the data from the destination of the data to the source of the data.

To sum up the above, the present invention proposes a data access method, which can effectively solve the problem of mutual data access between computer interface devices by adopting a direct transmission or direct reading method for data access between master-end controllers. , the data must first be temporarily stored in the memory, resulting in the problem of wasting time, and effectively improving the efficiency of data access.

The above descriptions are only preferred embodiments of the present invention, and should not limit the scope of the present invention. Therefore, all equivalent changes and modifications made according to the claims of the present invention will still not lose the gist of the present invention, nor depart from the spirit and scope of the present invention, and all should be regarded as further implementations of the present invention.

Claims (9)

1. a data access method, is characterized in that:

By in the first main side controller the data of keeping in directly transfer in the second main side controller;

Wherein also comprise the operator scheme of an original state, a unprogrammed state and a transmission state; And

Wherein at this unprogrammed state, when these data need transfer to this second main side controller by this first main side controller, the arithmetic register of this first main side controller of CPU (central processing unit) programmable, to set length, the kind of these data, the start address of these data, the state of this first main side controller of these data;

Wherein this first main side controller goes to set to should the transmission state of this first main side controller of the second main side controller according to the setting of this arithmetic register;

Wherein this transmission state also comprises single main write situation, single main reading situation, two main write situations and two main reading situations.

2. data access method as claimed in claim 1, wherein this original state comprises:

An arithmetic register in one CPU (central processing unit) sequencing first main side controller, to guarantee this first main side controller normal operation.

3. data access method as claimed in claim 2, wherein this CPU (central processing unit) can make this arithmetic register come into operation and postpone, restarts, stops the partial function of this first main side controller.

4. data access method as claimed in claim 1, wherein when this CPU (central processing unit) is for sequencing one direct memory access (DMA) function, this CPU (central processing unit) then sends a dominant period signal of this direct memory access (DMA) function to this arithmetic register.

5. data access method as claimed in claim 1, wherein this single main write situation comprises:

When these data need transfer to this second main side controller by this first main side controller, this first main side controller sends dominant period signal, to read and to confirm the transmission state of this second main side controller, to determine whether these data of active transmission.

6. data access method as claimed in claim 1, wherein this single main reading situation comprises:

When these data need transfer to this second main side controller by this first main side controller, start the direct memory access (DMA) function of this second main side controller, and this second main side controller sends the transmission state that a dominant period signal removes to read this first main side controller, with determine to make no initiatively access this first main side controller this data of keeping in.

7. data access method as claimed in claim 1, wherein this two main write situation comprises:

When these data need transfer to this second main side controller by this first main side controller, start the function of the direct memory access (DMA) of this first main side controller and this second main side controller simultaneously, dominant period signal is sent by this second main side controller, to notify the transmission state of this this second main side controller of the first main side controller, to determine whether this first main side controller can start to transmit this data.

8. data access method as claimed in claim 1, wherein this two main reading situation comprises:

When these data need transfer to this second main side controller by this first main side controller, start the function of a direct memory access (DMA) of this first main side controller and this second main side controller simultaneously, a dominant period signal is sent to notify the transmission state of this this first main side controller of the second main side controller, to determine whether this second main side controller can start to read this data by this first main side controller.

9. data access method as claimed in claim 1, also comprise a mixing direct read/write situation, this mixing direct read/write situation is:

When these data need come and go between this first main side controller and this second main side controller, start the function of the direct memory access (DMA) of this first main side controller and this second main side controller simultaneously, and in initiatively these data being transmitted the destination of these data by the source place of these data and initiatively being read between these data by destination to the source place of these data of these data and select one.