CN101848033B - Dual-rate receiving device - Google Patents
Dual-rate receiving device Download PDFInfo
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- CN101848033B CN101848033B CN201010157995.4A CN201010157995A CN101848033B CN 101848033 B CN101848033 B CN 101848033B CN 201010157995 A CN201010157995 A CN 201010157995A CN 101848033 B CN101848033 B CN 101848033B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/693—Arrangements for optimizing the preamplifier in the receiver
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Abstract
The invention discloses a dual-rate receiving device, which is suitable for a photoelectric module. The dual-rate receiving device comprises a dual-rate optical receiving component, a channel switching circuit, a low-rate limiting amplifier data path and a high-rate limiting amplifier data path, wherein the dual-rate optical receiving component further comprises an optical detector and a dual-rate trans-impedance amplifier; the channel switching circuit further comprises a first controllable switch, a second controllable switch, a third controllable switch and a fourth controllable switch; the low-rate limiting amplifier data path further comprises a low-rate limiting amplifier; and the high-rate limiting amplifier data path further comprises a high-rate limiting amplifier. Through the technical scheme of the invention, the optical receiving component works at an optimal rate and can select the limiting amplifier data path working at a corresponding rate at the same time so as to realize high sensitivity.
Description
Technical field
The present invention relates to the optical communication technique field, relate in particular to a kind of dual-rate receiving device.
Background technology
Optical communication equipment will be operated under the multiple operating rate usually, just requires optical-electric module to need can be operated under the multiple speed, thereby brings difficulty for actual circuit design.For compatible rate applications, so the device of optical-electric module need satisfy the requirement of two-forty wide bandwidth, but often sensitivity index is unsatisfactory when the device of two-forty and wide bandwidth is operated in low rate following time.
This contradiction is particularly outstanding in the dual rate receiver of ten thousand mbit ethernet passive optical network optical line terminal optical-electric modules; For the existing gigabit ethernet passive optical network device of optical network unit of compatibility, in ten thousand mbit ethernet passive optical network optical line terminal optical-electric modules, need to receive 10.3125Gbps and 1.25Gbps burst luminous signal.If the operation of receiver design optimization under the high speed of 10.3125Gbps, in the receiving sensitivity of 1.25Gbps with deterioration, otherwise then the two-forty receiver performance can't guarantee.
And operation of receiver the burst operating state under, dual rate optical fiber receive module and follow-up signal amplification circuit need be realized the conversion to burst in less than the time of 400ns, mode of operation is like this brought difficulty to parts selection.The bandwidth commutation circuit of bussiness class trans-impedance amplifier and limiting amplifier chip all can not satisfy the requirement that 400ns speed is switched.
Summary of the invention
The objective of the invention is to propose a kind of dual-rate receiving device, make when optical fiber receive module is operated under the most suitable speed, can select the limiting amplifier data path of corresponding operating rate, thereby realize high sensitivity.
For reaching this purpose, the present invention adopts following technical scheme:
A kind of dual-rate receiving device; Be applicable in the optical-electric module; Comprise dual rate optical fiber receive module, channel switching circuit, low speed limiting amplifier data path and high speed limiting amplifier data path, the dual rate optical fiber receive module further comprises photo-detector and dual rate trans-impedance amplifier, and channel switching circuit further comprises first controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch; Low speed limiting amplifier data path further comprises the low speed limiting amplifier; High speed limiting amplifier data path further comprises the high speed limiting amplifier, wherein
The output of photo-detector is connected with the input of dual rate trans-impedance amplifier, is used for the light signal that receives is transformed into photoelectric current, and delivers to the dual rate trans-impedance amplifier;
The output of dual rate trans-impedance amplifier is connected with the input of first controllable switch, the input of second controllable switch, the input of the 3rd controllable switch and the input of the 4th controllable switch respectively; Be used to produce differential data signals; The data anode of differential data signals is connected with the input of first controllable switch and the input of second controllable switch respectively, and the data negative terminal of differential data signals is connected with the input of the 3rd controllable switch and the input of the 4th controllable switch respectively;
The output of first controllable switch is connected with the data positive input terminal of low speed limiting amplifier;
The output of second controllable switch is connected with the data positive input terminal of high speed limiting amplifier;
The output of the 3rd controllable switch is connected with the data minus input of low speed limiting amplifier;
The output of the 4th controllable switch is connected with the data minus input of high speed limiting amplifier; The output of the output of low speed limiting amplifier and high speed limiting amplifier is connected with system host respectively, is used for delivering to system host respectively after the differential data signals amplification that receives separately;
The control end of the control end of the control end of the control end of first controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch is connected respectively with system host; Be used for obtaining the rate selection control signal, control the closed or disconnection of first controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch from system host.
Low speed limiting amplifier data path also comprises low-pass filter circuit, and the output of first controllable switch is connected with the data positive input terminal of low-pass filter circuit, and the output of the 3rd controllable switch is connected with the data positive input terminal of low-pass filter circuit;
The output of low-pass filter circuit is connected with the input of low speed limiting amplifier, is used for the high-frequency noise of filtering dual rate trans-impedance amplifier.
Channel switching circuit also comprises first ac coupling capacitor and second ac coupling capacitor; The data anode of the differential data signals of dual rate trans-impedance amplifier output is connected with the input of first ac coupling capacitor; The input of the input of first controllable switch and second controllable switch links together and is connected with the output of first ac coupling capacitor, is used to isolate the data anode DC operation level of dual rate trans-impedance amplifier and high speed limiting amplifier data path and low speed limiting amplifier data path;
The data negative terminal of the differential data signals of dual rate trans-impedance amplifier output is connected with the input of second ac coupling capacitor; The input of the input of the 3rd controllable switch and the 4th controllable switch links together and is connected with the output of second ac coupling capacitor, is used to isolate the data negative terminal DC operation level of dual rate trans-impedance amplifier and high speed limiting amplifier data path and low speed limiting amplifier data path.
Also comprise bias voltage circuit, the output of bias voltage circuit is connected with the input of photo-detector, is used to produce the required bias voltage of photo-detector.
Photo-detector is PIN photodiode or avalanche photodide.
Bias voltage circuit is PIN photodiode bias voltage circuit or bias voltage of avalanche photodiode circuit.
In the technique scheme; Revise through proper technique; Between dual rate optical fiber receive module and the channel switching circuit, between channel switching circuit and the low speed limiting amplifier data path, between channel switching circuit and the high speed limiting amplifier data path; And is connected through direct-current coupling or AC coupled between the data of optical-electric module output and the system host, connect the connection of employing differential mode.
As the application of technique scheme in the dual rate receiver of ten thousand mbit ethernet EPONs; The dual rate trans-impedance amplifier is the 10G/1.25G trans-impedance amplifier; The low speed limiting amplifier is the 1.25G limiting amplifier, and the high speed limiting amplifier is the 10G limiting amplifier.
Adopted technical scheme of the present invention, under the control of rate selection control signal, carried out different limiting amplifier data paths and switch, the low speed of selection and high speed limiting amplifier are ripe devices, low price, and it is convenient to realize, and receptivity is good.
Description of drawings
Fig. 1 is the structural representation of a kind of dual-rate receiving device of the present invention.
Fig. 2 is the structural representation of a kind of dual-rate receiving device in the specific embodiment of the invention.
Embodiment
Further specify technical scheme of the present invention below in conjunction with accompanying drawing and through embodiment.
Fig. 1 is the structural representation of a kind of dual-rate receiving device of the present invention.As shown in Figure 1, a kind of dual-rate receiving device is arranged in optical-electric module, comprises U1 dual rate optical fiber receive module, U2 channel switching circuit, U3 low speed limiting amplifier data path and U4 high speed limiting amplifier data path.
Between dual rate optical fiber receive module and the channel switching circuit, between channel switching circuit and the low speed limiting amplifier data path, between channel switching circuit and the high speed limiting amplifier data path; And is connected through direct-current coupling or AC coupled between the data of optical-electric module output and the system host, connect the connection of employing differential mode.
Wherein the dual rate optical fiber receive module further comprises U11 photo-detector and U12 dual rate trans-impedance amplifier; Channel switching circuit further comprises K1 first controllable switch, K2 second controllable switch, K3 the 3rd controllable switch and K4 the 4th controllable switch; Low speed limiting amplifier data path further comprises U32 low speed limiting amplifier, and high speed limiting amplifier data path further comprises U41 high speed limiting amplifier.
Concrete annexation is following:
Photo-detector is PIN photodiode or avalanche photodide, and the output of photo-detector is connected with the input of dual rate trans-impedance amplifier, and photo-detector is transformed into photoelectric current with the light signal that receives, and delivers to the dual rate trans-impedance amplifier.
The output of dual rate trans-impedance amplifier is connected with the input of first controllable switch, the input of second controllable switch, the input of the 3rd controllable switch and the input of the 4th controllable switch respectively; The dual rate trans-impedance amplifier produces differential data signals; The data anode of differential data signals is connected with the input of first controllable switch and the input of second controllable switch respectively, and the data negative terminal of differential data signals is connected with the input of the 3rd controllable switch and the input of the 4th controllable switch respectively.
The output of first controllable switch is connected with the data positive input terminal of low speed limiting amplifier.
The output of second controllable switch is connected with the data positive input terminal of high speed limiting amplifier.
The output of the 3rd controllable switch is connected with the data minus input of low speed limiting amplifier.
The output of the 4th controllable switch is connected with the data minus input of high speed limiting amplifier.
The output of the output of low speed limiting amplifier and high speed limiting amplifier is connected with system host respectively, and the differential data signals that low speed limiting amplifier and high speed limiting amplifier will receive is separately delivered to system host respectively after amplifying.
The control end of the control end of the control end of the control end of first controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch is connected respectively with system host; First controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch obtain the rate selection control signal from system host, control the closed or disconnection of first controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch.
Low speed limiting amplifier data path can also comprise the U31 low-pass filter circuit in addition; The output of first controllable switch is connected with the data positive input terminal of low-pass filter circuit; The output of the 3rd controllable switch is connected with the data minus input of low-pass filter circuit; The output of low-pass filter circuit is connected with the input of low speed limiting amplifier, and the high-frequency noise that low-pass filter circuit can filtering dual rate trans-impedance amplifier is to improve receiving circuit sensitivity.
Fig. 2 is the structural representation of a kind of dual-rate receiving device in the specific embodiment of the invention.As shown in Figure 2, in this dual-rate receiving device, before photo-detector, also comprise bias voltage circuit, the output of bias voltage circuit is connected with the input of photo-detector, can produce the required bias voltage of photo-detector.
Bias voltage circuit is PIN photodiode bias voltage circuit or bias voltage of avalanche photodiode circuit, is used to produce PIN photodiode or the required bias voltage of avalanche photodide.
U1 dual rate optical fiber receive module is a 10G/1.25G dual rate optical fiber receive module; Comprise U11 avalanche photo diode (APD) and U12 10G/1.25G trans-impedance amplifier, 10G/1.25G dual rate optical fiber receive module characteristic is can be operated under the speed of 1.25Gbps and 10Gbps.
The U2 channel switching circuit comprises K1 first controllable switch, K2 second controllable switch, K3 the 3rd controllable switch and K4 the 4th controllable switch, also comprises C1 first ac coupling capacitor and C2 second ac coupling capacitor.
The data anode of the differential data signals of dual rate trans-impedance amplifier output is connected with the input of first ac coupling capacitor; The input of the input of first controllable switch and second controllable switch links together and is connected with the output of first ac coupling capacitor, can isolate the data anode DC operation level of dual rate trans-impedance amplifier and high speed limiting amplifier data path and low speed limiting amplifier data path; The data negative terminal of the differential data signals of dual rate trans-impedance amplifier output is connected with the input of second ac coupling capacitor; The input of the input of the 3rd controllable switch and the 4th controllable switch links together and is connected with the output of second ac coupling capacitor, can isolate the data negative terminal DC operation level of dual rate trans-impedance amplifier and high speed limiting amplifier data path and low speed limiting amplifier data path.
In order to realize receiving and guaranteeing less than the bursty data of 400ns the data path of 10G speed, K1 first controllable switch, K2 second controllable switch, K3 the 3rd controllable switch and K4 the 4th controllable switch must satisfy high bandwidth (analog bandwidth is greater than 7GHZ) and respond (switch closure is opened the time less than 400ns) condition fast.
The U2 channel switching circuit is accepted the control of the rate selection control signal of system host transmission, realizes the switching of 10G and 1.25G data channel.
U3 low speed limiting amplifier data path is a 1.25G limiting amplifier data path, comprises U31 low-pass filter circuit and U32 1.25G limiting amplifier.
U31 low pass filter three dB bandwidth is arranged on about 800MhZ～1GHZ, is used for filter away high frequency noise.
10G limiting amplifier data path comprises U41 10G limiting amplifier during U4 high speed limiting amplifier data path.
The rate selection control signal is produced by system host, and the data path that is used for the control channel commutation circuit switches, and receiving circuit has two pairs of differential datas of 1.25G and 10G data path to link to each other with system host.
Following mask body is introduced the workflow of this dual-rate receiving device:
The bias voltage of avalanche photodiode circuit links to each other with the U11 avalanche photodide, for the U11 avalanche photodide provides bias voltage.
The U11 avalanche photodide is transformed into photoelectric current with the light signal that receives, and photo-signal is delivered in the U12 10G/1.25G trans-impedance amplifier.
U12 10G/1.25G trans-impedance amplifier changes the photo-signal that receives into the voltage signal of difference.
The data anode (Data+) of the differential data signals of U12 10G/1G trans-impedance amplifier output links to each other with C1 first ac coupling capacitor; The input of K1 first controllable switch and K2 second controllable switch links together and forms the 1st group of switch and link to each other with C1 first ac coupling capacitor; The output of K1 first controllable switch and the data of U31 low-pass filter circuit just (Data+) input are connected, and the data of the output of K2 second controllable switch and U41 10G limiting amplifier just (Data+) input are connected.
The data negative terminal (Data-) of the differential data signals of U12 10G/1G trans-impedance amplifier output links to each other with C2 second ac coupling capacitor; The input of K3 the 3rd controllable switch and K4 the 4th controllable switch links together and forms the 2nd group of switch and link to each other with C2 second ac coupling capacitor; The output of K3 the 3rd controllable switch is connected with data minus (Data-) input of U31 low-pass filter circuit, and the output of K4 the 4th controllable switch is connected with data minus (Data-) input of U41 10G limiting amplifier.
K1 first controllable switch, K2 second controllable switch, K3 the 3rd controllable switch and the control end of K4 the 4th controllable switch link to each other with system host, and the rate controlled that the receiving system main frame sends is selected signal.
The rate selection control signal that produces when system host is that high speed limit is when putting amplifier data path gating; K2 second controllable switch and K4 the 4th controllable switch are closed; And K1 first controllable switch and K3 the 3rd controllable switch break off, and the differential data signals that U12 dual rate trans-impedance amplifier produces is delivered to system host after amplifying through U41 high speed limiting amplifier.
When the rate selection control signal of system host generation is put amplifier data path gating for low speed limit; K1 first controllable switch and K3 the 3rd controllable switch are closed; And K2 second controllable switch and K4 the 4th controllable switch break off; The differential data signals that U12 dual rate trans-impedance amplifier produces is delivered to system host through the filtering of U31 low pass filter after the amplification of U32 low speed limiting amplifier; Wherein the output of U31 low-pass filter circuit links to each other filter away high frequency noise through difference direct-current coupling mode with U32 low speed limiting amplifier.
The above; Be merely the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with this technological people in the technical scope that the present invention disclosed; The variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (8)
1. dual-rate receiving device; Be applicable to it is characterized in that in the optical-electric module, comprise dual rate optical fiber receive module, channel switching circuit, low speed limiting amplifier data path and high speed limiting amplifier data path; The dual rate optical fiber receive module further comprises photo-detector and dual rate trans-impedance amplifier; Channel switching circuit further comprises first controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch, and low speed limiting amplifier data path further comprises the low speed limiting amplifier, and high speed limiting amplifier data path further comprises the high speed limiting amplifier; Wherein
The output of photo-detector is connected with the input of dual rate trans-impedance amplifier, is used for the light signal that receives is transformed into photoelectric current, and delivers to the dual rate trans-impedance amplifier;
The output of dual rate trans-impedance amplifier is connected with the input of first controllable switch, the input of second controllable switch, the input of the 3rd controllable switch and the input of the 4th controllable switch respectively; Be used to produce differential data signals; The data anode of differential data signals is connected with the input of first controllable switch and the input of second controllable switch respectively, and the data negative terminal of differential data signals is connected with the input of the 3rd controllable switch and the input of the 4th controllable switch respectively;
The output of first controllable switch is connected with the data positive input terminal of low speed limiting amplifier;
The output of second controllable switch is connected with the data positive input terminal of high speed limiting amplifier;
The output of the 3rd controllable switch is connected with the data minus input of low speed limiting amplifier;
The output of the 4th controllable switch is connected with the data minus input of high speed limiting amplifier;
The output of the output of low speed limiting amplifier and high speed limiting amplifier is connected with system host respectively, is used for delivering to system host respectively after the differential data signals amplification that receives separately;
The control end of the control end of the control end of the control end of first controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch is connected respectively with system host; Be used for obtaining the rate selection control signal, control the closed or disconnection of first controllable switch, second controllable switch, the 3rd controllable switch and the 4th controllable switch from system host.
2. a kind of dual-rate receiving device according to claim 1; It is characterized in that; Low speed limiting amplifier data path also comprises low-pass filter circuit; The output of first controllable switch is connected with the data positive input terminal of low-pass filter circuit, and the output of the 3rd controllable switch is connected with the data minus input of low-pass filter circuit;
The output of low-pass filter circuit is connected with the input of low speed limiting amplifier, is used for the high-frequency noise of filtering dual rate trans-impedance amplifier.
3. a kind of dual-rate receiving device according to claim 1; It is characterized in that; Channel switching circuit also comprises first ac coupling capacitor and second ac coupling capacitor; The data anode of the differential data signals of dual rate trans-impedance amplifier output is connected with the input of first ac coupling capacitor; The input of the input of first controllable switch and second controllable switch links together and is connected with the output of first ac coupling capacitor, is used to isolate the data anode DC operation level of dual rate trans-impedance amplifier and high speed limiting amplifier data path and low speed limiting amplifier data path;
The data negative terminal of the differential data signals of dual rate trans-impedance amplifier output is connected with the input of second ac coupling capacitor; The input of the input of the 3rd controllable switch and the 4th controllable switch links together and is connected with the output of second ac coupling capacitor, is used to isolate the data negative terminal DC operation level of dual rate trans-impedance amplifier and high speed limiting amplifier data path and low speed limiting amplifier data path.
4. a kind of dual-rate receiving device according to claim 1 is characterized in that, also comprises bias voltage circuit, and the output of bias voltage circuit is connected with the input of photo-detector, is used to produce the required bias voltage of photo-detector.
5. a kind of dual-rate receiving device according to claim 1 is characterized in that, photo-detector is PIN photodiode or avalanche photodide.
6. a kind of dual-rate receiving device according to claim 4 is characterized in that, bias voltage circuit is PIN photodiode biasing circuit or bias voltage of avalanche photodiode circuit.
7. a kind of dual-rate receiving device according to claim 1; It is characterized in that; Between dual rate optical fiber receive module and the channel switching circuit, between channel switching circuit and the low speed limiting amplifier data path, between channel switching circuit and the high speed limiting amplifier data path; And is connected through direct-current coupling or AC coupled between the data of optical-electric module output and the system host, connect the connection of employing differential mode.
8. a kind of dual-rate receiving device according to claim 1 is characterized in that, the dual rate trans-impedance amplifier is the 10G/1.25G trans-impedance amplifier, and the low speed limiting amplifier is the 1.25G limiting amplifier, and the high speed limiting amplifier is the 10G limiting amplifier.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010157995.4A CN101848033B (en) | 2010-04-28 | 2010-04-28 | Dual-rate receiving device |
| PCT/CN2010/075793 WO2011134213A1 (en) | 2010-04-28 | 2010-08-09 | Dual rate receiving device |
| US12/867,621 US8331801B2 (en) | 2010-04-28 | 2010-08-09 | Dual rate receiving device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010157995.4A CN101848033B (en) | 2010-04-28 | 2010-04-28 | Dual-rate receiving device |
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| CN101848033A CN101848033A (en) | 2010-09-29 |
| CN101848033B true CN101848033B (en) | 2012-11-14 |
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| US (1) | US8331801B2 (en) |
| CN (1) | CN101848033B (en) |
| WO (1) | WO2011134213A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2011134213A1 (en) | 2011-11-03 |
| US8331801B2 (en) | 2012-12-11 |
| CN101848033A (en) | 2010-09-29 |
| US20110293283A1 (en) | 2011-12-01 |
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