CN101877542A - Bit reverse method for Fourier transformation processing of data of frequency converter - Google Patents
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Abstract
The invention provides a bit reverse method for Fourier transformation processing of data of a frequency converter, which comprises the following steps of: S1) determining a loop body output by bit reverse; S2) finishing the bit reverse process by taking an initial value j<initial value> of a first loop as 0 and an advanced j<initial value> of a next loop as j<initial value>+4 under the loop condition that (j<final value>+1) is less than N/2 according to the loop body determined by the S1), wherein N is the number of sampling points of sampled data, and j<final value> refers to the value of j after each loop is finished; and S3) sequentially obtaining the bit reverse values A(N/2)-A(N-1) according to the bit reverse values A(0)-A(N/2-1) obtained by the S2) and a formula A(j+N/2)=A(j)+1. The method has the advantages of wide application and capability of reducing development cost.
Description
Technical field
The present invention relates to the signal processing field, particularly relate to FFT (fast fourier transform) process field of signal.
Background technology
In applications such as electric power, electronics, image, sound and Video processing, after time-domain signal gathered, in order to obtain the frequency spectrum of signal, usually all to carry out FFT (Fast Fourier Transform, fast fourier transform), thus can carry out data processing and signal Essential Analysis such as spectrum analysis, digital filtering, harmonic analysis targetedly to signal.And in the various algorithms of fast fourier transform, " bit-reversed " all is primary and necessary step, promptly the signal after input signal process collection pre-process and the analog-to-digital conversion is carried out step-by-step negate ordering, for the butterfly computation in the FFT computing provides initialization, therefore " bit-reversed algorithm " has very application fields and practical significance.
Through inquiry and practical study, " the bit-reversed algorithm " when having the data of frequency converter Fourier transform processing now in its fft algorithm lacking on the versatility this point relatively: do not have similar algorithm to propose as yet in Patent Office of the People's Republic of China's document inquiry; At home and abroad in the list of references, do not inquire as yet based on this a part of document of bit-reversed general-purpose algorithm; At home, mainly sampling number in the realization of bit-reversed at known signal, then according to this and the bit-reversed program that step-by-step is fixed, in case change sampling number, the bit-reversed program needs to revise, and has certain passivity; Abroad, the explanation of calling that provides as the bit-reversed function module of sampling numbers such as 128,256,512 is arranged among the dsp chip manufacturers such as TI, but do not provide general bit-reversed algorithm.
Therefore general bit-reversed algorithm has practical significance widely, has the versatility of bigger meaning and stronger logic realization in the realization of language, has very strong realistic meaning in frequency converter product development and tandem product research and development thereof.
Summary of the invention
Technical problem to be solved by this invention is: a kind of bit-reversed method that is used for the data of frequency converter Fourier transform processing is provided, and this method wide application can reduce development cost.
The technical solution adopted in the present invention: a kind of bit-reversed method that is used for the data of frequency converter Fourier transform processing may further comprise the steps:
S1) determine the loop body that bit-reversed is exported according to following formula (1)～(4):
A(j)＝x(t)???????????????(1)，
A(j+1)＝x(t+2N/4)????????(2)，
A(j+2)＝x(t+N/4)?????????(3)，
A(j+3)＝x(t+3N/4)????????(4)，
Wherein A (j) is the output result behind the bit-reversed, and j is output result's sequence number; X (t) is the sample sequence of a certain concrete data of actual frequency converter of input before the bit-reversed, and t is the sequence number of this sample sequence;
S2) according to S1) definite loop body, by the initial value j that circulates for the first time
Initial value=0, what enter next time circulation advances rank j
Initial value=j
Initial value+ 4, cycling condition (j
The end value+ 1)＜and N/2 completion bit inverted order process, wherein N is the sampling number of sampled data, j
The end valueThe value of j when representing each loop ends;
S3) according to S2) the bit-reversed value of A (0)～A (N/2-1) of obtaining, obtain the bit-reversed value of A (N/2)～A (N-1) successively according to A (j+N/2)=A (j)+1.
The present invention has following advantage:
Advantage one, the development cost that reduced, human cost and hardware, software resource cost, particularly human cost.After adopting algorithm of the present invention, because it is more common, so when the similar frequency converter product of exploitation when needs change sampled point, because change is flexibly with convenient, can reduce the chip-stored resource, the dependence of arithmetic speed needn't arrange the developer that the bit-reversed function is made amendment in addition specially, reduce the construction cycle, thereby saved the exploitation human cost.
The portability of advantage two, raising development efficiency and similar tandem product.Development efficiency mainly is that code revision and test job amount reduce, by the signal spectrum and the entire system performance of contrast different mining sampling point situation, for the high-quality of product has been set up the basis; Portability mainly is that similar other products of exploitation and tandem product thereof can obtain characteristic preferably by minimal change, and versatility is more intense; Dependence to language also is eliminated in addition.
Advantage three, actual applicability are wide.Use at the frequency converter product, even for example rotating speed changed in Flying-start (operation) functional test of Siemens's high-performance transducer and the development process and accurately in the detection, also can use.In addition, field such as digital control, photovoltaic control of digital power, wind light mutual complementing all can be used.
Description of drawings
Fig. 1 is the tree-like rule figure that the present invention relates to.
The flow chart that Fig. 2 the present invention realizes.
Fig. 3 is the hardware block diagram that algorithm of the present invention is realized the place.
Embodiment
In this patent algorithm, high-performance vector frequency converter series of products in conjunction with actual exploitation, changing under detected signal (as frequency converter output biphase current) the sampling number situation, can realize " bit-reversed " function quickly and efficiently, for FFT specific algorithm and signal analysis provide good basis, thereby improved the frequency converter product development efficiency, can more thoroughly analyze the spectrum signature of frequency converter sampled signal and choose optimum sampling and count, had good portability simultaneously.
The present invention is a starting point with the most basic bit-reversed, has summed up general relatively bit-reversed algorithm.Adopt this algorithm, only need provide list entries, memory location, can return the list entries of realizing behind the bit-reversed, for preliminary treatment is done in next step computing (being butterfly computation) of FFT.This algorithm can carry out bit-reversed to sampled point number N=4, multiple spot input timing row sampled datas such as 8,16, not limited by development language, has good versatility and expansion usability.
The present invention is based on the signal processing of practical study project high-performance vector frequency converter, utilize the load of 22kW frequency converter band asynchronous motor, carried out actual experiment and demonstration in conjunction with the real system that with TI 28xx DSP (Digital Signal Processing) is core processor.In the research and development of products of high-performance vector-control frequency converter, relate to parameter identification, this concerns in the critical process of Frequency Converter Control performance and just need detect and data processing the frequency converter output current, need carry out Fourier (Fourier) conversion and corresponding data analysis.After parameter of electric machine identification accurately, just the result carries out vector control according to this, thereby the control motor moves according to controlled target, reaches better dynamic response performance and very high steady state controling precision.Therefore, the realization of high-performance vector-control frequency converter must be applied to FFT, also must use bit-reversed.
For example, the frequency converter output current is sampled.Because the output current that is sampled itself more or less can contain certain high-frequency harmonic current components, so, what data points sample be in the truth that guarantees accurately to reflect under the constant prerequisite of the entire system speed of service measured signal? though when sampled point surpass what the time signal can truly reflect still and can have a strong impact on the entire system speed of service? reasonable combination sample frequency and select suitable sampled signal to count how, does adopting rational algorithm to carry out harmonic signal separate and obtains the fundamental current component that needs and can guarantee the accuracy and the rapidity of frequency convertor system?
Therefore, in the product development process of high-performance vector frequency converter, can change sampling number as required, to carry out the optimization test of signal analysis.Contrast obtains signal spectrum key signal feature and harmonic wave signal characteristic under different mining sampling point situation, and integral operation speed, for the accuracy and the rapidity of frequency converter detection signal lays the first stone.
1. current state, inside and outside DSP manufacturer do not provide the FFT built-in function or the FFT built-in function of several sampling number situations only are provided, and have very big passivity.Like this, we adopt general bit-reversed algorithm of the present invention to carry out fft analysis flexibly with selecting the butterfly computation that is fit to, by revising sampling number voluntarily, call oneself bit-reversed and the butterfly computation algorithm FFT that realizes a plurality of different mining number of samples, broken away from dependence to particularly external chip producer of chip manufacturer data information, thereby the more deep and careful spectrum analysis of carrying out the frequency converter related data is strengthened signal authenticity and regular assurance have been strengthened initiative.
2. in the existing development process, if change sampling number, then the bit-reversed function needs to revise simultaneously, such as C language, mostly be that the change sampled point promptly needs dirty bit inverted order function to realize content, have the waste on the workload like this, product portability is poor, makes simultaneously decrease in efficiency in the development﹠ testing process.And adopt general bit-reversed algorithm of the present invention, and only need change macrodefinition variable can realize the sampling number modification, need not revise the bit-reversed function body, convenient, quick, realize the bit-reversed function expeditiously, strengthen reliability and had superior portability.
We adopt DSP as Controlled CPU (as adopting the C language development on the TI 28xx DSP) in the vector frequency converter series of products of reality exploitation.In development process and test process, output fundamental current, motor output frequency signal (perhaps rotating speed) etc. need be arranged the data parameters of frequency convertor system sampling, carry out analog-to-digital conversion after, all need to carry out the FFT calculation process, this just relates to the bit-reversed process; Simultaneously because the frequency converter of seriation different capacity, different performance index, the sampling number that all needs the crucial detection signal of choose reasonable, use general bit-reversed and butterfly computation quite necessary, we have adopted this general-purpose algorithm just in the reality exploitation, improved development efficiency, and can more thoroughly analyze frequency converter and adopt the actual characteristic of signal and choose optimum sampling point.
Be described in further detail the present invention below in conjunction with accompanying drawing.
As shown in Figure 3, Fig. 3 is the application system exemplary block diagram of Frequency Converter Control three-phase alternating-current motor.(380V, 50Hz), it comprises rectifier and inverter to main circuit of converter by the three-phase alternating current power supply.After three-phase alternating current is transformed into direct current by rectifier, can obtain frequency conversion and all variable three-phase output AC electricity of amplitude, in order to the operation of control three-phase alternating-current motor through three-phase inverter.Transducer control circuit is core with DSP, detects the inverter corresponding signal, adopts suitable control algolithm, and output PWM (pulse width modulation) control signal can rationally be controlled inverter.Wherein, comprise key signals such as inverter output current in the DSP detection signal, this type of signal is at first by A/D (mould/number) conversion input DSP, realize error correction and corresponding signal processing by DSP then, wherein comprise very crucial FFT and handle, and must need to use this function of bit-reversed in the fft algorithm.After carrying out signal processing and error correction, DSP just may carry out pwm pulse output control comparatively accurately, thereby guarantees the control performance of whole Frequency Converter Control system.Frequency converter can be connected to testing of electric motors TG (perhaps pulse coder is to detect motor speed) on the three-phase alternating-current motor in closed loop control mode, the rate signal feedback input converter control circuit that speed measuring motor TG records.General bit-reversed algorithm of the present invention can be optimized the FFT computing bit-reversed process among the DSP.
If exporting to the sequence of butterfly computation among the FFT behind the bit-reversed is A (j), N sampled data arranged, j and N are integer.Because A (j+N/2)=A (j)+1, so the latter half N/2 bit-reversed output sequence can be obtained by the first half N/2 bit-reversed output sequence.Therefore following form only need be listed the situation of the first half N/2 sequence, and a later half part N/2 output sequence can be obtained by formula A (j+N/2)=A (j)+1.Wherein bit-reversed input index is the sequence number t of the list entries x (t) before the bit-reversed behind the crude sampling, and the binary data that the bit-reversed process obtains becomes the decimal system and promptly obtains bit-reversed input index.
Table one: N=4, (N is a sampling number to M=2, N=2
M)
| Bit-reversed output | The bit-reversed process | Bit-reversed input index |
| ??A(0) | ??00 | ??0 |
| ??A(1) | ??10 | ??2 |
Table two: N=8, M=3
| Bit-reversed output | The bit-reversed process | Bit-reversed input index |
| ??A(0) | ??000 | ??0 |
| ??A(1) | ??100 | ??4 |
| ??A(2) | ??010 | ??2 |
| ??A(3) | ??110 | ??6 |
Table three: N=16, M=4
| Bit-reversed output | The bit-reversed process | Bit-reversed input index |
| ??A(0) | ??0000 | ??0 |
| ??A(1) | ??1000 | ??8 |
| ??A(2) | ??0100 | ??4 |
| ??A(3) | ??1100 | ??12 |
| ??A(4) | ??0010 | ??2 |
| ??A(5) | ??1010 | ??10 |
| ??A(6) | ??0110 | ??6 |
| ??A(7) | ??1110 | ??14 |
Table four: N=32, M=5
| Bit-reversed output | The bit-reversed process | Bit-reversed input index |
| ??A(0) | ??00000 | ??0 |
| ??A(1) | ??10000 | ??16 |
| ??A(2) | ??01000 | ??8 |
| ??A(3) | ??11000 | ??24 |
| ??A(4) | ??00100 | ??4 |
| ??A(5) | ??10100 | ??20 |
| ??A(6) | ??01100 | ??12 |
| ??A(7) | ??11100 | ??28 |
| ??A(8) | ??00010 | ??2 |
| ??A(9) | ??10010 | ??18 |
| ??A(10) | ??01010 | ??10 |
| ??A(11) | ??11010 | ??26 |
| ??A(12) | ??00110 | ??6 |
| ??A(13) | ??10110 | ??22 |
| ??A(14) | ??01110 | ??14 |
| ??A(15) | ??11110 | ??30 |
Table five: N=64, M=6
| Bit-reversed output | The bit-reversed process | Bit-reversed input index |
| ??A(0) | ??000000 | ??0 |
| ??A(1) | ??100000 | ??32 |
| ??A(2) | ??010000 | ??16 |
| ??A(3) | ??110000 | ??48 |
| Bit-reversed output | The bit-reversed process | Bit-reversed input index |
| ??A(4) | ??001000 | ??8 |
| ??A(5) | ??101000 | ??40 |
| ??A(6) | ??011000 | ??24 |
| ??A(7) | ??111000 | ??56 |
| ??A(8) | ??000100 | ??4 |
| ??A(9) | ??100100 | ??36 |
| ??A(10) | ??010100 | ??20 |
| ??A(11) | ??110100 | ??52 |
| ??A(12) | ??001100 | ??12 |
| ??A(13) | ??101100 | ??44 |
| ??A(14) | ??011100 | ??28 |
| ??A(15) | ??111100 | ??60 |
| ??A(16) | ??000010 | ??2 |
| ??A(17) | ??100010 | ??34 |
| ??A(18) | ??010010 | ??18 |
| ??A(19) | ??110010 | ??50 |
| ??A(20) | ??001010 | ??10 |
| ??A(21) | ??101010 | ??42 |
| ??A(22) | ??011010 | ??26 |
| ??A(23) | ??111010 | ??58 |
| ??A(24) | ??000110 | ??6 |
| ??A(25) | ??100110 | ??38 |
| Bit-reversed output | The bit-reversed process | Bit-reversed input index |
| ??A(26) | ??010110 | ??22 |
| ??A(27) | ??110110 | ??54 |
| ??A(28) | ??001110 | ??14 |
| ??A(29) | ??101110 | ??16 |
| ??A(30) | ??011110 | ??30 |
| ??A(31) | ??111110 | ??62 |
From above five typical form data characteristicses, can obtain loop body.Wherein A (j) is the output result behind the bit-reversed, and it is verified that in the experiment of actual converter parameter Identification Data Processing x (t) is the sample sequence of a certain concrete data of the actual frequency converter of input before the bit-reversed:
A(j)＝x(t)，
A(j+1)＝x(t+2N/4)，
A(j+2)＝x(t+N/4)，
A(j+3)＝x(t+3N/4).
More than four formulas as loop body, this loop body is according to representative value 4=2
2, promptly by two binary digit B
1B
0Combination can obtain.Two binary digit B
1B
0Can make up and obtain four decimal values: be i.e. (00)
2=0, (01)
2=1, (10)
2=2, (11)
2=3, subscript 2 expressions 2 system numbers; And according to the thinking of bit-reversed, lowest order B here
0On duty with 2
1Add B
1Multiply by 2
0The result just obtained the output sequence behind the bit-reversed, i.e. (00)
2 bit-reverseds=0, (01)
2 bit-reverseds=2, (10)
2 bit-reverseds=1, (11)
2 bit-reverseds=3; Therefore the loop body of deriving is: A behind the bit-reversed (j)=x (t+N/4* (00)
2 bit-reverseds)=x (t), A (j+1)=x (t+N/4* (01)
2 bit-reverseds)=x (t+2N/4), A (j+2)=x (t+N/4* (10)
2 bit-reverseds)=x (t+N/4), A (j+3)=x (t+N/4* (11)
2 Bit-reversed)=x (t+3N/4).
The key point that changes is the value of t.Initial value t=0, value will be determined according to N (perhaps M) afterwards, respectively at N=8,16,32,64:
M＝3，t＝0；
M＝4，t＝0，2
M＝5，t＝0，4，2，6
M＝6，t＝0，8，4，12，2，10，6，14
As shown in Figure 1, can obtain the value rule of t:
T value when the t value during by M-1 can be derived M, two of t when promptly the t during M-1 is separated into M and t+N/8.
For example, the t=0 during M=4,2;
During M=5, last time to get 0 branch bifurcated be 0 and 0+N/8 (promptly 4) to t, and last time the branch bifurcated got 2 o'clock of t was 2 and 2+N/8 (promptly 6), thus this moment t value be 0,4,2,6.
Illustrate: N is that actual frequency converter sampled data (as the A phase current) is counted N=2
M, t is actual sequence number for list entries x (t) before the inverted order.Become tree form data structure with co-relation, the value that can find t all is the ordered branch of upper level M trunk.
The constraint of cyclic process: the initial value j of the circulation first time
Initial value=0, enter circulation next time and then advance rank j
Initial value=j
Initial value+ 4, cycling condition (j
The end value+ 1)＜N/2, wherein j
The end valueThe value of j when representing each loop ends.
Embodiment:
With N=16, M=4 is an example, this moment t=0,2.
At first obtain loop body:
A(j)＝x(t)，
A(j+1)＝x(t+8)，
A(j+2)＝x(t+4)，
A(j+3)＝x(t+12).
Circulation time for the first time, j
Initial value=0, t gets 0, then can obtain:
A (0)=x (0), A (1)=x (8), A (2)=x (4), A (3)=x (12), final j
The end value=3.
This moment j
The end value+ 1=4, N/2=8,4＜8, enter circulation next time.
Entering rank is j
Initial value=j
Initial value+ 4, promptly this moment j
Initial value=4, t gets 2, then can obtain:
A (4)=x (2), A (5)=x (10), A (6)=x (6), A (7)=x (14), final j
The end value=7.
This moment j
The end value+ 1=8 equates with N/2, stops circulation.
According to A (j+N/2)=A (j)+1, obtain then: A (8)=A (0)+1, i.e. A (8)=x (0)+1,
A (9)=x (8)+1 in like manner, A (10)=x (4)+1 ... A (15)=x (14)+1.
The flow chart of implementation algorithm is referring to Fig. 2 in the Figure of description; Below provide representative C language codes:
void?BitReverse(int?INPUT1[]，int?DATA1[]，int?number，int?M)
{
int?i，j，N，L；
int?t，k，p；
int?B[M-3][2^(M-3)]；
i＝0；
j＝0；
N＝number；
t＝0；
for(L＝0；L＜(M-2)；L++)
{
if(L＝＝0)B[0][0]＝0；
else
{for(k＝0，p＝0；(k＜2^(M-3))&&(p＜2^(M-4))；k＝k+2；p＝p+1)
{
B[L][k]＝B[L-1][p]；
B[L][k+1]＝B[L-1][p]+2^(L+3)/8；
}
}
}
for(i＝0；i＜2^(M-3)；i＝i+1)
if(j＜(N/2-3))
{?????t＝B[M-3][i]；
DATA1[j]＝INPUT1[t]；
DATA1[j+1]＝INPUT1[t+2*N/4]；
DATA1[j+2]＝INPUT1[t+1*N/4]；
DATA1[j+3]＝INPUT1[t+3*N/4]；
j＝j+4；
}
// later half N/2 bit-reversed is obtained by symmetry
for(j＝N/2；j＜N；j++)
DATA1[j]＝INPUT1[j-N/2+1]；
}
Claims (2)
1. a bit-reversed method that is used for the data of frequency converter Fourier transform processing is characterized in that, may further comprise the steps:
S1) determine the loop body that bit-reversed is exported according to following formula (1)～(4):
A(j)＝x(t)???????????????(1)，
A(j+1)＝x(t+2N/4)????????(2)，
A(j+2)＝x(t+N/4)?????????(3)，
A(j+3)＝x(t+3N/4)????????(4)，
Wherein A (j) is the output result behind the bit-reversed, and j is output result's sequence number; X (t) is the sample sequence of a certain concrete data of actual frequency converter of input before the bit-reversed, and t is the sequence number of this sample sequence;
S2) according to S1) definite loop body, by the initial value j that circulates for the first time
Initial value=0, what enter next time circulation advances rank j
Initial value=j
Initial value+ 4, cycling condition (j
The end value+ 1)＜and N/2 completion bit inverted order process, wherein N is the sampling number of sampled data, j
The end valueThe value of j when representing each loop ends;
S3) according to S2) the bit-reversed value of A (0)～A (N/2-1) of obtaining, obtain the bit-reversed value of A (N/2)～A (N-1) successively according to A (j+N/2)=A (j)+1.
2. bit-reversed method according to claim 1 is characterized in that, determine that the method for the value of the sequence number t of sample sequence before the bit-reversed is: initial value t=0, its value is determined according to the number N of sampled data afterwards, wherein N=2
M, be specially:
During M=3, t=0;
During M=4, t=0,2;
During M=5, t=0,4,2,6;
During M=6, t=0,8,4,12,2,10,6,14;
Wherein the value of t all is the ordered branch of upper level M trunk.
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| JP2002351858A (en) * | 2001-05-30 | 2002-12-06 | Fujitsu Ltd | Processing equipment |
| US20030131032A1 (en) * | 2001-12-28 | 2003-07-10 | Gil Vinitzky | Bit-reversed indexing in a modified harvard DSP architecture |
| CN1808419A (en) * | 2005-07-15 | 2006-07-26 | 北京大学深圳研究生院 | Real-time fast Fourier transform circuit |
| KR100667188B1 (en) * | 2005-12-10 | 2007-01-12 | 한국전자통신연구원 | Fast Fourier Transform and Fast Fourier Transform |
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2010
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002351858A (en) * | 2001-05-30 | 2002-12-06 | Fujitsu Ltd | Processing equipment |
| US20030131032A1 (en) * | 2001-12-28 | 2003-07-10 | Gil Vinitzky | Bit-reversed indexing in a modified harvard DSP architecture |
| CN1808419A (en) * | 2005-07-15 | 2006-07-26 | 北京大学深圳研究生院 | Real-time fast Fourier transform circuit |
| KR100667188B1 (en) * | 2005-12-10 | 2007-01-12 | 한국전자통신연구원 | Fast Fourier Transform and Fast Fourier Transform |
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