CN101888242B - Phase-locked loop circuit and operation method thereof - Google Patents
Phase-locked loop circuit and operation method thereof Download PDFInfo
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- CN101888242B CN101888242B CN 200910050992 CN200910050992A CN101888242B CN 101888242 B CN101888242 B CN 101888242B CN 200910050992 CN200910050992 CN 200910050992 CN 200910050992 A CN200910050992 A CN 200910050992A CN 101888242 B CN101888242 B CN 101888242B
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Abstract
The invention provides a phase-locked loop circuit. The circuit comprises a charge pump, a first capacitor, a second capacitor, a main capacitor, an on-off control unit and a feedback circuit, wherein the charge pump is used to generate charge pump current capable of performing forward transmission or reverse transmission; the first capacitor is connected with the second capacitor in parallel and the two capacitors are connected with the charge pump; the main capacitor is in series connection with the parallel first capacitor and second capacitor; the on-off control unit controls the connection or disconnection between the first and second capacitors and the main capacitor; the charge pump current generated by the charge pump is used to charge or discharge the first capacitor or second capacitor in off state; and the feedback circuit is connected with the first capacitor, the second capacitor and the main capacitor, and the feedback circuit is used to generate control voltage according to the voltages of the first capacitor, the second capacitor and the main capacitor. Therefore, the adjustment of damping factor does not depend on the adjustment of capacitance so that the adjustment of damping factor is wholly independent from the adjustment of eigen frequency.
Description
Technical field
The present invention relates to integrated circuit fields, particularly phase-locked loop (Phase-Locked Loop, PLL) circuit.
Background technology
The PLL circuit is widely used in many aspects, comprises that clock and data are recovered, clock is synthetic, frequency synthesis, modulator-demodulator etc.Generally speaking, the PLL circuit is used to provide one to become certain multiple relation, the output clock that the position is relevant with input clock frequency usually.
As shown in Figure 1 is a traditional P LL circuit, comprise a phase frequency detector (Phase FrequencyDetector, PFD); A charge pump; A loop filter, (Voltage ControlledOscillator is VCO) with a frequency divider for a voltage controlled oscillator.Said frequency divider will be exported clock Fvco and obtain a feedback clock Ffbk divided by a division factor N.One between said input clock Fref of PFD detection and the feedback clock Ffbk differs.Said charge pump according to input clock Fref be prior to or lag behind the situation of feedback clock Ffbk, the charge pump current ICP that produces a transmission forward or backwards gives loop filter.Loop filter is integrated these charge pulses and is produced an oscillator control voltage Vctr1..Said oscillator control voltage Vctr1 raises or reduces the Phase synchronization of the output clock Fvco of said VCO up to input clock Fref and feedback clock Ffbk.Said loop filter further comprises a loop resitance device R of series connection
pWith a loop capacitance device C
pSaid division factor N is by the expected frequence decision of said output clock Fvco.Because said division factor N is constant, said PLL circuit can make output clock Fvco accurately for the N of input clock Fref doubly.
Please refer to formula and calculate the damping factor δ and the eigenfrequency ω of a PLL circuit
n:
The Kvco tuning sensitivity that to be said VCO draw according to the ratio of radian and voltage wherein, Icp is a charge pump current, and N is a division factor, and Rp is the resistance of loop resitance, and Cp is the electric capacity of loop capacitance.
Said eigenfrequency ω
nThe response performance of representing said PLL circuit.Said damping factor δ is used for detecting the mapping of said PLL circuit.If adopt inappropriate damping factor δ, the fluctuation of circuit can not be blocked, and makes said PLL circuit become unstable.
In existing P LL circuit, usually through regulation loop capacitor C
pRegulate damping factor δ, however visible by formula (1) and (2), the damping factor δ of existing P LL circuit and eigenfrequency ω
nValue all with loop capacitance device C
pValue relevant, when regulating damping factor δ, can change its eigenfrequency ω simultaneously
n
Because charge pump directly discharges and recharges the node of VCO control voltage, eigenperiod property noise is higher among the PLL simultaneously.Because voltge surge peak value and reference frequency that charge pump discharges and recharges the control voltage node have nothing to do, after the phase-locked loop reference frequency reduced, this periodic noise can and then not reduce simultaneously.
The present invention then provides a kind of new mode in order to improve or to solve the above problems.
Summary of the invention
The technical problem that the present invention will solve is to provide a kind of PLL circuit and operation method thereof, makes the adjusting of damping factor can be totally independent of the adjusting of eigenfrequency, also can the periodicity intrinsic noise be reduced to minimum; Adopt single charge pump simultaneously, reduce the total capacitance size requirements.
The present invention solves above-mentioned technical problem through such technical scheme:
A kind of phase-locked loop circuit is provided, and it comprises:
Charge pump is used to produce the charge pump current of transmission forward or backwards;
First electric capacity and second electric capacity, said first electric capacity is parallelly connected with second electric capacity, and is connected with said charge pump;
Main capacitance is with the said first parallelly connected electric capacity and second capacitances in series;
Switch control unit is controlled and is broken off in turn between said first electric capacity and second electric capacity and the said main capacitance and is communicated with, and the charge pump current of said charge pump generation is to first electric capacity or second capacitor charge and discharge of said off-state;
Feedback circuit connects said first electric capacity, second electric capacity and main capacitance, is used for according to the voltage on said first electric capacity, second electric capacity and the main capacitance, generates control voltage;
Voltage controlled oscillator, said voltage controlled oscillator is connected to said feedback circuit, and produces an output clock according to the control voltage of said feedback circuit output.
As a kind of improvement of the present invention, said feedback circuit comprises at least three P type metal-oxide-semiconductors, is connected with said first electric capacity, second electric capacity, main capacitance respectively, and the control voltage of said feedback circuit output is: Vct=V1+ α (Δ V21+ Δ V22);
Wherein, Vct representes the control voltage that said feedback circuit produces, and V1 representes said main capacitance voltage; Δ V21 representes the voltage difference of said first electric capacity and main capacitance; Δ V22 representes the voltage difference of said second electric capacity and main capacitance, and α is the feedback circuit parameter, is confirmed by each P type metal-oxide-semiconductor dimension ratio.
As a kind of improvement of the present invention, said circuit also comprises:
Frequency divider connects said voltage controlled oscillator, is used for the output clock that said voltage controlled oscillator produces is obtained a feedback clock divided by a division factor;
Phase frequency detector connects said frequency divider, is used to detect differing between an input clock and the said feedback clock;
Said charge pump produces the charge pump current of transmission forward or backwards according to the testing result of said phase frequency detector.
As a kind of improvement of the present invention; Said switch control unit comprises two switches; With said first electric capacity and second capacitances in series, said each switch breaks off in turn and is communicated with respectively, the capacitor charge and discharge that the charge pump current that said charge pump produces breaks off said switch.
As a kind of improvement of the present invention, the disconnection of said switch and connection are by said input clock control.
As a kind of improvement of the present invention, said first electric capacity and second capacitance size equate.
The present invention also provides a kind of operation method of phase-locked loop circuit, may further comprise the steps:
Charge pump produces the charge pump current of transmission forward or backwards;
Control and break off in turn between first electric capacity and second electric capacity and the main capacitance and is communicated with, the charge pump current of said charge pump generation is to first electric capacity or second capacitor charge and discharge of said off-state;
Feedback circuit generates control voltage according to the voltage on said first electric capacity, second electric capacity and the main capacitance;
Voltage controlled oscillator produces an output clock according to the control voltage of said feedback circuit output.
As a kind of improvement of the present invention, the control voltage of said feedback circuit output is: Vct=V1+ α (Δ V21+ Δ V22);
Wherein, Vct representes the control voltage that said feedback circuit produces; V1 representes said main capacitance voltage, and Δ V21 representes the voltage difference of said first electric capacity and main capacitance, and Δ V22 representes the voltage difference of said second electric capacity and main capacitance; α is the feedback circuit parameter, is confirmed by each P type metal-oxide-semiconductor dimension ratio in the said feedback circuit.
As a kind of improvement of the present invention, further comprising the steps of:
Said output clock is obtained a feedback clock divided by a division factor;
An input clock and said feedback clock are compared, and said charge pump produces the charge pump current of transmission forward or backwards according to this comparative result.
As a kind of improvement of the present invention; In the step of breaking off in turn between said control first electric capacity and second electric capacity and the main capacitance and being communicated with, control the switch disconnection and being communicated with in turn between the switch between said first electric capacity and the main capacitance, said second electric capacity and the main capacitance according to said input clock.
Compared with prior art, the present invention has the following advantages: said first electric capacity is parallelly connected with second electric capacity, and is connected with said charge pump; Main capacitance and the said first parallelly connected electric capacity and second capacitances in series; Switch control unit is controlled and is broken off in turn between said first electric capacity and second electric capacity and the said main capacitance and is communicated with, and the charge pump current of said charge pump generation is to first electric capacity or second capacitor charge and discharge of said off-state; Feedback circuit connects said first electric capacity, second electric capacity and main capacitance, is used for according to the voltage on said first electric capacity, second electric capacity and the main capacitance, generates control voltage.Make the adjusting of damping factor need not rely on the adjusting of electric capacity, thereby make the adjusting of damping factor can be totally independent of the adjusting of eigenfrequency.Do not discharge and recharge owing to charge pump has direct node to VCO control voltage simultaneously, thereby can the periodicity intrinsic noise be reduced to minimum.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Fig. 1 is a traditional P LL circuit diagram in the prior art;
Fig. 2 is the PLL circuit diagram of first embodiment of the invention;
Fig. 3 is the PLL circuit diagram of second embodiment of the invention;
Fig. 4 is the PLL circuit diagram of third embodiment of the invention;
Fig. 5 is the PLL circuit operational flow diagram of four embodiment of the invention.
Embodiment
Specify embodiment of the present invention below in conjunction with accompanying drawing.
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing that execution mode of the present invention is done to describe in detail further below.
First embodiment of the invention relates to a kind of PLL circuit, and this PLL circuit is for adopting the phase-locked loop feedback circuit of switching capacity structure, and is as shown in Figure 2; Comprise PFD 210, the electric capacity of 220, two parallel connections of charge pump---electric capacity 231 and electric capacity 232; A main capacitance 240; Switch control unit 250, feedback circuit 260, VCO 270 and frequency divider 280.Generally speaking, electric capacity 231 and electric capacity 232 equal and opposite in directions.
Wherein, charge pump 220 is used to produce the charge pump current of transmission forward or backwards; Electric capacity 231 and electric capacity 232 parallel connections, and be connected with charge pump 220; Electric capacity 231 after main capacitance 240 and the parallel connection is connected with electric capacity 232; Break off in turn between switch control unit 250 control capacitances 231 and electric capacity 232 and the main capacitance 240 and is communicated with, the charge pump current of charge pump 220 generations discharges and recharges the electric capacity 231 or the electric capacity 232 of off-state; Feedback circuit 260 connects electric capacity 231, electric capacity 232 and main capacitance 240, is used for according to the voltage on electric capacity 231, electric capacity 232 and the main capacitance 240, generates control voltage; VCO 270 connects with being connected feedback circuit 260, and produces an output clock according to the control voltage of its output.Frequency divider 280 connects VCO 270, is used for the output clock that VCO 270 produces is obtained a feedback clock divided by a division factor N; PFD210 is connected with frequency divider 280, is used to detect differing between input clock and the feedback clock; Charge pump 220 produces the charge pump current of transmission forward or backwards according to the testing result of PFD 210.In this PLL circuit, can obstructedly overregulate electric capacity and change damping factor, the adjusting that is to say damping factor is not certain adjusting that needs to rely on electric capacity, thereby makes the adjusting of damping factor can be totally independent of the adjusting of eigenfrequency.Do not discharge and recharge owing to charge pump has direct node to VCO control voltage simultaneously, thereby can the periodicity intrinsic noise be reduced to minimum.
Second embodiment of the invention relates to a kind of PLL circuit equally, and is roughly the same with first execution mode, and its difference is; In this execution mode, switch control unit is replaced by two switches, i.e. switch 251 and switch 252; As shown in Figure 3; Switch 251 is connected with electric capacity 231 and electric capacity 232 respectively with switch 252, and each switch breaks off in turn and is communicated with, and the charge pump current that charge pump produces is split and closed the capacitor charge and discharge that breaks off.
That is to say that 220 pairs of electric capacity of the control of two switches and charge pump 231 are opposite with the control logic of electric capacity 232 chargings.When 220 pairs of electric capacity 231 of charge pump discharged and recharged, the switch 251 that electric capacity 231 and main capacitance are 240 broke off; When 220 pairs of electric capacity 232 of charge pump discharged and recharged, the switch 252 that electric capacity 232 and main capacitance are 240 broke off.The disconnection of switch 251 and switch 252 and connection can be controlled by input clock.
Third embodiment of the invention relates to a kind of PLL circuit equally, and is roughly the same with second execution mode, and its difference is; In this execution mode; Feedback circuit 260 comprises at least three P type metal-oxide-semiconductors, is connected with electric capacity 231, electric capacity 232, main capacitance 240 respectively, and is as shown in Figure 4.
Because charge pump 220 discharges and recharges electric capacity 231 and 232 in turn, that is to say that when 220 pairs of electric capacity 231 of charge pump discharged and recharged, the switch 251 that electric capacity 231 and main capacitance are 240 broke off; When 220 pairs of electric capacity 232 of charge pump discharged and recharged, the switch 252 that electric capacity 232 and main capacitance are 240 broke off.Behind the switch connection between electric capacity in electric capacity 231 or the electric capacity 232 and the main capacitance 240, the voltage on its magnitude of voltage and the main capacitance 240 is redistributed the magnitude of voltage that reaches same through electric charge; Simultaneously, the magnitude of voltage on another electric capacity is by electric capacity 231, and the voltage on electric capacity 232 and the main capacitance 240 generates final control voltage through feedback circuit 260 combinations.Feedback circuit 260 last control voltage Vct as shown in Figure 4 are magnitude of voltage V1, V21, the weighted average of V22.Be Vct=V1+ α (Δ V21+ Δ V22), wherein, V1 representes the magnitude of voltage of main capacitance 240; Δ V21 representes the voltage difference of electric capacity 231 and main capacitance 240; Be Δ V21=V21-V1, Δ V22 representes the voltage difference of electric capacity 232 and main capacitance 240, i.e. Δ V22=V22-V1.α is the feedback circuit parameter, and by receiving electric capacity 231, the P type metal-oxide-semiconductor dimension ratio decision of P type metal-oxide-semiconductor size on the electric capacity 232 and the 3rd diode short circuit is promptly confirmed by P0, P1, P2 dimension ratio.In this execution mode, electric capacity 231 is identical with electric capacity 232 sizes.
Release the eigenfrequency ω of whole phase-locked loop thus
nApproximate calculation is through continuous model with damping factor δ:
Wherein, Icp is the charge pump current of charge pump 240.K1 is the gain of VCO 270.N is the division factor of frequency divider 280, i.e. frequency division value.T is the input clock cycle of PFD 210.C1 is the capacitance of main capacitance 240, and C2 is the capacitance of electric capacity 231 and electric capacity 232.From formula (4), can find out; Damping factor can δ changes and adjusted with the α value; Promptly only need to regulate the ratio of three P type metal-oxide-semiconductor sizes, just can regulate damping factor δ, the value that need not change main capacitance 240, electric capacity 231 and electric capacity 232 so also can realize the adjusting of damping factor δ; Make when regulating damping factor δ, can not change eigenfrequency ω
n
Four embodiment of the invention relates to a kind of operation method of PLL circuit, and is as shown in Figure 5, may further comprise the steps:
In step 510, charge pump produces the charge pump current of transmission forward or backwards.
In step 520, to control and break off in turn between first electric capacity and second electric capacity and the main capacitance and is communicated with, the charge pump current of charge pump generation is to first electric capacity or second capacitor charge and discharge of off-state.Specifically, can be according to the input clock of input PFD, control switch between first electric capacity and the main capacitance, second electric capacity and break off in turn with switch between the main capacitance and be communicated with.
In the step 530, feedback circuit generates control voltage according to the voltage on first electric capacity, second electric capacity and the main capacitance.Make the adjusting of damping factor need not rely on the adjusting of electric capacity, thereby make the adjusting of damping factor can be totally independent of the adjusting of eigenfrequency.Wherein, the control voltage of feedback circuit output is: Vct=V1+ α (Δ V21+ Δ V22); Vct representes the control voltage that feedback circuit produces; V1 representes main capacitance voltage, and Δ V21 representes the voltage difference of first electric capacity and main capacitance, and Δ V22 representes the voltage difference of second electric capacity and main capacitance; α is the feedback circuit parameter, is confirmed by each P type metal-oxide-semiconductor dimension ratio in the feedback circuit.
In the step 540, VCO produces an output clock according to the control voltage of feedback circuit output.Because charge pump does not have direct node to VCO control voltage to discharge and recharge, thereby can the periodicity intrinsic noise be reduced to minimum.
In the step 550, frequency divider will be exported clock and obtain a feedback clock divided by a division factor.
In the step 560, PFD detects differing between an input clock and the feedback clock, and testing result outputs to charge pump.Then return step 410, charge pump produces the charge pump current of transmission forward or backwards according to this comparative result.
In sum, in embodiments of the present invention, said first electric capacity is parallelly connected with second electric capacity, and is connected with said charge pump; Main capacitance and the said first parallelly connected electric capacity and second capacitances in series; Switch control unit is controlled and is broken off in turn between said first electric capacity and second electric capacity and the said main capacitance and is communicated with, and the charge pump current of said charge pump generation is to first electric capacity or second capacitor charge and discharge of said off-state; Feedback circuit connects said first electric capacity, second electric capacity and main capacitance, is used for according to the voltage on said first electric capacity, second electric capacity and the main capacitance, generates control voltage.Make the adjusting of damping factor need not rely on the adjusting of electric capacity, thereby make the adjusting of damping factor can be totally independent of the adjusting of eigenfrequency.Do not discharge and recharge owing to charge pump has direct node to VCO control voltage simultaneously, thereby can the periodicity intrinsic noise be reduced to minimum.
The above is merely preferred embodiments of the present invention; Protection scope of the present invention is not exceeded with above-mentioned execution mode; As long as the equivalence that those of ordinary skills do according to disclosed content is modified or changed, all should include in the protection range of putting down in writing in claims.
Claims (8)
1. a phase-locked loop circuit is characterized in that, comprising:
Charge pump is used to produce the charge pump current of transmission forward or backwards;
First electric capacity and second electric capacity, said first electric capacity is parallelly connected with second electric capacity, and is connected with said charge pump;
Main capacitance is with the said first parallelly connected electric capacity and second capacitances in series;
Switch control unit is controlled and is broken off in turn between said first electric capacity and second electric capacity and the said main capacitance and is communicated with, first electric capacity or second capacitor charge and discharge of the charge pump current that said charge pump produces pair and main capacitance disconnection;
Feedback circuit connects said first electric capacity, second electric capacity and main capacitance, is used for according to the voltage on said first electric capacity, second electric capacity and the main capacitance, generates control voltage;
Voltage controlled oscillator, said voltage controlled oscillator is connected to said feedback circuit, and produces an output clock according to the control voltage of said feedback circuit output;
Wherein, said feedback circuit comprises at least three P type metal-oxide-semiconductors, is connected with said first electric capacity, second electric capacity, main capacitance respectively, and the control voltage of said feedback circuit output is: Vct=V1+ α (Δ V21+ Δ V22);
Wherein, Vct representes the control voltage that said feedback circuit produces, and V1 representes said main capacitance voltage; Δ V21 representes the voltage difference of said first electric capacity and main capacitance; Δ V22 representes the voltage difference of said second electric capacity and main capacitance, and α is the feedback circuit parameter, is confirmed by each P type metal-oxide-semiconductor dimension ratio.
2. phase-locked loop circuit according to claim 1 is characterized in that, also comprises:
Frequency divider connects said voltage controlled oscillator, is used for the output clock that said voltage controlled oscillator produces is obtained a feedback clock divided by a division factor;
Phase frequency detector connects said frequency divider, is used to detect differing between an input clock and the said feedback clock;
Said charge pump produces the charge pump current of transmission forward or backwards according to the testing result of said phase frequency detector.
3. phase-locked loop circuit according to claim 2; It is characterized in that; Said switch control unit comprises two switches; With said first electric capacity and second capacitances in series, said each switch breaks off in turn and is communicated with respectively, the capacitor charge and discharge that the charge pump current that said charge pump produces breaks off said switch.
4. phase-locked loop circuit according to claim 3 is characterized in that, the disconnection of said switch and connection are by said input clock control.
5. phase-locked loop circuit according to claim 1 is characterized in that, said first electric capacity and second capacitance size equate.
6. the operation method of a phase-locked loop circuit is characterized in that, may further comprise the steps:
Charge pump produces the charge pump current of transmission forward or backwards;
Control and break off in turn between first electric capacity and second electric capacity and the main capacitance and is communicated with, first electric capacity or second capacitor charge and discharge of the charge pump current that said charge pump produces pair and main capacitance disconnection;
Feedback circuit generates control voltage according to the voltage on said first electric capacity, second electric capacity and the main capacitance;
Voltage controlled oscillator produces an output clock according to the control voltage of said feedback circuit output;
Wherein, the control voltage of said feedback circuit output is: Vct=V1+ α (Δ V21+ Δ V22);
Wherein, Vct representes the control voltage that said feedback circuit produces; V1 representes said main capacitance voltage, and Δ V21 representes the voltage difference of said first electric capacity and main capacitance, and Δ V22 representes the voltage difference of said second electric capacity and main capacitance; α is the feedback circuit parameter, is confirmed by each P type metal-oxide-semiconductor dimension ratio in the said feedback circuit.
7. the operation method of phase-locked loop circuit according to claim 6 is characterized in that, and is further comprising the steps of:
Said output clock is obtained a feedback clock divided by a division factor;
An input clock and said feedback clock are compared, and said charge pump produces the charge pump current of transmission forward or backwards according to this comparative result.
8. the operation method of phase-locked loop circuit according to claim 7; It is characterized in that; In the step of breaking off in turn between said control first electric capacity and second electric capacity and the main capacitance and being communicated with, control the switch disconnection and being communicated with in turn between the switch between said first electric capacity and the main capacitance, said second electric capacity and the main capacitance according to said input clock.
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| CN 200910050992 CN101888242B (en) | 2009-05-12 | 2009-05-12 | Phase-locked loop circuit and operation method thereof |
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| CN 200910050992 CN101888242B (en) | 2009-05-12 | 2009-05-12 | Phase-locked loop circuit and operation method thereof |
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| CN101888242B true CN101888242B (en) | 2012-12-19 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101056105A (en) * | 2007-04-11 | 2007-10-17 | 威盛电子股份有限公司 | Composite Metal Oxide Semiconductor Capacitor and Phase Locked Loop |
| US7339420B2 (en) * | 2004-07-27 | 2008-03-04 | Matsushita Electric Industrial Co., Ltd. | Method of switching PLL characteristics and PLL circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7339420B2 (en) * | 2004-07-27 | 2008-03-04 | Matsushita Electric Industrial Co., Ltd. | Method of switching PLL characteristics and PLL circuit |
| CN101056105A (en) * | 2007-04-11 | 2007-10-17 | 威盛电子股份有限公司 | Composite Metal Oxide Semiconductor Capacitor and Phase Locked Loop |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平11-251902A 1999.09.17 |
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