CN101976949B - Anti-interference rapid current sampling circuit based on difference structure - Google Patents

Abstract

The present invention proposes a fast anti-interference current sampling circuit based on a differential structure, including a differential sampling main circuit and a bias voltage generating circuit, and two different voltages are generated by the bias voltage to the common gate transistor in the sampling main circuit , the output signal of the main circuit of the differential sampling is the anti-interference sampling signal that controls the entire loop or the overcurrent protection circuit. The present invention can effectively filter out the interference caused by the power supply itself or the multi-channel DC-DC switch action. This anti-interference structure can not only be used for precise control of the overcurrent protection circuit, but also can be applied to the current mode DC-DC Stable loop control is achieved in the DC loop.

Description

Fast Anti-interference Current Sampling Circuit Based on Differential Structure

technical field

The invention relates to the field of switching power supplies, and is applied to the overcurrent protection circuit of a voltage-mode DC-DC converter (DC-DC) and the current control loop of a current-mode DC-DC converter, in particular to a fast anti-corrosion circuit based on a differential structure in an integrated circuit. Interfering with the current sampling circuit.

Background technique

Power management chips are an important part of electronic products, and the quality of power management chips directly affects the performance of electronic devices. With the increasingly diversified functions of portable devices such as mobile phones, PDAs, digital cameras and MP3 players, research and development of high-efficiency miniaturized DC-DC converters has become the mainstream direction in this field. Current sampling can not only be used in the voltage mode DC-DC overcurrent protection circuit, but also an important part of the current mode DC-DC loop, which affects the performance of the current mode DC-DC. On the one hand, when there is interference on the power line (for example, when the switching tube is switched or other switching tubes in the multi-channel DC-DC are switched), the sampled signal also has interference. When the amount of interference is significant, it will lead to comparison The wrong flip of the device will cause the control logic to be confused or the over-temperature protection circuit to shut down the chip by mistake; on the other hand, the speed of the sampling circuit limits the DC-DC operating frequency.

At present, there are relatively few studies on sampling anti-interference problems. Although the traditional current sampling circuit involved in Document 1 has a simple structure and relatively fast speed, its anti-interference ability is relatively poor, and it is not suitable for application in multi-channel DC-DC.

[Document 1] Kuo-Hsing Cheng; Chia-Wei Su; Hsin-Hsin Ko.A High-Accuracy and High-Efficiency on-Chip Current Sensing for Current-ModeControl CMOS DC-DC Buck Converter, Electronics, Circuits and Systems, 2008. ICECS 2008.15th IEEE International Conference on

Contents of the invention

In order to overcome the shortcomings of the above-mentioned prior art, the present invention provides a fast and anti-interference current sampling circuit based on a differential structure. The circuit has a simple structure, strong anti-interference ability, and fast sampling speed. Its impact is small.

Technical scheme of the present invention is realized like this:

A fast anti-interference current sampling circuit based on a differential structure, characterized in that: the sampling circuit includes a differential sampling main circuit and a bias voltage generating circuit, and the bias voltage generating circuit generates two different voltages for the sampling main circuit The common gate transistor in the circuit provides gate voltage bias, and the output signal of the main circuit of differential sampling is the anti-interference sampling signal that can be used to control the entire loop or the overcurrent protection circuit.

In the differential sampling main circuit, the high potential of the input power supply is connected to the source of the PMOS transistor Mp, the drain of the PMOS transistor Mp is connected to the drain of the NMOS transistor Mn, and the source of the NMOS transistor Mn is connected to the low potential of the input power supply The connection point of the PMOS transistor Mp and the NMOS transistor Mn is connected to the filter circuit, and the filter circuit is connected to the load resistor R; the source of the PMOS transistor Mp is connected to the PMOS transistor M8, the gate of the PMOS transistor M8 is connected to the low potential of the power supply, and the PMOS transistor M8 The drain is connected to the source of the PMOS transistor M1, the drain of the PMOS transistor M1 is connected to the source of the PMOS transistor M3, and the PMOS transistor M3 adopts a diode connection method, and the gate and the drain are connected to the low potential of the power supply; the drain of the PMOS transistor Mp The pole is connected to the PMOS transistor M9, the gate of the PMOS transistor M9 is connected to the first control signal, the drain of M9 is connected to the source of the PMOS transistor M2, the drain of the PMOS transistor M2 is connected to the source of the PMOS transistor M4, and the PMOS transistor M4 uses a diode Connection method, the gate and drain are connected to the low potential of the power supply; the gate of the PMOS transistor MP is connected to the second control signal, the gate of the NMOS transistor Mn is connected to the third control signal; the source of the PMOS transistor Mpx1 is connected to the input The power supply is at a high potential, the drain of the PMOS transistor Mpx1 is connected to the drain of the PMOS transistor M2, the gate of the PMOS transistor Mpx1 is connected to the fourth control signal, and the gates of the PMOS transistors M1 and M2 are respectively connected to the bias voltages V _b1 and V _b2 ; The sampling signal is differentially output from the sources of the PMOS transistors M3 and M4; the filter circuit is formed by connecting the inductor L and the capacitor C, wherein ESR is the equivalent series resistance of the capacitor C.

In the bias voltage generating circuit, the source of the series connected PMOS transistor M7 is connected to the high potential of the input power supply, the gate is connected to the low potential of the power supply, and the drain is connected to the source end of the PMOS transistor M5, and the PMOS transistor M5 adopts a diode connection method, The gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M1 to provide the bias voltage V _b1 for the PMOS transistor M1, and the bias current source I is connected between the connection point of the gate and the drain of the PMOS transistor M5 and the low potential of the power supply. _b1 ; the source of the series connected PMOS transistor M10 is connected to the high potential of the input power supply, the gate is connected to the low potential of the power supply, and the drain is connected to the source of the PMOS transistor M6, and the PMOS transistor M6 adopts a diode connection method, and the gate of the PMOS transistor M6 is connected to the PMOS transistor M6 The gate connection of the tube M2 provides the bias voltage V _b2 for the PMOS tube M2, and the bias current source I _b2 is connected between the connection point of the gate and the drain of the PMOS tube M6 and the low potential of the power supply; the source of the PMOS tube M6 A current source I _C1 is connected between the pole and the low potential of the power supply.

The timings of the four control signals are different, the rising edge of the second control signal is slightly earlier than the third control signal, and the falling edge of the second control signal is slightly later than the third control signal; the first The control signal is a slightly delayed signal of the second control signal; the fourth control signal is the inverted signal of the first control signal with a slight delay.

Compared with the prior art, the present invention provides a current sampling circuit with strong anti-interference ability, fast sampling speed and simple structure, and provides the circuit applied in voltage mode DC-DC overcurrent protection circuit and current mode DC-DC Scheme in DC loop. The anti-interference and fast characteristics enable the operating frequency of the current mode DC-DC to be further improved.

Description of drawings

Figure 1 is a schematic diagram of a fast anti-interference current sampling circuit based on a differential structure;

Figure 2 is a circuit schematic diagram of a fast anti-interference current sampling circuit based on a differential structure applied in an overcurrent protection function;

Fig. 3 is a circuit schematic diagram of a fast anti-interference current sampling circuit based on a differential structure applied in a current mode DC-DC loop;

Detailed ways

The content of the present invention will be further described below in conjunction with the accompanying drawings.

As shown in Figure 1, the basic principle of the fast anti-interference current sampling circuit based on the differential structure is that the control signal Q_p of the gate of the PMOS transistor Mp first becomes low when sampling starts, and the control signal Q_p_2 of the gate of the PMOS transistor M9 changes slightly later than Q_p. low to avoid sampling signal overshoot, the control signal Q_z of the gate of the PMOS transistor Mpx becomes high, and Mpx is turned off; at this time, the PMOS transistors M8 and M9 are in the linear region, the resistance of M8 is R_M8, and the resistance of M9 is R_M9; Considering the effect of channel length modulation, the following relationship can be obtained:

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">I</figure-callout></span><figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 8</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 3</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

(1)

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; y</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">I</figure-callout></span><figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 9</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 4</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

(2)

Since I _d1 and I _d2 are very small, the above equation can be approximated as:

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 3</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

(3)

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; y</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 4</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

(4)

After the two formulas are opened with the square root sign respectively, both ends are subtracted at the same time, and take

(W/L) ₁ = (W/L) ₂ , (W/L) ₂ = (W/L) ₄

Available:

V _M -V _N =K(V _x -V _y )

(5)

in $K=\sqrt{{(W/L)}_{\mathrm{1,2}}/{(W/L)}_{\mathrm{3,4}}}$

There is a large parasitic capacitance at the source and drain of Mp, and there is a parasitic inductance on the connection from the high potential of the power supply to Mp, and there is a resistance on the connection. When the switch of Mp is activated, the signal on the high potential of the power supply will appear Damping oscillation, due to the large size of Mp, the resistance value is small, there is only a DC voltage drop across the source and drain of Mp, and the signal phase difference between the two ends is very small, the voltage difference between the source and drain of Mp is approximately one The value without oscillation is ΔV, ΔV=R _Mp ×I _L , this difference is output from two points M and N through the amplification network composed of M1, M2, M3, and M4, and the voltage difference between point M and point N is Mp source K times the voltage difference across the drain, this difference is the undisturbed sampling signal of the inductor current, namely:

V _M -V _N ＝K× _RMp ×I _L

(6)

There are only two transistors in the path between the two ends of Mp and the two ends of the output, which makes the signal path have fewer nodes, fewer corresponding poles, and sufficient phase margin; and the RC is small, so the sampling speed is fast .

Referring to FIG. 2, the same parts shown in FIG. 1 are represented by the same symbols. Compared with FIG. 1, the source of the series-connected PMOS transistor M7 is connected to the high potential of the input power supply, the gate is connected to the low potential of the power supply, and the drain is connected to the low potential of the power supply. The source of PMOS tube M5, M7 works in the linear region; M5 adopts the diode connection method, the gate of M5 is connected with the gate of M1 to provide bias voltage V _b1 for M1; the connection between the gate and drain of M5 The bias current source I _b1 is connected between the point and the low potential of the power supply; the source of the series connected PMOS transistor M10 is connected to the high potential of the input power supply, the gate is connected to the low potential of the power supply, and the drain is connected to the source of the PMOS transistor M6, and M10 works online M6 uses a diode connection method, the gate of M6 is connected to the gate of M2 to provide a bias voltage V _b2 for M2, and the bias current source is connected between the connection point of the gate and drain of M6 and the low potential of the power supply I _b2 , requires I _b1 =I _b2 ; connect the non-inverting input terminal of the comparator CP at point M, connect the inverting input terminal of CP at point N, and connect a current flow to the low potential of the power supply between the source of M6 and the low potential of the power supply The potential constant current source I _C1 , when I _C1 is connected, V _b1 ≠ V _b2 , the following relationship can be obtained by analogy with the basic structure:

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">I</figure-callout></span><figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 8</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

(7)

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; y</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">I</figure-callout></span><figure-callout\; id="2"\; label="I\; d"\; filenames="HDA0000029926880000012.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 9</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 4</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; THP</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

(8)

Using the approximations and transistor scaling used in deriving the basic structure, we get:

V _M -V _N ＝K(V _x -V _y )-K(V _b1 -V _b2 )

(9)

Among them, V _b2 is lower than V _b1 by I _C1 × R _M10 ; the increase of inductor current reduces the voltage of point N, and when the voltage of point N is as low as that of point M, the comparator will flip over, that is:

V _x -V _y =V _b1 -V _b2 (10)

I _L ×R _Mp =I _C1 ×R _M10

(11)

The threshold of overcurrent protection is set by setting the value of I _C1 . When the inductor current increases to the point where the comparator is reversed, the comparator output controls the switch to turn off to realize the function of overcurrent protection.

Referring to FIG. 3, the same parts shown in FIG. 2 are denoted by the same symbols. Compared with Figure 2, in Figure 3, feedback resistors R1 and R2 are connected in series at Vout, the node connected between R1 and R2 is used as the inverting input terminal of EA, Vref is used as the non-inverting input terminal of EA, and the output of EA is connected to the compensation The network is then connected to a voltage-to-current converter v to i, and the slope compensation voltage Ramp Signal is also connected to a v to i. The sum of the two parts of the current provides I _C2 through the current mirror, and I _C2 is connected to the source of M6. Between the low potential of the power supply, the M point and the N point are connected to the comparator CMP, the output of the CMP is connected to the input of the pulse generation module Pulse Width Generator, and the output of the Pulse Width Generator controls the gates of Mp, Mn, Mpx, and M9 through the buffer Buffer pole, when the voltages of point M and point N are equal, the comparator reverses and outputs a control signal to control the action of the switch tube, thereby realizing the control function of the current mode DC-DC current loop.

Claims (2)

1. A fast anti-jamming current sampling circuit based on a differential structure, characterized in that: the sampling circuit includes a differential sampling main circuit and a bias voltage generation circuit, and two different voltages are produced by the bias voltage to the sampling main circuit The common gate transistor, the main circuit output signal of differential sampling is the anti-interference sampling signal that controls the entire loop or overcurrent protection circuit; the main circuit of differential sampling is connected to the source of PMOS tube Mp by the high potential of the input power supply The drain of the PMOS transistor Mp is connected to the drain of the NMOS transistor Mn, and the source of the NMOS transistor Mn is connected to the low potential of the input power supply; the connection point of the PMOS transistor Mp and the NMOS transistor Mn is connected to the filter circuit, and the filter circuit is connected to Load resistor R; the source of the PMOS transistor Mp is connected to the PMOS transistor M8, the gate of the PMOS transistor M8 is connected to the low potential of the power supply, the drain of the PMOS transistor M8 is connected to the source of the PMOS transistor M1, and the drain of the PMOS transistor M1 is connected to the PMOS transistor M3 The source of the PMOS transistor M3 adopts a diode connection method, and the gate and drain are connected to the low potential of the power supply; the drain of the PMOS transistor Mp is connected to the source of the PMOS transistor M9, and the gate of the PMOS transistor M9 is connected to the first control signal, the drain of M9 is connected to the source of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the source of PMOS transistor M4, and PMOS transistor M4 adopts a diode connection method, and the gate and drain are connected to the low potential of the power supply; PMOS The gate of the tube Mp is connected to the second control signal, the gate of the NMOS tube Mn is connected to the third control signal; the source of the PMOS tube Mpx1 is connected to the high potential of the input power supply, and the drain of the PMOS tube Mpx1 is connected to the source of the PMOS tube M2 , the gate of the PMOS transistor Mpx1 is connected to the fourth control signal, and the gates of the PMOS transistors M1 and M2 are connected to the bias voltages V _b1 and V _b2 respectively; the sampling signal is differentially output from the sources of the PMOS transistors M3 and M4; The filter circuit is formed by connecting an inductance L and a capacitor C, and the capacitor C has an equivalent series resistance ESR; the bias voltage generation circuit is connected to the high potential of the input power supply by the source of the series-connected PMOS transistor M7, and the gate is connected to The power supply is at a low potential, and the drain is connected to the source end of the PMOS transistor M5. The PMOS transistor M5 adopts a diode connection method, and the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M1 to provide a bias voltage V _b1 for the PMOS transistor M1. A bias current source I _b1 is connected between the connection point of the gate and the drain of M5 and the low potential of the power supply; the source of the series connected PMOS transistor M10 is connected to the high potential of the input power supply, the gate is connected to the low potential of the power supply, and the drain is connected to the PMOS The source of the transistor M6, the PMOS transistor M6 adopts a diode connection method, the gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M2 to provide a bias voltage V _b2 for the PMOS transistor M2, and the gate and drain of the PMOS transistor M6 Connect the bias current source I _b2 between the connection point and the low potential of the power supply; at the source of the PMOS transistor M6 Connect a current source I _C1 to the low potential of the power supply. 2. The fast anti-interference current sampling circuit based on differential structure according to claim 1, characterized in that: the timings of the four control signals are different, and the rising edge of the second control signal is slightly earlier than the third The falling edge of the second control signal is slightly later than the third control signal; the first control signal is a slightly delayed signal of the second control signal; the fourth control signal is the inverse of the first control signal phase signal with a slight delay.

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