CN101980149B - Main processor and coprocessor communication system and communication method - Google Patents

Abstract

The present invention discloses a communication system between a main processor and a coprocessor. The system includes: a main processor, which sends command words and control words; a communication storage module, which stores the command words sent by the main processor; a communication control module , receiving the control word sent by the main processor and sending a control signal; the coprocessor interrupt control module receiving the control signal and sending an interrupt signal; and the coprocessor, after receiving the interrupt signal, from the communication storage module Get the command word. Compared with the prior art, the present invention changes the design mode of the traditional coprocessor, adopts the mode of direct communication, realizes the communication between the main processor and the coprocessor through the predefined command word, makes the main processor and the coprocessor Communication between coprocessors is more convenient and efficient.

Description

Main processor and coprocessor communication system and communication method

【Technical field】

The invention relates to the field of chip design, in particular to the communication technology between the main processor and the co-processor.

【Background technique】

In the existing electronic product industry, the development cycle of new products is required to be shorter and shorter. If the product solution design manufacturer already has relatively mature and fixed hardware architecture and software architecture, when launching a new product, the main control chip is often not replaced, because replacing the main control chip means that the hardware architecture and software architecture of the entire system need to be changed. Make big changes. When implementing new functionality, it is often chosen to complement it with a coprocessor. The main processor is the main processing chip in the system and is used to control the entire workflow of the system. Coprocessors can assist the main processor to complete certain functions and have certain computing execution capabilities. For example, a math coprocessor can control digital processing, and a graphics coprocessor can handle video rendering.

Due to the need for cooperation, data transmission between the main processor and the coprocessor needs to be carried out in a certain way, that is, communication between the main processor and the coprocessor. The traditional main processor mainly achieves the purpose of controlling the coprocessor by operating registers and memory as a shared storage area, but in this way, the main processor cannot directly send interrupt signals to the coprocessor, but through registers and memory. The coprocessor is driven to perform functions, and the coprocessor cannot directly send interrupts to the main processor, but sends interrupts to the main processor through the functional modules of the coprocessor. This causes problems such as difficult communication between the main processor and the co-processor, passive co-processor, and slow communication speed in the existing communication system.

Therefore, it is necessary to propose a new technical solution to solve the above-mentioned shortcoming.

【Content of invention】

The purpose of this section is to outline some aspects of embodiments of the invention and briefly describe some preferred embodiments. Some simplifications or omissions may be made in this section, as well as in the abstract and titles of this application, to avoid obscuring the purpose of this section, the abstract and titles, and such simplifications or omissions should not be used to limit the scope of the invention.

An object of the present invention is to provide a new communication system between a main processor and a coprocessor.

Another object of the present invention is to provide a new communication method between the main processor and the co-processor system.

In order to achieve the purpose of the present invention, according to an aspect of the present invention, the present invention provides a kind of new main processor and coprocessor communication system, described system comprises: main processor, sends order word and control word; Communication memory module , store the command word sent by the main processor; the communication control module receives the control word sent by the main processor and sends a control signal; the coprocessor interrupt control module receives the control signal and sends an interrupt signal; and the coprocessor The processor obtains the command word from the communication storage module after receiving an interrupt signal.

Further, the system further includes a unified access interface, through which the main processor accesses the communication storage module and the communication control module.

Further, the communication storage module is a shared memory area or register accessible to both the main processor and the coprocessor.

Further, the communication control module is a register capable of directly controlling the coprocessor interrupt control module.

Further, the system also includes a registered interrupt controller, the coprocessor executes the corresponding command after obtaining the command word, and when it needs to send a command reply, status information or execution result, the command reply, status Information or execution results are stored in the communication storage module, and an interrupt request is issued through the registered interrupt controller.

Further, the system further includes a main processor interrupt control module, and the main processor interrupt control module sends an interrupt signal to the main processor after receiving the interrupt request.

Further, the registered interrupt controller, communication storage module, communication control module, coprocessor interrupt control module and coprocessor all belong to a coprocessor system.

Further, the interrupt signal giving method of the registered interrupt controller matches the interrupt triggering method of the main processor interrupt control module.

According to another aspect of the present invention, the present invention provides a new communication method between a main processor and a coprocessor system, the method comprising:

Setting the register capable of controlling the coprocessor interrupt control module in the coprocessor system as the communication control module;

Set the shared memory or register in the coprocessor system as a communication storage module;

The main processor sends a control word to the communication control module and a command word to the communication storage module through a unified access interface;

The communication control module sends a control signal to the coprocessor interrupt control module after receiving the control word;

The coprocessor interrupt control module sends an interrupt signal to the coprocessor; and

The coprocessor acquires the command word from the communication storage module and executes it.

Further, the command word and control word are predefined.

Furthermore, when it is necessary to send command replies, status information or execution results,

The coprocessor stores the command reply, status information or execution result in the communication storage module;

The coprocessor sends an interrupt request to the main processor interrupt control module by registering the interrupt controller;

The main processor interrupt control module sends an interrupt signal to the main processor; and

The main processor obtains the command reply, status information or execution result from the communication storage module.

Compared with the prior art, the present invention changes the design mode of the traditional coprocessor, adopts the mode of direct communication, realizes the communication between the main processor and the coprocessor through the predefined command word, makes the main processor and the coprocessor Communication between coprocessors is more convenient and efficient.

【Description of drawings】

The present invention will be better understood with reference to the accompanying drawings and the ensuing detailed description, wherein like reference numerals correspond to like structural components, wherein:

FIG. 1 is a schematic structural diagram of a communication system between a main processor and a coprocessor in an embodiment of the present invention. and

FIG. 2 is a method flowchart of a communication method between a main processor and a coprocessor in an embodiment of the present invention.

【Detailed ways】

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

The main processor and coprocessor communication system and communication method of the present invention use predefined command words to communicate, instead of using the main processor operation register and memory in the prior art as a shared storage area to achieve control co-processing device technical solutions. However, the main processor and co-processor communication system and communication method of the present invention can be implemented in a combination of software and hardware alone, or can coexist with technical solutions in the prior art, and exist in a system at the same time.

Please refer to FIG. 1 , which shows a structural block diagram of a communication system 100 between a main processor and a coprocessor in an embodiment of the present invention. The main processor and coprocessor communication system 100 mainly includes a main processing system 120 , a coprocessing system 140 and a unified access interface 160 .

The main processing system 120 includes a main processor 121 and a main processor interrupt control module 122 .

The coprocessing system 140 includes a coprocessor 141 , a coprocessor interrupt control module 142 , a communication control module 143 , a communication storage module 144 and a registered interrupt controller 145 .

The main processor 121 accesses and controls the co-processing system 140 through the unified access interface 160 . The unified access interface 160 may be a host access interface (Host Access Interface, HAI) in the standard bus interface. When the main processor 121 needs to communicate with the coprocessor 141 , it can send a control word to the communication control module 143 and a command word to the communication storage module 144 through the unified access interface 160 . The control word and the command word are predefined signals that can be recognized and executed by the main processor 121 and the coprocessor 141 .

The communication control module 143 may be a register in the coprocessor system 140 that can directly control the coprocessor interrupt control module 142 . The main processor 121 can send a control word to change the internal state of the communication control module 143 to achieve the purpose of controlling the coprocessor interrupt control module 142 .

The communication storage module 144 may be a shared memory area or a register in the co-processing system 140 . Both the main processor 121 and the coprocessor 141 can access the communication storage module 144 . The communication storage module 144 is used for storing command words sent by the main processor 121 .

The coprocessor interrupt control module 142 can be controlled by the communication control module 143, and when the communication control module 143 receives the control word sent by the main processor 141, it sends a control signal to the coprocessor interrupt The control module 142 , the coprocessor interrupt control module 142 further sends an interrupt signal to the coprocessor 141 . After receiving the interrupt signal, the coprocessor 141 obtains the command word from the communication storage module 144 for execution.

Different from the traditional scheme in which the main processor 121 continuously inquires about the working status of the coprocessor 141, in this embodiment, the coprocessor 141 controls the coprocessor 145 by controlling the registered interrupt controller 145 These predetermined external pins are connected to the external interrupt source of the main processor 121, so that the purpose of the coprocessor 141 actively sending an interrupt to the main processor 121 can be achieved. The coprocessor 141 executes the corresponding command after obtaining the command word, and stores the command reply, status information or execution result in the communication storage module 144 when it needs to send a command reply, status information or execution result. , and send an interrupt request to the main processor interrupt control module 122 through the registered interrupt controller 145, and the main processor interrupt control module 122 receives the interrupt request and then sends an interrupt signal to the main processor 121, The main processor 121 can obtain the command reply, status information or execution result of the coprocessor 141 from the communication storage module 144 .

It should be recognized that the main processor 121 sends an interrupt to the coprocessor 141 through the communication control module 143, and as the coprocessor 141 normally handles an interrupt request, no special processing is required, so the coprocessor is reduced. 141 complexities. The coprocessor 141 can actively send an interrupt to the main processor 121 through the registered interrupt controller 145, so that the main processor 121 can obtain the command reply and status information of the coprocessor 141 as soon as possible. Or execute the result, making the communication between the main processor and the coprocessor more convenient and efficient.

The present invention also proposes a communication method between a main processor and a coprocessor system, please refer to FIG. 2 , which shows a method flow chart of a communication method 200 between a main processor and a coprocessor in an embodiment of the present invention . The main processor and the coprocessor communication method 200 first set the register that can control the coprocessor interrupt control module in the coprocessor system as the communication control module; set the shared memory or the register in the coprocessor system as Communication storage module. At the same time, the command word and control word for communication between the two are also predefined. The communication method 200 between the main processor and the coprocessor includes:

Step 201, the main processor sends a control word to the communication control module and a command word to the communication storage module through a unified access interface;

Step 202, the communication control module sends a control signal to the coprocessor interrupt control module after receiving the control word;

Step 203, the coprocessor interrupt control module sends an interrupt signal to the coprocessor;

Step 204, the coprocessor obtains the command word from the communication storage module and executes it.

Step 205, judge whether the coprocessor needs to send command reply, status information or execution result, if yes, go to step 206, if not, go to step 210, end this communication.

Step 206, the coprocessor stores the command reply, status information or execution result in the communication storage module;

Step 207, the coprocessor sends an interrupt request to the main processor interrupt control module through the registered interrupt controller;

Step 208, the main processor interrupt control module sends an interrupt signal to the main processor after receiving the interrupt request; and

Step 209, the main processor acquires the command reply, status information or execution result from the communication storage module.

The above description has fully disclosed the specific implementation manners of the present invention. It should be pointed out that any changes made by those skilled in the art to the specific embodiments of the present invention will not depart from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited only to the specific embodiments described.

Claims (8)

1. a primary processor and coprocessor communication system is characterized in that, it comprises:

Primary processor sends command word and control word;

The communication memory module is stored the command word that described primary processor sends;

Communication control module receives the control word of described primary processor transmission and sends control signal;

Coprocessor interrupts control module, receives described control signal and sends look-at-me; With

Coprocessor obtains described command word from described communication memory module after receiving look-at-me;

Described system also comprises the registration interruptable controller, described coprocessor is carried out the corresponding command after getting access to described command word, when needs send order answer, status information or execution result, described order answer, status information or execution result are stored in described communication memory module, and send interrupt request by described registration interruptable controller.

2. system according to claim 1 is characterized in that, described system also comprises unified access interface, and described primary processor is accessed described communication memory module and communication control module by described unified access interface.

3. system according to claim 1 is characterized in that, described communication memory module is described primary processor and described coprocessor all addressable a slice shared drive zone or register.

4. system according to claim 1 is characterized in that, described communication control module interrupts the register of control module for can directly controlling described coprocessor.

5. system according to claim 1 is characterized in that, described system comprises that also primary processor interrupts control module, and described primary processor interrupts sending look-at-me to described primary processor after control module receives described interrupt request.

6. system according to claim 1 is characterized in that, described registration interruptable controller, communication memory module, communication control module, coprocessor interruption control module and coprocessor belong to a coprocessor system.

7. system according to claim 5 is characterized in that, the down trigger mode that the look-at-me of described registration interruptable controller provides mode and described primary processor interruption control module is complementary.

8. the communication means of a primary processor and coprocessor system is characterized in that, it comprises:

The register that can control coprocessor interruption control module in the coprocessor system is set as communication control module;

Shared drive in the coprocessor system or register are set as the communication memory module;

Primary processor by unified access interface send control word to described communication control module and transmission command word to the described memory module of communicating by letter;

Described communication control module transmits control signal after receiving control word and interrupts control module to described coprocessor;

Described coprocessor interrupts control module and sends look-at-me to coprocessor; With

Described coprocessor obtains described command word and execution from the communication memory module,

When needs send order answer, status information or execution result,

Described coprocessor is stored in described communication memory module with described order answer, status information or execution result;

Described coprocessor sends interrupt request by the registration interruptable controller and interrupts control module to primary processor;

Described primary processor interrupts control module and sends look-at-me to described primary processor; With

Described primary processor obtains described order answer, status information or execution result from the communication memory module.

9. method according to claim 8 is characterized in that, described command word and control word are predefined.

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